pci/hotplug/pciehp.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * PCI Express Hot Plug Controller Driver
0004  *
0005  * Copyright (C) 1995,2001 Compaq Computer Corporation
0006  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
0007  * Copyright (C) 2001 IBM Corp.
0008  * Copyright (C) 2003-2004 Intel Corporation
0009  *
0010  * All rights reserved.
0011  *
0012  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
0013  *
0014  */
0015 #ifndef _PCIEHP_H
0016 #define _PCIEHP_H
0017
0018 #include <linux/types.h>
0019 #include <linux/pci.h>
0020 #include <linux/pci_hotplug.h>
0021 #include <linux/delay.h>
0022 #include <linux/mutex.h>
0023 #include <linux/rwsem.h>
0024 #include <linux/workqueue.h>
0025
0026 #include "../pcie/portdrv.h"
0027
0028 extern bool pciehp_poll_mode;
0029 extern int pciehp_poll_time;
0030
0031 /*
0032  * Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to
0033  * enable debug messages.
0034  */
0035 #define ctrl_dbg(ctrl, format, arg...)                  \
0036     pci_dbg(ctrl->pcie->port, format, ## arg)
0037 #define ctrl_err(ctrl, format, arg...)                  \
0038     pci_err(ctrl->pcie->port, format, ## arg)
0039 #define ctrl_info(ctrl, format, arg...)                 \
0040     pci_info(ctrl->pcie->port, format, ## arg)
0041 #define ctrl_warn(ctrl, format, arg...)                 \
0042     pci_warn(ctrl->pcie->port, format, ## arg)
0043
0044 #define SLOT_NAME_SIZE 10
0045
0046 /**
0047  * struct controller - PCIe hotplug controller
0048  * @pcie: pointer to the controller's PCIe port service device
0049  * @slot_cap: cached copy of the Slot Capabilities register
0050  * @inband_presence_disabled: In-Band Presence Detect Disable supported by
0051  *  controller and disabled per spec recommendation (PCIe r5.0, appendix I
0052  *  implementation note)
0053  * @slot_ctrl: cached copy of the Slot Control register
0054  * @ctrl_lock: serializes writes to the Slot Control register
0055  * @cmd_started: jiffies when the Slot Control register was last written;
0056  *  the next write is allowed 1 second later, absent a Command Completed
0057  *  interrupt (PCIe r4.0, sec 6.7.3.2)
0058  * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
0059  *  on reception of a Command Completed event
0060  * @queue: wait queue to wake up on reception of a Command Completed event,
0061  *  used for synchronous writes to the Slot Control register
0062  * @pending_events: used by the IRQ handler to save events retrieved from the
0063  *  Slot Status register for later consumption by the IRQ thread
0064  * @notification_enabled: whether the IRQ was requested successfully
0065  * @power_fault_detected: whether a power fault was detected by the hardware
0066  *  that has not yet been cleared by the user
0067  * @poll_thread: thread to poll for slot events if no IRQ is available,
0068  *  enabled with pciehp_poll_mode module parameter
0069  * @state: current state machine position
0070  * @state_lock: protects reads and writes of @state;
0071  *  protects scheduling, execution and cancellation of @button_work
0072  * @button_work: work item to turn the slot on or off after 5 seconds
0073  *  in response to an Attention Button press
0074  * @hotplug_slot: structure registered with the PCI hotplug core
0075  * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
0076  *  Link Status register and to the Presence Detect State bit in the Slot
0077  *  Status register during a slot reset which may cause them to flap
0078  * @depth: Number of additional hotplug ports in the path to the root bus,
0079  *  used as lock subclass for @reset_lock
0080  * @ist_running: flag to keep user request waiting while IRQ thread is running
0081  * @request_result: result of last user request submitted to the IRQ thread
0082  * @requester: wait queue to wake up on completion of user request,
0083  *  used for synchronous slot enable/disable request via sysfs
0084  *
0085  * PCIe hotplug has a 1:1 relationship between controller and slot, hence
0086  * unlike other drivers, the two aren't represented by separate structures.
0087  */
0088 struct controller {
0089     struct pcie_device *pcie;
0090
0091     u32 slot_cap;               /* capabilities and quirks */
0092     unsigned int inband_presence_disabled:1;
0093
0094     u16 slot_ctrl;              /* control register access */
0095     struct mutex ctrl_lock;
0096     unsigned long cmd_started;
0097     unsigned int cmd_busy:1;
0098     wait_queue_head_t queue;
0099
0100     atomic_t pending_events;        /* event handling */
0101     unsigned int notification_enabled:1;
0102     unsigned int power_fault_detected;
0103     struct task_struct *poll_thread;
0104
0105     u8 state;               /* state machine */
0106     struct mutex state_lock;
0107     struct delayed_work button_work;
0108
0109     struct hotplug_slot hotplug_slot;   /* hotplug core interface */
0110     struct rw_semaphore reset_lock;
0111     unsigned int depth;
0112     unsigned int ist_running;
0113     int request_result;
0114     wait_queue_head_t requester;
0115 };
0116
0117 /**
0118  * DOC: Slot state
0119  *
0120  * @OFF_STATE: slot is powered off, no subordinate devices are enumerated
0121  * @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
0122  *  Power Indicator is blinking
0123  * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
0124  *  Power Indicator is blinking
0125  * @POWERON_STATE: slot is currently powering on
0126  * @POWEROFF_STATE: slot is currently powering off
0127  * @ON_STATE: slot is powered on, subordinate devices have been enumerated
0128  */
0129 #define OFF_STATE           0
0130 #define BLINKINGON_STATE        1
0131 #define BLINKINGOFF_STATE       2
0132 #define POWERON_STATE           3
0133 #define POWEROFF_STATE          4
0134 #define ON_STATE            5
0135
0136 /**
0137  * DOC: Flags to request an action from the IRQ thread
0138  *
0139  * These are stored together with events read from the Slot Status register,
0140  * hence must be greater than its 16-bit width.
0141  *
0142  * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
0143  *  an Attention Button press after the 5 second delay
0144  * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
0145  *  hotplug port was inaccessible when the interrupt occurred, requiring
0146  *  that the IRQ handler is rerun by the IRQ thread after it has made the
0147  *  hotplug port accessible by runtime resuming its parents to D0
0148  */
0149 #define DISABLE_SLOT        (1 << 16)
0150 #define RERUN_ISR       (1 << 17)
0151
0152 #define ATTN_BUTTN(ctrl)    ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
0153 #define POWER_CTRL(ctrl)    ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
0154 #define MRL_SENS(ctrl)      ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
0155 #define ATTN_LED(ctrl)      ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
0156 #define PWR_LED(ctrl)       ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
0157 #define NO_CMD_CMPL(ctrl)   ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
0158 #define PSN(ctrl)       (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
0159
0160 void pciehp_request(struct controller *ctrl, int action);
0161 void pciehp_handle_button_press(struct controller *ctrl);
0162 void pciehp_handle_disable_request(struct controller *ctrl);
0163 void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
0164 int pciehp_configure_device(struct controller *ctrl);
0165 void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
0166 void pciehp_queue_pushbutton_work(struct work_struct *work);
0167 struct controller *pcie_init(struct pcie_device *dev);
0168 int pcie_init_notification(struct controller *ctrl);
0169 void pcie_shutdown_notification(struct controller *ctrl);
0170 void pcie_clear_hotplug_events(struct controller *ctrl);
0171 void pcie_enable_interrupt(struct controller *ctrl);
0172 void pcie_disable_interrupt(struct controller *ctrl);
0173 int pciehp_power_on_slot(struct controller *ctrl);
0174 void pciehp_power_off_slot(struct controller *ctrl);
0175 void pciehp_get_power_status(struct controller *ctrl, u8 *status);
0176
0177 #define INDICATOR_NOOP -1   /* Leave indicator unchanged */
0178 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn);
0179
0180 void pciehp_get_latch_status(struct controller *ctrl, u8 *status);
0181 int pciehp_query_power_fault(struct controller *ctrl);
0182 int pciehp_card_present(struct controller *ctrl);
0183 int pciehp_card_present_or_link_active(struct controller *ctrl);
0184 int pciehp_check_link_status(struct controller *ctrl);
0185 int pciehp_check_link_active(struct controller *ctrl);
0186 void pciehp_release_ctrl(struct controller *ctrl);
0187
0188 int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot);
0189 int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot);
0190 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe);
0191 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status);
0192 int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
0193 int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
0194
0195 int pciehp_slot_reset(struct pcie_device *dev);
0196
0197 static inline const char *slot_name(struct controller *ctrl)
0198 {
0199     return hotplug_slot_name(&ctrl->hotplug_slot);
0200 }
0201
0202 static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot)
0203 {
0204     return container_of(hotplug_slot, struct controller, hotplug_slot);
0205 }
0206
0207 #endif              /* _PCIEHP_H */