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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * IBM Hot Plug Controller Driver
0004  *
0005  * Written By: Jyoti Shah, IBM Corporation
0006  *
0007  * Copyright (C) 2001-2003 IBM Corp.
0008  *
0009  * All rights reserved.
0010  *
0011  * Send feedback to <gregkh@us.ibm.com>
0012  *                  <jshah@us.ibm.com>
0013  *
0014  */
0015 
0016 #include <linux/wait.h>
0017 #include <linux/time.h>
0018 #include <linux/completion.h>
0019 #include <linux/delay.h>
0020 #include <linux/module.h>
0021 #include <linux/pci.h>
0022 #include <linux/init.h>
0023 #include <linux/mutex.h>
0024 #include <linux/sched.h>
0025 #include <linux/kthread.h>
0026 #include "ibmphp.h"
0027 
0028 static int to_debug = 0;
0029 #define debug_polling(fmt, arg...)  do { if (to_debug) debug(fmt, arg); } while (0)
0030 
0031 //----------------------------------------------------------------------------
0032 // timeout values
0033 //----------------------------------------------------------------------------
0034 #define CMD_COMPLETE_TOUT_SEC   60  // give HPC 60 sec to finish cmd
0035 #define HPC_CTLR_WORKING_TOUT   60  // give HPC 60 sec to finish cmd
0036 #define HPC_GETACCESS_TIMEOUT   60  // seconds
0037 #define POLL_INTERVAL_SEC   2   // poll HPC every 2 seconds
0038 #define POLL_LATCH_CNT      5   // poll latch 5 times, then poll slots
0039 
0040 //----------------------------------------------------------------------------
0041 // Winnipeg Architected Register Offsets
0042 //----------------------------------------------------------------------------
0043 #define WPG_I2CMBUFL_OFFSET 0x08    // I2C Message Buffer Low
0044 #define WPG_I2CMOSUP_OFFSET 0x10    // I2C Master Operation Setup Reg
0045 #define WPG_I2CMCNTL_OFFSET 0x20    // I2C Master Control Register
0046 #define WPG_I2CPARM_OFFSET  0x40    // I2C Parameter Register
0047 #define WPG_I2CSTAT_OFFSET  0x70    // I2C Status Register
0048 
0049 //----------------------------------------------------------------------------
0050 // Winnipeg Store Type commands (Add this commands to the register offset)
0051 //----------------------------------------------------------------------------
0052 #define WPG_I2C_AND     0x1000  // I2C AND operation
0053 #define WPG_I2C_OR      0x2000  // I2C OR operation
0054 
0055 //----------------------------------------------------------------------------
0056 // Command set for I2C Master Operation Setup Register
0057 //----------------------------------------------------------------------------
0058 #define WPG_READATADDR_MASK 0x00010000  // read,bytes,I2C shifted,index
0059 #define WPG_WRITEATADDR_MASK    0x40010000  // write,bytes,I2C shifted,index
0060 #define WPG_READDIRECT_MASK 0x10010000
0061 #define WPG_WRITEDIRECT_MASK    0x60010000
0062 
0063 
0064 //----------------------------------------------------------------------------
0065 // bit masks for I2C Master Control Register
0066 //----------------------------------------------------------------------------
0067 #define WPG_I2CMCNTL_STARTOP_MASK   0x00000002  // Start the Operation
0068 
0069 //----------------------------------------------------------------------------
0070 //
0071 //----------------------------------------------------------------------------
0072 #define WPG_I2C_IOREMAP_SIZE    0x2044  // size of linear address interval
0073 
0074 //----------------------------------------------------------------------------
0075 // command index
0076 //----------------------------------------------------------------------------
0077 #define WPG_1ST_SLOT_INDEX  0x01    // index - 1st slot for ctlr
0078 #define WPG_CTLR_INDEX      0x0F    // index - ctlr
0079 #define WPG_1ST_EXTSLOT_INDEX   0x10    // index - 1st ext slot for ctlr
0080 #define WPG_1ST_BUS_INDEX   0x1F    // index - 1st bus for ctlr
0081 
0082 //----------------------------------------------------------------------------
0083 // macro utilities
0084 //----------------------------------------------------------------------------
0085 // if bits 20,22,25,26,27,29,30 are OFF return 1
0086 #define HPC_I2CSTATUS_CHECK(s)  ((u8)((s & 0x00000A76) ? 0 : 1))
0087 
0088 //----------------------------------------------------------------------------
0089 // global variables
0090 //----------------------------------------------------------------------------
0091 static DEFINE_MUTEX(sem_hpcaccess); // lock access to HPC
0092 static DEFINE_MUTEX(operations_mutex);  // lock all operations and
0093                     // access to data structures
0094 static DECLARE_COMPLETION(exit_complete); // make sure polling thread goes away
0095 static struct task_struct *ibmphp_poll_thread;
0096 //----------------------------------------------------------------------------
0097 // local function prototypes
0098 //----------------------------------------------------------------------------
0099 static u8 i2c_ctrl_read(struct controller *, void __iomem *, u8);
0100 static u8 i2c_ctrl_write(struct controller *, void __iomem *, u8, u8);
0101 static u8 hpc_writecmdtoindex(u8, u8);
0102 static u8 hpc_readcmdtoindex(u8, u8);
0103 static void get_hpc_access(void);
0104 static void free_hpc_access(void);
0105 static int poll_hpc(void *data);
0106 static int process_changeinstatus(struct slot *, struct slot *);
0107 static int process_changeinlatch(u8, u8, struct controller *);
0108 static int hpc_wait_ctlr_notworking(int, struct controller *, void __iomem *, u8 *);
0109 //----------------------------------------------------------------------------
0110 
0111 
0112 /*----------------------------------------------------------------------
0113 * Name:    i2c_ctrl_read
0114 *
0115 * Action:  read from HPC over I2C
0116 *
0117 *---------------------------------------------------------------------*/
0118 static u8 i2c_ctrl_read(struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index)
0119 {
0120     u8 status;
0121     int i;
0122     void __iomem *wpg_addr; // base addr + offset
0123     unsigned long wpg_data; // data to/from WPG LOHI format
0124     unsigned long ultemp;
0125     unsigned long data; // actual data HILO format
0126 
0127     debug_polling("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index);
0128 
0129     //--------------------------------------------------------------------
0130     // READ - step 1
0131     // read at address, byte length, I2C address (shifted), index
0132     // or read direct, byte length, index
0133     if (ctlr_ptr->ctlr_type == 0x02) {
0134         data = WPG_READATADDR_MASK;
0135         // fill in I2C address
0136         ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
0137         ultemp = ultemp >> 1;
0138         data |= (ultemp << 8);
0139 
0140         // fill in index
0141         data |= (unsigned long)index;
0142     } else if (ctlr_ptr->ctlr_type == 0x04) {
0143         data = WPG_READDIRECT_MASK;
0144 
0145         // fill in index
0146         ultemp = (unsigned long)index;
0147         ultemp = ultemp << 8;
0148         data |= ultemp;
0149     } else {
0150         err("this controller type is not supported \n");
0151         return HPC_ERROR;
0152     }
0153 
0154     wpg_data = swab32(data);    // swap data before writing
0155     wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
0156     writel(wpg_data, wpg_addr);
0157 
0158     //--------------------------------------------------------------------
0159     // READ - step 2 : clear the message buffer
0160     data = 0x00000000;
0161     wpg_data = swab32(data);
0162     wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
0163     writel(wpg_data, wpg_addr);
0164 
0165     //--------------------------------------------------------------------
0166     // READ - step 3 : issue start operation, I2C master control bit 30:ON
0167     //                 2020 : [20] OR operation at [20] offset 0x20
0168     data = WPG_I2CMCNTL_STARTOP_MASK;
0169     wpg_data = swab32(data);
0170     wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
0171     writel(wpg_data, wpg_addr);
0172 
0173     //--------------------------------------------------------------------
0174     // READ - step 4 : wait until start operation bit clears
0175     i = CMD_COMPLETE_TOUT_SEC;
0176     while (i) {
0177         msleep(10);
0178         wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
0179         wpg_data = readl(wpg_addr);
0180         data = swab32(wpg_data);
0181         if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
0182             break;
0183         i--;
0184     }
0185     if (i == 0) {
0186         debug("%s - Error : WPG timeout\n", __func__);
0187         return HPC_ERROR;
0188     }
0189     //--------------------------------------------------------------------
0190     // READ - step 5 : read I2C status register
0191     i = CMD_COMPLETE_TOUT_SEC;
0192     while (i) {
0193         msleep(10);
0194         wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
0195         wpg_data = readl(wpg_addr);
0196         data = swab32(wpg_data);
0197         if (HPC_I2CSTATUS_CHECK(data))
0198             break;
0199         i--;
0200     }
0201     if (i == 0) {
0202         debug("ctrl_read - Exit Error:I2C timeout\n");
0203         return HPC_ERROR;
0204     }
0205 
0206     //--------------------------------------------------------------------
0207     // READ - step 6 : get DATA
0208     wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
0209     wpg_data = readl(wpg_addr);
0210     data = swab32(wpg_data);
0211 
0212     status = (u8) data;
0213 
0214     debug_polling("%s - Exit index[%x] status[%x]\n", __func__, index, status);
0215 
0216     return (status);
0217 }
0218 
0219 /*----------------------------------------------------------------------
0220 * Name:    i2c_ctrl_write
0221 *
0222 * Action:  write to HPC over I2C
0223 *
0224 * Return   0 or error codes
0225 *---------------------------------------------------------------------*/
0226 static u8 i2c_ctrl_write(struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd)
0227 {
0228     u8 rc;
0229     void __iomem *wpg_addr; // base addr + offset
0230     unsigned long wpg_data; // data to/from WPG LOHI format
0231     unsigned long ultemp;
0232     unsigned long data; // actual data HILO format
0233     int i;
0234 
0235     debug_polling("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd);
0236 
0237     rc = 0;
0238     //--------------------------------------------------------------------
0239     // WRITE - step 1
0240     // write at address, byte length, I2C address (shifted), index
0241     // or write direct, byte length, index
0242     data = 0x00000000;
0243 
0244     if (ctlr_ptr->ctlr_type == 0x02) {
0245         data = WPG_WRITEATADDR_MASK;
0246         // fill in I2C address
0247         ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr;
0248         ultemp = ultemp >> 1;
0249         data |= (ultemp << 8);
0250 
0251         // fill in index
0252         data |= (unsigned long)index;
0253     } else if (ctlr_ptr->ctlr_type == 0x04) {
0254         data = WPG_WRITEDIRECT_MASK;
0255 
0256         // fill in index
0257         ultemp = (unsigned long)index;
0258         ultemp = ultemp << 8;
0259         data |= ultemp;
0260     } else {
0261         err("this controller type is not supported \n");
0262         return HPC_ERROR;
0263     }
0264 
0265     wpg_data = swab32(data);    // swap data before writing
0266     wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET;
0267     writel(wpg_data, wpg_addr);
0268 
0269     //--------------------------------------------------------------------
0270     // WRITE - step 2 : clear the message buffer
0271     data = 0x00000000 | (unsigned long)cmd;
0272     wpg_data = swab32(data);
0273     wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET;
0274     writel(wpg_data, wpg_addr);
0275 
0276     //--------------------------------------------------------------------
0277     // WRITE - step 3 : issue start operation,I2C master control bit 30:ON
0278     //                 2020 : [20] OR operation at [20] offset 0x20
0279     data = WPG_I2CMCNTL_STARTOP_MASK;
0280     wpg_data = swab32(data);
0281     wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR;
0282     writel(wpg_data, wpg_addr);
0283 
0284     //--------------------------------------------------------------------
0285     // WRITE - step 4 : wait until start operation bit clears
0286     i = CMD_COMPLETE_TOUT_SEC;
0287     while (i) {
0288         msleep(10);
0289         wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET;
0290         wpg_data = readl(wpg_addr);
0291         data = swab32(wpg_data);
0292         if (!(data & WPG_I2CMCNTL_STARTOP_MASK))
0293             break;
0294         i--;
0295     }
0296     if (i == 0) {
0297         debug("%s - Exit Error:WPG timeout\n", __func__);
0298         rc = HPC_ERROR;
0299     }
0300 
0301     //--------------------------------------------------------------------
0302     // WRITE - step 5 : read I2C status register
0303     i = CMD_COMPLETE_TOUT_SEC;
0304     while (i) {
0305         msleep(10);
0306         wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET;
0307         wpg_data = readl(wpg_addr);
0308         data = swab32(wpg_data);
0309         if (HPC_I2CSTATUS_CHECK(data))
0310             break;
0311         i--;
0312     }
0313     if (i == 0) {
0314         debug("ctrl_read - Error : I2C timeout\n");
0315         rc = HPC_ERROR;
0316     }
0317 
0318     debug_polling("%s Exit rc[%x]\n", __func__, rc);
0319     return (rc);
0320 }
0321 
0322 //------------------------------------------------------------
0323 //  Read from ISA type HPC
0324 //------------------------------------------------------------
0325 static u8 isa_ctrl_read(struct controller *ctlr_ptr, u8 offset)
0326 {
0327     u16 start_address;
0328     u8 data;
0329 
0330     start_address = ctlr_ptr->u.isa_ctlr.io_start;
0331     data = inb(start_address + offset);
0332     return data;
0333 }
0334 
0335 //--------------------------------------------------------------
0336 // Write to ISA type HPC
0337 //--------------------------------------------------------------
0338 static void isa_ctrl_write(struct controller *ctlr_ptr, u8 offset, u8 data)
0339 {
0340     u16 start_address;
0341     u16 port_address;
0342 
0343     start_address = ctlr_ptr->u.isa_ctlr.io_start;
0344     port_address = start_address + (u16) offset;
0345     outb(data, port_address);
0346 }
0347 
0348 static u8 pci_ctrl_read(struct controller *ctrl, u8 offset)
0349 {
0350     u8 data = 0x00;
0351     debug("inside pci_ctrl_read\n");
0352     if (ctrl->ctrl_dev)
0353         pci_read_config_byte(ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data);
0354     return data;
0355 }
0356 
0357 static u8 pci_ctrl_write(struct controller *ctrl, u8 offset, u8 data)
0358 {
0359     u8 rc = -ENODEV;
0360     debug("inside pci_ctrl_write\n");
0361     if (ctrl->ctrl_dev) {
0362         pci_write_config_byte(ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data);
0363         rc = 0;
0364     }
0365     return rc;
0366 }
0367 
0368 static u8 ctrl_read(struct controller *ctlr, void __iomem *base, u8 offset)
0369 {
0370     u8 rc;
0371     switch (ctlr->ctlr_type) {
0372     case 0:
0373         rc = isa_ctrl_read(ctlr, offset);
0374         break;
0375     case 1:
0376         rc = pci_ctrl_read(ctlr, offset);
0377         break;
0378     case 2:
0379     case 4:
0380         rc = i2c_ctrl_read(ctlr, base, offset);
0381         break;
0382     default:
0383         return -ENODEV;
0384     }
0385     return rc;
0386 }
0387 
0388 static u8 ctrl_write(struct controller *ctlr, void __iomem *base, u8 offset, u8 data)
0389 {
0390     u8 rc = 0;
0391     switch (ctlr->ctlr_type) {
0392     case 0:
0393         isa_ctrl_write(ctlr, offset, data);
0394         break;
0395     case 1:
0396         rc = pci_ctrl_write(ctlr, offset, data);
0397         break;
0398     case 2:
0399     case 4:
0400         rc = i2c_ctrl_write(ctlr, base, offset, data);
0401         break;
0402     default:
0403         return -ENODEV;
0404     }
0405     return rc;
0406 }
0407 /*----------------------------------------------------------------------
0408 * Name:    hpc_writecmdtoindex()
0409 *
0410 * Action:  convert a write command to proper index within a controller
0411 *
0412 * Return   index, HPC_ERROR
0413 *---------------------------------------------------------------------*/
0414 static u8 hpc_writecmdtoindex(u8 cmd, u8 index)
0415 {
0416     u8 rc;
0417 
0418     switch (cmd) {
0419     case HPC_CTLR_ENABLEIRQ:    // 0x00.N.15
0420     case HPC_CTLR_CLEARIRQ: // 0x06.N.15
0421     case HPC_CTLR_RESET:    // 0x07.N.15
0422     case HPC_CTLR_IRQSTEER: // 0x08.N.15
0423     case HPC_CTLR_DISABLEIRQ:   // 0x01.N.15
0424     case HPC_ALLSLOT_ON:    // 0x11.N.15
0425     case HPC_ALLSLOT_OFF:   // 0x12.N.15
0426         rc = 0x0F;
0427         break;
0428 
0429     case HPC_SLOT_OFF:  // 0x02.Y.0-14
0430     case HPC_SLOT_ON:   // 0x03.Y.0-14
0431     case HPC_SLOT_ATTNOFF:  // 0x04.N.0-14
0432     case HPC_SLOT_ATTNON:   // 0x05.N.0-14
0433     case HPC_SLOT_BLINKLED: // 0x13.N.0-14
0434         rc = index;
0435         break;
0436 
0437     case HPC_BUS_33CONVMODE:
0438     case HPC_BUS_66CONVMODE:
0439     case HPC_BUS_66PCIXMODE:
0440     case HPC_BUS_100PCIXMODE:
0441     case HPC_BUS_133PCIXMODE:
0442         rc = index + WPG_1ST_BUS_INDEX - 1;
0443         break;
0444 
0445     default:
0446         err("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd);
0447         rc = HPC_ERROR;
0448     }
0449 
0450     return rc;
0451 }
0452 
0453 /*----------------------------------------------------------------------
0454 * Name:    hpc_readcmdtoindex()
0455 *
0456 * Action:  convert a read command to proper index within a controller
0457 *
0458 * Return   index, HPC_ERROR
0459 *---------------------------------------------------------------------*/
0460 static u8 hpc_readcmdtoindex(u8 cmd, u8 index)
0461 {
0462     u8 rc;
0463 
0464     switch (cmd) {
0465     case READ_CTLRSTATUS:
0466         rc = 0x0F;
0467         break;
0468     case READ_SLOTSTATUS:
0469     case READ_ALLSTAT:
0470         rc = index;
0471         break;
0472     case READ_EXTSLOTSTATUS:
0473         rc = index + WPG_1ST_EXTSLOT_INDEX;
0474         break;
0475     case READ_BUSSTATUS:
0476         rc = index + WPG_1ST_BUS_INDEX - 1;
0477         break;
0478     case READ_SLOTLATCHLOWREG:
0479         rc = 0x28;
0480         break;
0481     case READ_REVLEVEL:
0482         rc = 0x25;
0483         break;
0484     case READ_HPCOPTIONS:
0485         rc = 0x27;
0486         break;
0487     default:
0488         rc = HPC_ERROR;
0489     }
0490     return rc;
0491 }
0492 
0493 /*----------------------------------------------------------------------
0494 * Name:    HPCreadslot()
0495 *
0496 * Action:  issue a READ command to HPC
0497 *
0498 * Input:   pslot   - cannot be NULL for READ_ALLSTAT
0499 *          pstatus - can be NULL for READ_ALLSTAT
0500 *
0501 * Return   0 or error codes
0502 *---------------------------------------------------------------------*/
0503 int ibmphp_hpc_readslot(struct slot *pslot, u8 cmd, u8 *pstatus)
0504 {
0505     void __iomem *wpg_bbar = NULL;
0506     struct controller *ctlr_ptr;
0507     u8 index, status;
0508     int rc = 0;
0509     int busindex;
0510 
0511     debug_polling("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus);
0512 
0513     if ((pslot == NULL)
0514         || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) {
0515         rc = -EINVAL;
0516         err("%s - Error invalid pointer, rc[%d]\n", __func__, rc);
0517         return rc;
0518     }
0519 
0520     if (cmd == READ_BUSSTATUS) {
0521         busindex = ibmphp_get_bus_index(pslot->bus);
0522         if (busindex < 0) {
0523             rc = -EINVAL;
0524             err("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
0525             return rc;
0526         } else
0527             index = (u8) busindex;
0528     } else
0529         index = pslot->ctlr_index;
0530 
0531     index = hpc_readcmdtoindex(cmd, index);
0532 
0533     if (index == HPC_ERROR) {
0534         rc = -EINVAL;
0535         err("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc);
0536         return rc;
0537     }
0538 
0539     ctlr_ptr = pslot->ctrl;
0540 
0541     get_hpc_access();
0542 
0543     //--------------------------------------------------------------------
0544     // map physical address to logical address
0545     //--------------------------------------------------------------------
0546     if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
0547         wpg_bbar = ioremap(ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
0548 
0549     //--------------------------------------------------------------------
0550     // check controller status before reading
0551     //--------------------------------------------------------------------
0552     rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
0553     if (!rc) {
0554         switch (cmd) {
0555         case READ_ALLSTAT:
0556             // update the slot structure
0557             pslot->ctrl->status = status;
0558             pslot->status = ctrl_read(ctlr_ptr, wpg_bbar, index);
0559             rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
0560                                &status);
0561             if (!rc)
0562                 pslot->ext_status = ctrl_read(ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX);
0563 
0564             break;
0565 
0566         case READ_SLOTSTATUS:
0567             // DO NOT update the slot structure
0568             *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
0569             break;
0570 
0571         case READ_EXTSLOTSTATUS:
0572             // DO NOT update the slot structure
0573             *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
0574             break;
0575 
0576         case READ_CTLRSTATUS:
0577             // DO NOT update the slot structure
0578             *pstatus = status;
0579             break;
0580 
0581         case READ_BUSSTATUS:
0582             pslot->busstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
0583             break;
0584         case READ_REVLEVEL:
0585             *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
0586             break;
0587         case READ_HPCOPTIONS:
0588             *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
0589             break;
0590         case READ_SLOTLATCHLOWREG:
0591             // DO NOT update the slot structure
0592             *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index);
0593             break;
0594 
0595             // Not used
0596         case READ_ALLSLOT:
0597             list_for_each_entry(pslot, &ibmphp_slot_head,
0598                         ibm_slot_list) {
0599                 index = pslot->ctlr_index;
0600                 rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr,
0601                                 wpg_bbar, &status);
0602                 if (!rc) {
0603                     pslot->status = ctrl_read(ctlr_ptr, wpg_bbar, index);
0604                     rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT,
0605                                     ctlr_ptr, wpg_bbar, &status);
0606                     if (!rc)
0607                         pslot->ext_status =
0608                             ctrl_read(ctlr_ptr, wpg_bbar,
0609                                 index + WPG_1ST_EXTSLOT_INDEX);
0610                 } else {
0611                     err("%s - Error ctrl_read failed\n", __func__);
0612                     rc = -EINVAL;
0613                     break;
0614                 }
0615             }
0616             break;
0617         default:
0618             rc = -EINVAL;
0619             break;
0620         }
0621     }
0622     //--------------------------------------------------------------------
0623     // cleanup
0624     //--------------------------------------------------------------------
0625 
0626     // remove physical to logical address mapping
0627     if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
0628         iounmap(wpg_bbar);
0629 
0630     free_hpc_access();
0631 
0632     debug_polling("%s - Exit rc[%d]\n", __func__, rc);
0633     return rc;
0634 }
0635 
0636 /*----------------------------------------------------------------------
0637 * Name:    ibmphp_hpc_writeslot()
0638 *
0639 * Action: issue a WRITE command to HPC
0640 *---------------------------------------------------------------------*/
0641 int ibmphp_hpc_writeslot(struct slot *pslot, u8 cmd)
0642 {
0643     void __iomem *wpg_bbar = NULL;
0644     struct controller *ctlr_ptr;
0645     u8 index, status;
0646     int busindex;
0647     u8 done;
0648     int rc = 0;
0649     int timeout;
0650 
0651     debug_polling("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd);
0652     if (pslot == NULL) {
0653         rc = -EINVAL;
0654         err("%s - Error Exit rc[%d]\n", __func__, rc);
0655         return rc;
0656     }
0657 
0658     if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) ||
0659         (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) ||
0660         (cmd == HPC_BUS_133PCIXMODE)) {
0661         busindex = ibmphp_get_bus_index(pslot->bus);
0662         if (busindex < 0) {
0663             rc = -EINVAL;
0664             err("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc);
0665             return rc;
0666         } else
0667             index = (u8) busindex;
0668     } else
0669         index = pslot->ctlr_index;
0670 
0671     index = hpc_writecmdtoindex(cmd, index);
0672 
0673     if (index == HPC_ERROR) {
0674         rc = -EINVAL;
0675         err("%s - Error Exit rc[%d]\n", __func__, rc);
0676         return rc;
0677     }
0678 
0679     ctlr_ptr = pslot->ctrl;
0680 
0681     get_hpc_access();
0682 
0683     //--------------------------------------------------------------------
0684     // map physical address to logical address
0685     //--------------------------------------------------------------------
0686     if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) {
0687         wpg_bbar = ioremap(ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE);
0688 
0689         debug("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__,
0690         ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar,
0691         ctlr_ptr->u.wpeg_ctlr.i2c_addr);
0692     }
0693     //--------------------------------------------------------------------
0694     // check controller status before writing
0695     //--------------------------------------------------------------------
0696     rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status);
0697     if (!rc) {
0698 
0699         ctrl_write(ctlr_ptr, wpg_bbar, index, cmd);
0700 
0701         //--------------------------------------------------------------------
0702         // check controller is still not working on the command
0703         //--------------------------------------------------------------------
0704         timeout = CMD_COMPLETE_TOUT_SEC;
0705         done = 0;
0706         while (!done) {
0707             rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar,
0708                             &status);
0709             if (!rc) {
0710                 if (NEEDTOCHECK_CMDSTATUS(cmd)) {
0711                     if (CTLR_FINISHED(status) == HPC_CTLR_FINISHED_YES)
0712                         done = 1;
0713                 } else
0714                     done = 1;
0715             }
0716             if (!done) {
0717                 msleep(1000);
0718                 if (timeout < 1) {
0719                     done = 1;
0720                     err("%s - Error command complete timeout\n", __func__);
0721                     rc = -EFAULT;
0722                 } else
0723                     timeout--;
0724             }
0725         }
0726         ctlr_ptr->status = status;
0727     }
0728     // cleanup
0729 
0730     // remove physical to logical address mapping
0731     if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4))
0732         iounmap(wpg_bbar);
0733     free_hpc_access();
0734 
0735     debug_polling("%s - Exit rc[%d]\n", __func__, rc);
0736     return rc;
0737 }
0738 
0739 /*----------------------------------------------------------------------
0740 * Name:    get_hpc_access()
0741 *
0742 * Action: make sure only one process can access HPC at one time
0743 *---------------------------------------------------------------------*/
0744 static void get_hpc_access(void)
0745 {
0746     mutex_lock(&sem_hpcaccess);
0747 }
0748 
0749 /*----------------------------------------------------------------------
0750 * Name:    free_hpc_access()
0751 *---------------------------------------------------------------------*/
0752 void free_hpc_access(void)
0753 {
0754     mutex_unlock(&sem_hpcaccess);
0755 }
0756 
0757 /*----------------------------------------------------------------------
0758 * Name:    ibmphp_lock_operations()
0759 *
0760 * Action: make sure only one process can change the data structure
0761 *---------------------------------------------------------------------*/
0762 void ibmphp_lock_operations(void)
0763 {
0764     mutex_lock(&operations_mutex);
0765     to_debug = 1;
0766 }
0767 
0768 /*----------------------------------------------------------------------
0769 * Name:    ibmphp_unlock_operations()
0770 *---------------------------------------------------------------------*/
0771 void ibmphp_unlock_operations(void)
0772 {
0773     debug("%s - Entry\n", __func__);
0774     mutex_unlock(&operations_mutex);
0775     to_debug = 0;
0776     debug("%s - Exit\n", __func__);
0777 }
0778 
0779 /*----------------------------------------------------------------------
0780 * Name:    poll_hpc()
0781 *---------------------------------------------------------------------*/
0782 #define POLL_LATCH_REGISTER 0
0783 #define POLL_SLOTS      1
0784 #define POLL_SLEEP      2
0785 static int poll_hpc(void *data)
0786 {
0787     struct slot myslot;
0788     struct slot *pslot = NULL;
0789     int rc;
0790     int poll_state = POLL_LATCH_REGISTER;
0791     u8 oldlatchlow = 0x00;
0792     u8 curlatchlow = 0x00;
0793     int poll_count = 0;
0794     u8 ctrl_count = 0x00;
0795 
0796     debug("%s - Entry\n", __func__);
0797 
0798     while (!kthread_should_stop()) {
0799         /* try to get the lock to do some kind of hardware access */
0800         mutex_lock(&operations_mutex);
0801 
0802         switch (poll_state) {
0803         case POLL_LATCH_REGISTER:
0804             oldlatchlow = curlatchlow;
0805             ctrl_count = 0x00;
0806             list_for_each_entry(pslot, &ibmphp_slot_head,
0807                         ibm_slot_list) {
0808                 if (ctrl_count >= ibmphp_get_total_controllers())
0809                     break;
0810                 if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
0811                     ctrl_count++;
0812                     if (READ_SLOT_LATCH(pslot->ctrl)) {
0813                         rc = ibmphp_hpc_readslot(pslot,
0814                                       READ_SLOTLATCHLOWREG,
0815                                       &curlatchlow);
0816                         if (oldlatchlow != curlatchlow)
0817                             process_changeinlatch(oldlatchlow,
0818                                            curlatchlow,
0819                                            pslot->ctrl);
0820                     }
0821                 }
0822             }
0823             ++poll_count;
0824             poll_state = POLL_SLEEP;
0825             break;
0826         case POLL_SLOTS:
0827             list_for_each_entry(pslot, &ibmphp_slot_head,
0828                         ibm_slot_list) {
0829                 // make a copy of the old status
0830                 memcpy((void *) &myslot, (void *) pslot,
0831                     sizeof(struct slot));
0832                 rc = ibmphp_hpc_readslot(pslot, READ_ALLSTAT, NULL);
0833                 if ((myslot.status != pslot->status)
0834                     || (myslot.ext_status != pslot->ext_status))
0835                     process_changeinstatus(pslot, &myslot);
0836             }
0837             ctrl_count = 0x00;
0838             list_for_each_entry(pslot, &ibmphp_slot_head,
0839                         ibm_slot_list) {
0840                 if (ctrl_count >= ibmphp_get_total_controllers())
0841                     break;
0842                 if (pslot->ctrl->ctlr_relative_id == ctrl_count) {
0843                     ctrl_count++;
0844                     if (READ_SLOT_LATCH(pslot->ctrl))
0845                         rc = ibmphp_hpc_readslot(pslot,
0846                                       READ_SLOTLATCHLOWREG,
0847                                       &curlatchlow);
0848                 }
0849             }
0850             ++poll_count;
0851             poll_state = POLL_SLEEP;
0852             break;
0853         case POLL_SLEEP:
0854             /* don't sleep with a lock on the hardware */
0855             mutex_unlock(&operations_mutex);
0856             msleep(POLL_INTERVAL_SEC * 1000);
0857 
0858             if (kthread_should_stop())
0859                 goto out_sleep;
0860 
0861             mutex_lock(&operations_mutex);
0862 
0863             if (poll_count >= POLL_LATCH_CNT) {
0864                 poll_count = 0;
0865                 poll_state = POLL_SLOTS;
0866             } else
0867                 poll_state = POLL_LATCH_REGISTER;
0868             break;
0869         }
0870         /* give up the hardware semaphore */
0871         mutex_unlock(&operations_mutex);
0872         /* sleep for a short time just for good measure */
0873 out_sleep:
0874         msleep(100);
0875     }
0876     complete(&exit_complete);
0877     debug("%s - Exit\n", __func__);
0878     return 0;
0879 }
0880 
0881 
0882 /*----------------------------------------------------------------------
0883 * Name:    process_changeinstatus
0884 *
0885 * Action:  compare old and new slot status, process the change in status
0886 *
0887 * Input:   pointer to slot struct, old slot struct
0888 *
0889 * Return   0 or error codes
0890 * Value:
0891 *
0892 * Side
0893 * Effects: None.
0894 *
0895 * Notes:
0896 *---------------------------------------------------------------------*/
0897 static int process_changeinstatus(struct slot *pslot, struct slot *poldslot)
0898 {
0899     u8 status;
0900     int rc = 0;
0901     u8 disable = 0;
0902     u8 update = 0;
0903 
0904     debug("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot);
0905 
0906     // bit 0 - HPC_SLOT_POWER
0907     if ((pslot->status & 0x01) != (poldslot->status & 0x01))
0908         update = 1;
0909 
0910     // bit 1 - HPC_SLOT_CONNECT
0911     // ignore
0912 
0913     // bit 2 - HPC_SLOT_ATTN
0914     if ((pslot->status & 0x04) != (poldslot->status & 0x04))
0915         update = 1;
0916 
0917     // bit 3 - HPC_SLOT_PRSNT2
0918     // bit 4 - HPC_SLOT_PRSNT1
0919     if (((pslot->status & 0x08) != (poldslot->status & 0x08))
0920         || ((pslot->status & 0x10) != (poldslot->status & 0x10)))
0921         update = 1;
0922 
0923     // bit 5 - HPC_SLOT_PWRGD
0924     if ((pslot->status & 0x20) != (poldslot->status & 0x20))
0925         // OFF -> ON: ignore, ON -> OFF: disable slot
0926         if ((poldslot->status & 0x20) && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT(poldslot->status)))
0927             disable = 1;
0928 
0929     // bit 6 - HPC_SLOT_BUS_SPEED
0930     // ignore
0931 
0932     // bit 7 - HPC_SLOT_LATCH
0933     if ((pslot->status & 0x80) != (poldslot->status & 0x80)) {
0934         update = 1;
0935         // OPEN -> CLOSE
0936         if (pslot->status & 0x80) {
0937             if (SLOT_PWRGD(pslot->status)) {
0938                 // power goes on and off after closing latch
0939                 // check again to make sure power is still ON
0940                 msleep(1000);
0941                 rc = ibmphp_hpc_readslot(pslot, READ_SLOTSTATUS, &status);
0942                 if (SLOT_PWRGD(status))
0943                     update = 1;
0944                 else    // overwrite power in pslot to OFF
0945                     pslot->status &= ~HPC_SLOT_POWER;
0946             }
0947         }
0948         // CLOSE -> OPEN
0949         else if ((SLOT_PWRGD(poldslot->status) == HPC_SLOT_PWRGD_GOOD)
0950             && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT(poldslot->status))) {
0951             disable = 1;
0952         }
0953         // else - ignore
0954     }
0955     // bit 4 - HPC_SLOT_BLINK_ATTN
0956     if ((pslot->ext_status & 0x08) != (poldslot->ext_status & 0x08))
0957         update = 1;
0958 
0959     if (disable) {
0960         debug("process_changeinstatus - disable slot\n");
0961         pslot->flag = 0;
0962         rc = ibmphp_do_disable_slot(pslot);
0963     }
0964 
0965     if (update || disable)
0966         ibmphp_update_slot_info(pslot);
0967 
0968     debug("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update);
0969 
0970     return rc;
0971 }
0972 
0973 /*----------------------------------------------------------------------
0974 * Name:    process_changeinlatch
0975 *
0976 * Action:  compare old and new latch reg status, process the change
0977 *
0978 * Input:   old and current latch register status
0979 *
0980 * Return   0 or error codes
0981 * Value:
0982 *---------------------------------------------------------------------*/
0983 static int process_changeinlatch(u8 old, u8 new, struct controller *ctrl)
0984 {
0985     struct slot myslot, *pslot;
0986     u8 i;
0987     u8 mask;
0988     int rc = 0;
0989 
0990     debug("%s - Entry old[%x], new[%x]\n", __func__, old, new);
0991     // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots
0992 
0993     for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) {
0994         mask = 0x01 << i;
0995         if ((mask & old) != (mask & new)) {
0996             pslot = ibmphp_get_slot_from_physical_num(i);
0997             if (pslot) {
0998                 memcpy((void *) &myslot, (void *) pslot, sizeof(struct slot));
0999                 rc = ibmphp_hpc_readslot(pslot, READ_ALLSTAT, NULL);
1000                 debug("%s - call process_changeinstatus for slot[%d]\n", __func__, i);
1001                 process_changeinstatus(pslot, &myslot);
1002             } else {
1003                 rc = -EINVAL;
1004                 err("%s - Error bad pointer for slot[%d]\n", __func__, i);
1005             }
1006         }
1007     }
1008     debug("%s - Exit rc[%d]\n", __func__, rc);
1009     return rc;
1010 }
1011 
1012 /*----------------------------------------------------------------------
1013 * Name:    ibmphp_hpc_start_poll_thread
1014 *
1015 * Action:  start polling thread
1016 *---------------------------------------------------------------------*/
1017 int __init ibmphp_hpc_start_poll_thread(void)
1018 {
1019     debug("%s - Entry\n", __func__);
1020 
1021     ibmphp_poll_thread = kthread_run(poll_hpc, NULL, "hpc_poll");
1022     if (IS_ERR(ibmphp_poll_thread)) {
1023         err("%s - Error, thread not started\n", __func__);
1024         return PTR_ERR(ibmphp_poll_thread);
1025     }
1026     return 0;
1027 }
1028 
1029 /*----------------------------------------------------------------------
1030 * Name:    ibmphp_hpc_stop_poll_thread
1031 *
1032 * Action:  stop polling thread and cleanup
1033 *---------------------------------------------------------------------*/
1034 void __exit ibmphp_hpc_stop_poll_thread(void)
1035 {
1036     debug("%s - Entry\n", __func__);
1037 
1038     kthread_stop(ibmphp_poll_thread);
1039     debug("before locking operations\n");
1040     ibmphp_lock_operations();
1041     debug("after locking operations\n");
1042 
1043     // wait for poll thread to exit
1044     debug("before exit_complete down\n");
1045     wait_for_completion(&exit_complete);
1046     debug("after exit_completion down\n");
1047 
1048     // cleanup
1049     debug("before free_hpc_access\n");
1050     free_hpc_access();
1051     debug("after free_hpc_access\n");
1052     ibmphp_unlock_operations();
1053     debug("after unlock operations\n");
1054 
1055     debug("%s - Exit\n", __func__);
1056 }
1057 
1058 /*----------------------------------------------------------------------
1059 * Name:    hpc_wait_ctlr_notworking
1060 *
1061 * Action:  wait until the controller is in a not working state
1062 *
1063 * Return   0, HPC_ERROR
1064 * Value:
1065 *---------------------------------------------------------------------*/
1066 static int hpc_wait_ctlr_notworking(int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar,
1067                     u8 *pstatus)
1068 {
1069     int rc = 0;
1070     u8 done = 0;
1071 
1072     debug_polling("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout);
1073 
1074     while (!done) {
1075         *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX);
1076         if (*pstatus == HPC_ERROR) {
1077             rc = HPC_ERROR;
1078             done = 1;
1079         }
1080         if (CTLR_WORKING(*pstatus) == HPC_CTLR_WORKING_NO)
1081             done = 1;
1082         if (!done) {
1083             msleep(1000);
1084             if (timeout < 1) {
1085                 done = 1;
1086                 err("HPCreadslot - Error ctlr timeout\n");
1087                 rc = HPC_ERROR;
1088             } else
1089                 timeout--;
1090         }
1091     }
1092     debug_polling("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus);
1093     return rc;
1094 }
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