pci/hotplug/ibmphp.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 #ifndef __IBMPHP_H
0003 #define __IBMPHP_H
0004
0005 /*
0006  * IBM Hot Plug Controller Driver
0007  *
0008  * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation
0009  *
0010  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
0011  * Copyright (C) 2001-2003 IBM Corp.
0012  *
0013  * All rights reserved.
0014  *
0015  * Send feedback to <gregkh@us.ibm.com>
0016  *
0017  */
0018
0019 #include <linux/pci_hotplug.h>
0020
0021 extern int ibmphp_debug;
0022
0023 #if !defined(MODULE)
0024     #define MY_NAME "ibmphpd"
0025 #else
0026     #define MY_NAME THIS_MODULE->name
0027 #endif
0028 #define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
0029 #define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
0030 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
0031 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
0032 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
0033
0034
0035 /* EBDA stuff */
0036
0037 /***********************************************************
0038 * SLOT CAPABILITY                                          *
0039 ***********************************************************/
0040
0041 #define EBDA_SLOT_133_MAX       0x20
0042 #define EBDA_SLOT_100_MAX       0x10
0043 #define EBDA_SLOT_66_MAX        0x02
0044 #define EBDA_SLOT_PCIX_CAP      0x08
0045
0046
0047 /************************************************************
0048 *  RESOURCE TYPE                                             *
0049 ************************************************************/
0050
0051 #define EBDA_RSRC_TYPE_MASK     0x03
0052 #define EBDA_IO_RSRC_TYPE       0x00
0053 #define EBDA_MEM_RSRC_TYPE      0x01
0054 #define EBDA_PFM_RSRC_TYPE      0x03
0055 #define EBDA_RES_RSRC_TYPE      0x02
0056
0057
0058 /*************************************************************
0059 *  IO RESTRICTION TYPE                                       *
0060 *************************************************************/
0061
0062 #define EBDA_IO_RESTRI_MASK     0x0c
0063 #define EBDA_NO_RESTRI          0x00
0064 #define EBDA_AVO_VGA_ADDR       0x04
0065 #define EBDA_AVO_VGA_ADDR_AND_ALIA  0x08
0066 #define EBDA_AVO_ISA_ADDR       0x0c
0067
0068
0069 /**************************************************************
0070 *  DEVICE TYPE DEF                                            *
0071 **************************************************************/
0072
0073 #define EBDA_DEV_TYPE_MASK      0x10
0074 #define EBDA_PCI_DEV            0x10
0075 #define EBDA_NON_PCI_DEV        0x00
0076
0077
0078 /***************************************************************
0079 *  PRIMARY DEF DEFINITION                                      *
0080 ***************************************************************/
0081
0082 #define EBDA_PRI_DEF_MASK       0x20
0083 #define EBDA_PRI_PCI_BUS_INFO       0x20
0084 #define EBDA_NORM_DEV_RSRC_INFO     0x00
0085
0086
0087 //--------------------------------------------------------------
0088 // RIO TABLE DATA STRUCTURE
0089 //--------------------------------------------------------------
0090
0091 struct rio_table_hdr {
0092     u8 ver_num;
0093     u8 scal_count;
0094     u8 riodev_count;
0095     u16 offset;
0096 };
0097
0098 //-------------------------------------------------------------
0099 // SCALABILITY DETAIL
0100 //-------------------------------------------------------------
0101
0102 struct scal_detail {
0103     u8 node_id;
0104     u32 cbar;
0105     u8 port0_node_connect;
0106     u8 port0_port_connect;
0107     u8 port1_node_connect;
0108     u8 port1_port_connect;
0109     u8 port2_node_connect;
0110     u8 port2_port_connect;
0111     u8 chassis_num;
0112 //  struct list_head scal_detail_list;
0113 };
0114
0115 //--------------------------------------------------------------
0116 // RIO DETAIL
0117 //--------------------------------------------------------------
0118
0119 struct rio_detail {
0120     u8 rio_node_id;
0121     u32 bbar;
0122     u8 rio_type;
0123     u8 owner_id;
0124     u8 port0_node_connect;
0125     u8 port0_port_connect;
0126     u8 port1_node_connect;
0127     u8 port1_port_connect;
0128     u8 first_slot_num;
0129     u8 status;
0130     u8 wpindex;
0131     u8 chassis_num;
0132     struct list_head rio_detail_list;
0133 };
0134
0135 struct opt_rio {
0136     u8 rio_type;
0137     u8 chassis_num;
0138     u8 first_slot_num;
0139     u8 middle_num;
0140     struct list_head opt_rio_list;
0141 };
0142
0143 struct opt_rio_lo {
0144     u8 rio_type;
0145     u8 chassis_num;
0146     u8 first_slot_num;
0147     u8 middle_num;
0148     u8 pack_count;
0149     struct list_head opt_rio_lo_list;
0150 };
0151
0152 /****************************************************************
0153 *  HPC DESCRIPTOR NODE                                          *
0154 ****************************************************************/
0155
0156 struct ebda_hpc_list {
0157     u8 format;
0158     u16 num_ctlrs;
0159     short phys_addr;
0160 //      struct list_head ebda_hpc_list;
0161 };
0162 /*****************************************************************
0163 *   IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS           *
0164 *   STRUCTURE                                                    *
0165 *****************************************************************/
0166
0167 struct ebda_hpc_slot {
0168     u8 slot_num;
0169     u32 slot_bus_num;
0170     u8 ctl_index;
0171     u8 slot_cap;
0172 };
0173
0174 struct ebda_hpc_bus {
0175     u32 bus_num;
0176     u8 slots_at_33_conv;
0177     u8 slots_at_66_conv;
0178     u8 slots_at_66_pcix;
0179     u8 slots_at_100_pcix;
0180     u8 slots_at_133_pcix;
0181 };
0182
0183
0184 /********************************************************************
0185 *   THREE TYPE OF HOT PLUG CONTROLLER                                *
0186 ********************************************************************/
0187
0188 struct isa_ctlr_access {
0189     u16 io_start;
0190     u16 io_end;
0191 };
0192
0193 struct pci_ctlr_access {
0194     u8 bus;
0195     u8 dev_fun;
0196 };
0197
0198 struct wpeg_i2c_ctlr_access {
0199     ulong wpegbbar;
0200     u8 i2c_addr;
0201 };
0202
0203 #define HPC_DEVICE_ID       0x0246
0204 #define HPC_SUBSYSTEM_ID    0x0247
0205 #define HPC_PCI_OFFSET      0x40
0206 /*************************************************************************
0207 *   RSTC DESCRIPTOR NODE                                                 *
0208 *************************************************************************/
0209
0210 struct ebda_rsrc_list {
0211     u8 format;
0212     u16 num_entries;
0213     u16 phys_addr;
0214     struct ebda_rsrc_list *next;
0215 };
0216
0217
0218 /***************************************************************************
0219 *   PCI RSRC NODE                                                          *
0220 ***************************************************************************/
0221
0222 struct ebda_pci_rsrc {
0223     u8 rsrc_type;
0224     u8 bus_num;
0225     u8 dev_fun;
0226     u32 start_addr;
0227     u32 end_addr;
0228     u8 marked;  /* for NVRAM */
0229     struct list_head ebda_pci_rsrc_list;
0230 };
0231
0232
0233 /***********************************************************
0234 * BUS_INFO DATE STRUCTURE                                  *
0235 ***********************************************************/
0236
0237 struct bus_info {
0238     u8 slot_min;
0239     u8 slot_max;
0240     u8 slot_count;
0241     u8 busno;
0242     u8 controller_id;
0243     u8 current_speed;
0244     u8 current_bus_mode;
0245     u8 index;
0246     u8 slots_at_33_conv;
0247     u8 slots_at_66_conv;
0248     u8 slots_at_66_pcix;
0249     u8 slots_at_100_pcix;
0250     u8 slots_at_133_pcix;
0251     struct list_head bus_info_list;
0252 };
0253
0254
0255 /***********************************************************
0256 * GLOBAL VARIABLES                                         *
0257 ***********************************************************/
0258 extern struct list_head ibmphp_ebda_pci_rsrc_head;
0259 extern struct list_head ibmphp_slot_head;
0260 /***********************************************************
0261 * FUNCTION PROTOTYPES                                      *
0262 ***********************************************************/
0263
0264 void ibmphp_free_ebda_hpc_queue(void);
0265 int ibmphp_access_ebda(void);
0266 struct slot *ibmphp_get_slot_from_physical_num(u8);
0267 int ibmphp_get_total_hp_slots(void);
0268 void ibmphp_free_ibm_slot(struct slot *);
0269 void ibmphp_free_bus_info_queue(void);
0270 void ibmphp_free_ebda_pci_rsrc_queue(void);
0271 struct bus_info *ibmphp_find_same_bus_num(u32);
0272 int ibmphp_get_bus_index(u8);
0273 u16 ibmphp_get_total_controllers(void);
0274 int ibmphp_register_pci(void);
0275
0276 /* passed parameters */
0277 #define MEM     0
0278 #define IO      1
0279 #define PFMEM       2
0280
0281 /* bit masks */
0282 #define RESTYPE     0x03
0283 #define IOMASK      0x00    /* will need to take its complement */
0284 #define MMASK       0x01
0285 #define PFMASK      0x03
0286 #define PCIDEVMASK  0x10    /* we should always have PCI devices */
0287 #define PRIMARYBUSMASK  0x20
0288
0289 /* pci specific defines */
0290 #define PCI_VENDOR_ID_NOTVALID      0xFFFF
0291 #define PCI_HEADER_TYPE_MULTIDEVICE 0x80
0292 #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81
0293
0294 #define LATENCY     0x64
0295 #define CACHE       64
0296 #define DEVICEENABLE    0x015F      /* CPQ has 0x0157 */
0297
0298 #define IOBRIDGE    0x1000      /* 4k */
0299 #define MEMBRIDGE   0x100000    /* 1M */
0300
0301 /* irqs */
0302 #define SCSI_IRQ    0x09
0303 #define LAN_IRQ     0x0A
0304 #define OTHER_IRQ   0x0B
0305
0306 /* Data Structures */
0307
0308 /* type is of the form x x xx xx
0309  *                     | |  |  |_ 00 - I/O, 01 - Memory, 11 - PFMemory
0310  *                     | |  - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid
0311  *                     | |    VGA and their aliases, 11 - Avoid ISA
0312  *                     | - 1 - PCI device, 0 - non pci device
0313  *                     - 1 - Primary PCI Bus Information (0 if Normal device)
0314  * the IO restrictions [2:3] are only for primary buses
0315  */
0316
0317
0318 /* we need this struct because there could be several resource blocks
0319  * allocated per primary bus in the EBDA
0320  */
0321 struct range_node {
0322     int rangeno;
0323     u32 start;
0324     u32 end;
0325     struct range_node *next;
0326 };
0327
0328 struct bus_node {
0329     u8 busno;
0330     int noIORanges;
0331     struct range_node *rangeIO;
0332     int noMemRanges;
0333     struct range_node *rangeMem;
0334     int noPFMemRanges;
0335     struct range_node *rangePFMem;
0336     int needIOUpdate;
0337     int needMemUpdate;
0338     int needPFMemUpdate;
0339     struct resource_node *firstIO;  /* first IO resource on the Bus */
0340     struct resource_node *firstMem; /* first memory resource on the Bus */
0341     struct resource_node *firstPFMem;   /* first prefetchable memory resource on the Bus */
0342     struct resource_node *firstPFMemFromMem;    /* when run out of pfmem available, taking from Mem */
0343     struct list_head bus_list;
0344 };
0345
0346 struct resource_node {
0347     int rangeno;
0348     u8 busno;
0349     u8 devfunc;
0350     u32 start;
0351     u32 end;
0352     u32 len;
0353     int type;       /* MEM, IO, PFMEM */
0354     u8 fromMem;     /* this is to indicate that the range is from
0355                  * the Memory bucket rather than from PFMem */
0356     struct resource_node *next;
0357     struct resource_node *nextRange;    /* for the other mem range on bus */
0358 };
0359
0360 struct res_needed {
0361     u32 mem;
0362     u32 pfmem;
0363     u32 io;
0364     u8 not_correct;     /* needed for return */
0365     int devices[32];    /* for device numbers behind this bridge */
0366 };
0367
0368 /* functions */
0369
0370 int ibmphp_rsrc_init(void);
0371 int ibmphp_add_resource(struct resource_node *);
0372 int ibmphp_remove_resource(struct resource_node *);
0373 int ibmphp_find_resource(struct bus_node *, u32, struct resource_node **, int);
0374 int ibmphp_check_resource(struct resource_node *, u8);
0375 int ibmphp_remove_bus(struct bus_node *, u8);
0376 void ibmphp_free_resources(void);
0377 int ibmphp_add_pfmem_from_mem(struct resource_node *);
0378 struct bus_node *ibmphp_find_res_bus(u8);
0379 void ibmphp_print_test(void);   /* for debugging purposes */
0380
0381 int ibmphp_hpc_readslot(struct slot *, u8, u8 *);
0382 int ibmphp_hpc_writeslot(struct slot *, u8);
0383 void ibmphp_lock_operations(void);
0384 void ibmphp_unlock_operations(void);
0385 int ibmphp_hpc_start_poll_thread(void);
0386 void ibmphp_hpc_stop_poll_thread(void);
0387
0388 //----------------------------------------------------------------------------
0389
0390
0391 //----------------------------------------------------------------------------
0392 // HPC return codes
0393 //----------------------------------------------------------------------------
0394 #define HPC_ERROR           0xFF
0395
0396 //-----------------------------------------------------------------------------
0397 // BUS INFO
0398 //-----------------------------------------------------------------------------
0399 #define BUS_SPEED           0x30
0400 #define BUS_MODE            0x40
0401 #define BUS_MODE_PCIX           0x01
0402 #define BUS_MODE_PCI            0x00
0403 #define BUS_SPEED_2         0x20
0404 #define BUS_SPEED_1         0x10
0405 #define BUS_SPEED_33            0x00
0406 #define BUS_SPEED_66            0x01
0407 #define BUS_SPEED_100           0x02
0408 #define BUS_SPEED_133           0x03
0409 #define BUS_SPEED_66PCIX        0x04
0410 #define BUS_SPEED_66UNKNOWN     0x05
0411 #define BUS_STATUS_AVAILABLE        0x01
0412 #define BUS_CONTROL_AVAILABLE       0x02
0413 #define SLOT_LATCH_REGS_SUPPORTED   0x10
0414
0415 #define PRGM_MODEL_REV_LEVEL        0xF0
0416 #define MAX_ADAPTER_NONE        0x09
0417
0418 //----------------------------------------------------------------------------
0419 // HPC 'write' operations/commands
0420 //----------------------------------------------------------------------------
0421 //  Command         Code    State   Write to reg
0422 //                  Machine at index
0423 //------------------------- ----    ------- ------------
0424 #define HPC_CTLR_ENABLEIRQ  0x00    // N    15
0425 #define HPC_CTLR_DISABLEIRQ 0x01    // N    15
0426 #define HPC_SLOT_OFF        0x02    // Y    0-14
0427 #define HPC_SLOT_ON     0x03    // Y    0-14
0428 #define HPC_SLOT_ATTNOFF    0x04    // N    0-14
0429 #define HPC_SLOT_ATTNON     0x05    // N    0-14
0430 #define HPC_CTLR_CLEARIRQ   0x06    // N    15
0431 #define HPC_CTLR_RESET      0x07    // Y    15
0432 #define HPC_CTLR_IRQSTEER   0x08    // N    15
0433 #define HPC_BUS_33CONVMODE  0x09    // Y    31-34
0434 #define HPC_BUS_66CONVMODE  0x0A    // Y    31-34
0435 #define HPC_BUS_66PCIXMODE  0x0B    // Y    31-34
0436 #define HPC_BUS_100PCIXMODE 0x0C    // Y    31-34
0437 #define HPC_BUS_133PCIXMODE 0x0D    // Y    31-34
0438 #define HPC_ALLSLOT_OFF     0x11    // Y    15
0439 #define HPC_ALLSLOT_ON      0x12    // Y    15
0440 #define HPC_SLOT_BLINKLED   0x13    // N    0-14
0441
0442 //----------------------------------------------------------------------------
0443 // read commands
0444 //----------------------------------------------------------------------------
0445 #define READ_SLOTSTATUS     0x01
0446 #define READ_EXTSLOTSTATUS  0x02
0447 #define READ_BUSSTATUS      0x03
0448 #define READ_CTLRSTATUS     0x04
0449 #define READ_ALLSTAT        0x05
0450 #define READ_ALLSLOT        0x06
0451 #define READ_SLOTLATCHLOWREG    0x07
0452 #define READ_REVLEVEL       0x08
0453 #define READ_HPCOPTIONS     0x09
0454 //----------------------------------------------------------------------------
0455 // slot status
0456 //----------------------------------------------------------------------------
0457 #define HPC_SLOT_POWER      0x01
0458 #define HPC_SLOT_CONNECT    0x02
0459 #define HPC_SLOT_ATTN       0x04
0460 #define HPC_SLOT_PRSNT2     0x08
0461 #define HPC_SLOT_PRSNT1     0x10
0462 #define HPC_SLOT_PWRGD      0x20
0463 #define HPC_SLOT_BUS_SPEED  0x40
0464 #define HPC_SLOT_LATCH      0x80
0465
0466 //----------------------------------------------------------------------------
0467 // HPC_SLOT_POWER status return codes
0468 //----------------------------------------------------------------------------
0469 #define HPC_SLOT_POWER_OFF  0x00
0470 #define HPC_SLOT_POWER_ON   0x01
0471
0472 //----------------------------------------------------------------------------
0473 // HPC_SLOT_CONNECT status return codes
0474 //----------------------------------------------------------------------------
0475 #define HPC_SLOT_CONNECTED  0x00
0476 #define HPC_SLOT_DISCONNECTED   0x01
0477
0478 //----------------------------------------------------------------------------
0479 // HPC_SLOT_ATTN status return codes
0480 //----------------------------------------------------------------------------
0481 #define HPC_SLOT_ATTN_OFF   0x00
0482 #define HPC_SLOT_ATTN_ON    0x01
0483 #define HPC_SLOT_ATTN_BLINK 0x02
0484
0485 //----------------------------------------------------------------------------
0486 // HPC_SLOT_PRSNT status return codes
0487 //----------------------------------------------------------------------------
0488 #define HPC_SLOT_EMPTY      0x00
0489 #define HPC_SLOT_PRSNT_7    0x01
0490 #define HPC_SLOT_PRSNT_15   0x02
0491 #define HPC_SLOT_PRSNT_25   0x03
0492
0493 //----------------------------------------------------------------------------
0494 // HPC_SLOT_PWRGD status return codes
0495 //----------------------------------------------------------------------------
0496 #define HPC_SLOT_PWRGD_FAULT_NONE   0x00
0497 #define HPC_SLOT_PWRGD_GOOD     0x01
0498
0499 //----------------------------------------------------------------------------
0500 // HPC_SLOT_BUS_SPEED status return codes
0501 //----------------------------------------------------------------------------
0502 #define HPC_SLOT_BUS_SPEED_OK   0x00
0503 #define HPC_SLOT_BUS_SPEED_MISM 0x01
0504
0505 //----------------------------------------------------------------------------
0506 // HPC_SLOT_LATCH status return codes
0507 //----------------------------------------------------------------------------
0508 #define HPC_SLOT_LATCH_OPEN 0x01    // NOTE : in PCI spec bit off = open
0509 #define HPC_SLOT_LATCH_CLOSED   0x00    // NOTE : in PCI spec bit on  = closed
0510
0511
0512 //----------------------------------------------------------------------------
0513 // extended slot status
0514 //----------------------------------------------------------------------------
0515 #define HPC_SLOT_PCIX       0x01
0516 #define HPC_SLOT_SPEED1     0x02
0517 #define HPC_SLOT_SPEED2     0x04
0518 #define HPC_SLOT_BLINK_ATTN 0x08
0519 #define HPC_SLOT_RSRVD1     0x10
0520 #define HPC_SLOT_RSRVD2     0x20
0521 #define HPC_SLOT_BUS_MODE   0x40
0522 #define HPC_SLOT_RSRVD3     0x80
0523
0524 //----------------------------------------------------------------------------
0525 // HPC_XSLOT_PCIX_CAP status return codes
0526 //----------------------------------------------------------------------------
0527 #define HPC_SLOT_PCIX_NO    0x00
0528 #define HPC_SLOT_PCIX_YES   0x01
0529
0530 //----------------------------------------------------------------------------
0531 // HPC_XSLOT_SPEED status return codes
0532 //----------------------------------------------------------------------------
0533 #define HPC_SLOT_SPEED_33   0x00
0534 #define HPC_SLOT_SPEED_66   0x01
0535 #define HPC_SLOT_SPEED_133  0x02
0536
0537 //----------------------------------------------------------------------------
0538 // HPC_XSLOT_ATTN_BLINK status return codes
0539 //----------------------------------------------------------------------------
0540 #define HPC_SLOT_ATTN_BLINK_OFF 0x00
0541 #define HPC_SLOT_ATTN_BLINK_ON  0x01
0542
0543 //----------------------------------------------------------------------------
0544 // HPC_XSLOT_BUS_MODE status return codes
0545 //----------------------------------------------------------------------------
0546 #define HPC_SLOT_BUS_MODE_OK    0x00
0547 #define HPC_SLOT_BUS_MODE_MISM  0x01
0548
0549 //----------------------------------------------------------------------------
0550 // Controller status
0551 //----------------------------------------------------------------------------
0552 #define HPC_CTLR_WORKING    0x01
0553 #define HPC_CTLR_FINISHED   0x02
0554 #define HPC_CTLR_RESULT0    0x04
0555 #define HPC_CTLR_RESULT1    0x08
0556 #define HPC_CTLR_RESULE2    0x10
0557 #define HPC_CTLR_RESULT3    0x20
0558 #define HPC_CTLR_IRQ_ROUTG  0x40
0559 #define HPC_CTLR_IRQ_PENDG  0x80
0560
0561 //----------------------------------------------------------------------------
0562 // HPC_CTLR_WORKING status return codes
0563 //----------------------------------------------------------------------------
0564 #define HPC_CTLR_WORKING_NO 0x00
0565 #define HPC_CTLR_WORKING_YES    0x01
0566
0567 //----------------------------------------------------------------------------
0568 // HPC_CTLR_FINISHED status return codes
0569 //----------------------------------------------------------------------------
0570 #define HPC_CTLR_FINISHED_NO    0x00
0571 #define HPC_CTLR_FINISHED_YES   0x01
0572
0573 //----------------------------------------------------------------------------
0574 // HPC_CTLR_RESULT status return codes
0575 //----------------------------------------------------------------------------
0576 #define HPC_CTLR_RESULT_SUCCESS 0x00
0577 #define HPC_CTLR_RESULT_FAILED  0x01
0578 #define HPC_CTLR_RESULT_RSVD    0x02
0579 #define HPC_CTLR_RESULT_NORESP  0x03
0580
0581
0582 //----------------------------------------------------------------------------
0583 // macro for slot info
0584 //----------------------------------------------------------------------------
0585 #define SLOT_POWER(s)   ((u8) ((s & HPC_SLOT_POWER) \
0586     ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))
0587
0588 #define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
0589     ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
0590
0591 #define SLOT_ATTN(s, es)    ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
0592     ? HPC_SLOT_ATTN_BLINK \
0593     : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
0594
0595 #define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \
0596     ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \
0597     : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))
0598
0599 #define SLOT_PWRGD(s)   ((u8) ((s & HPC_SLOT_PWRGD) \
0600     ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))
0601
0602 #define SLOT_BUS_SPEED(s)   ((u8) ((s & HPC_SLOT_BUS_SPEED) \
0603     ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))
0604
0605 #define SLOT_LATCH(s)   ((u8) ((s & HPC_SLOT_LATCH) \
0606     ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))
0607
0608 #define SLOT_PCIX(es)   ((u8) ((es & HPC_SLOT_PCIX) \
0609     ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))
0610
0611 #define SLOT_SPEED(es)  ((u8) ((es & HPC_SLOT_SPEED2) \
0612     ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133   \
0613                 : HPC_SLOT_SPEED_66)   \
0614     : HPC_SLOT_SPEED_33))
0615
0616 #define SLOT_BUS_MODE(es)   ((u8) ((es & HPC_SLOT_BUS_MODE) \
0617     ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))
0618
0619 //--------------------------------------------------------------------------
0620 // macro for bus info
0621 //---------------------------------------------------------------------------
0622 #define CURRENT_BUS_SPEED(s)    ((u8) (s & BUS_SPEED_2) \
0623     ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \
0624     : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))
0625
0626 #define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)
0627
0628 #define READ_BUS_STATUS(s)  ((u8) (s->options & BUS_STATUS_AVAILABLE))
0629
0630 #define READ_BUS_MODE(s)    ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)
0631
0632 #define SET_BUS_STATUS(s)   ((u8) (s->options & BUS_CONTROL_AVAILABLE))
0633
0634 #define READ_SLOT_LATCH(s)  ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))
0635
0636 //----------------------------------------------------------------------------
0637 // macro for controller info
0638 //----------------------------------------------------------------------------
0639 #define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \
0640     ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))
0641 #define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \
0642     ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))
0643 #define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1)  \
0644     ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \
0645                 : HPC_CTLR_RESULT_RSVD)  \
0646     : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \
0647                 : HPC_CTLR_RESULT_SUCCESS)))
0648
0649 // command that affect the state machine of HPC
0650 #define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF)        || \
0651                   (c == HPC_SLOT_ON)         || \
0652                   (c == HPC_CTLR_RESET)      || \
0653                   (c == HPC_BUS_33CONVMODE)  || \
0654                   (c == HPC_BUS_66CONVMODE)  || \
0655                   (c == HPC_BUS_66PCIXMODE)  || \
0656                   (c == HPC_BUS_100PCIXMODE) || \
0657                   (c == HPC_BUS_133PCIXMODE) || \
0658                   (c == HPC_ALLSLOT_OFF)     || \
0659                   (c == HPC_ALLSLOT_ON))
0660
0661
0662 /* Core part of the driver */
0663
0664 #define ENABLE      1
0665 #define DISABLE     0
0666
0667 #define CARD_INFO   0x07
0668 #define PCIX133     0x07
0669 #define PCIX66      0x05
0670 #define PCI66       0x04
0671
0672 extern struct pci_bus *ibmphp_pci_bus;
0673
0674 /* Variables */
0675
0676 struct pci_func {
0677     struct pci_dev *dev;    /* from the OS */
0678     u8 busno;
0679     u8 device;
0680     u8 function;
0681     struct resource_node *io[6];
0682     struct resource_node *mem[6];
0683     struct resource_node *pfmem[6];
0684     struct pci_func *next;
0685     int devices[32];    /* for bridge config */
0686     u8 irq[4];      /* for interrupt config */
0687     u8 bus;         /* flag for unconfiguring, to say if PPB */
0688 };
0689
0690 struct slot {
0691     u8 bus;
0692     u8 device;
0693     u8 number;
0694     u8 real_physical_slot_num;
0695     u32 capabilities;
0696     u8 supported_speed;
0697     u8 supported_bus_mode;
0698     u8 flag;        /* this is for disable slot and polling */
0699     u8 ctlr_index;
0700     struct hotplug_slot hotplug_slot;
0701     struct controller *ctrl;
0702     struct pci_func *func;
0703     u8 irq[4];
0704     int bit_mode;       /* 0 = 32, 1 = 64 */
0705     struct bus_info *bus_on;
0706     struct list_head ibm_slot_list;
0707     u8 status;
0708     u8 ext_status;
0709     u8 busstatus;
0710 };
0711
0712 struct controller {
0713     struct ebda_hpc_slot *slots;
0714     struct ebda_hpc_bus *buses;
0715     struct pci_dev *ctrl_dev; /* in case where controller is PCI */
0716     u8 starting_slot_num;   /* starting and ending slot #'s this ctrl controls*/
0717     u8 ending_slot_num;
0718     u8 revision;
0719     u8 options;     /* which options HPC supports */
0720     u8 status;
0721     u8 ctlr_id;
0722     u8 slot_count;
0723     u8 bus_count;
0724     u8 ctlr_relative_id;
0725     u32 irq;
0726     union {
0727         struct isa_ctlr_access isa_ctlr;
0728         struct pci_ctlr_access pci_ctlr;
0729         struct wpeg_i2c_ctlr_access wpeg_ctlr;
0730     } u;
0731     u8 ctlr_type;
0732     struct list_head ebda_hpc_list;
0733 };
0734
0735 /* Functions */
0736
0737 int ibmphp_init_devno(struct slot **);  /* This function is called from EBDA, so we need it not be static */
0738 int ibmphp_do_disable_slot(struct slot *slot_cur);
0739 int ibmphp_update_slot_info(struct slot *); /* This function is called from HPC, so we need it to not be static */
0740 int ibmphp_configure_card(struct pci_func *, u8);
0741 int ibmphp_unconfigure_card(struct slot **, int);
0742 extern const struct hotplug_slot_ops ibmphp_hotplug_slot_ops;
0743
0744 static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot)
0745 {
0746     return container_of(hotplug_slot, struct slot, hotplug_slot);
0747 }
0748
0749 #endif              //__IBMPHP_H
0750