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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Compaq Hot Plug Controller Driver
0004  *
0005  * Copyright (C) 1995,2001 Compaq Computer Corporation
0006  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
0007  * Copyright (C) 2001 IBM Corp.
0008  *
0009  * All rights reserved.
0010  *
0011  * Send feedback to <greg@kroah.com>
0012  *
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/kernel.h>
0017 #include <linux/types.h>
0018 #include <linux/slab.h>
0019 #include <linux/workqueue.h>
0020 #include <linux/proc_fs.h>
0021 #include <linux/pci.h>
0022 #include <linux/pci_hotplug.h>
0023 #include "../pci.h"
0024 #include "cpqphp.h"
0025 #include "cpqphp_nvram.h"
0026 
0027 
0028 u8 cpqhp_nic_irq;
0029 u8 cpqhp_disk_irq;
0030 
0031 static u16 unused_IRQ;
0032 
0033 /*
0034  * detect_HRT_floating_pointer
0035  *
0036  * find the Hot Plug Resource Table in the specified region of memory.
0037  *
0038  */
0039 static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
0040 {
0041     void __iomem *fp;
0042     void __iomem *endp;
0043     u8 temp1, temp2, temp3, temp4;
0044     int status = 0;
0045 
0046     endp = (end - sizeof(struct hrt) + 1);
0047 
0048     for (fp = begin; fp <= endp; fp += 16) {
0049         temp1 = readb(fp + SIG0);
0050         temp2 = readb(fp + SIG1);
0051         temp3 = readb(fp + SIG2);
0052         temp4 = readb(fp + SIG3);
0053         if (temp1 == '$' &&
0054             temp2 == 'H' &&
0055             temp3 == 'R' &&
0056             temp4 == 'T') {
0057             status = 1;
0058             break;
0059         }
0060     }
0061 
0062     if (!status)
0063         fp = NULL;
0064 
0065     dbg("Discovered Hotplug Resource Table at %p\n", fp);
0066     return fp;
0067 }
0068 
0069 
0070 int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
0071 {
0072     struct pci_bus *child;
0073     int num;
0074 
0075     pci_lock_rescan_remove();
0076 
0077     if (func->pci_dev == NULL)
0078         func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
0079                             PCI_DEVFN(func->device,
0080                             func->function));
0081 
0082     /* No pci device, we need to create it then */
0083     if (func->pci_dev == NULL) {
0084         dbg("INFO: pci_dev still null\n");
0085 
0086         num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
0087         if (num)
0088             pci_bus_add_devices(ctrl->pci_dev->bus);
0089 
0090         func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
0091                             PCI_DEVFN(func->device,
0092                             func->function));
0093         if (func->pci_dev == NULL) {
0094             dbg("ERROR: pci_dev still null\n");
0095             goto out;
0096         }
0097     }
0098 
0099     if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
0100         pci_hp_add_bridge(func->pci_dev);
0101         child = func->pci_dev->subordinate;
0102         if (child)
0103             pci_bus_add_devices(child);
0104     }
0105 
0106     pci_dev_put(func->pci_dev);
0107 
0108  out:
0109     pci_unlock_rescan_remove();
0110     return 0;
0111 }
0112 
0113 
0114 int cpqhp_unconfigure_device(struct pci_func *func)
0115 {
0116     int j;
0117 
0118     dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
0119 
0120     pci_lock_rescan_remove();
0121     for (j = 0; j < 8 ; j++) {
0122         struct pci_dev *temp = pci_get_domain_bus_and_slot(0,
0123                             func->bus,
0124                             PCI_DEVFN(func->device,
0125                             j));
0126         if (temp) {
0127             pci_dev_put(temp);
0128             pci_stop_and_remove_bus_device(temp);
0129         }
0130     }
0131     pci_unlock_rescan_remove();
0132     return 0;
0133 }
0134 
0135 static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
0136 {
0137     u32 vendID = 0;
0138 
0139     if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
0140         return -1;
0141     if (vendID == 0xffffffff)
0142         return -1;
0143     return pci_bus_read_config_dword(bus, devfn, offset, value);
0144 }
0145 
0146 
0147 /*
0148  * cpqhp_set_irq
0149  *
0150  * @bus_num: bus number of PCI device
0151  * @dev_num: device number of PCI device
0152  * @slot: pointer to u8 where slot number will be returned
0153  */
0154 int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
0155 {
0156     int rc = 0;
0157 
0158     if (cpqhp_legacy_mode) {
0159         struct pci_dev *fakedev;
0160         struct pci_bus *fakebus;
0161         u16 temp_word;
0162 
0163         fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
0164         fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
0165         if (!fakedev || !fakebus) {
0166             kfree(fakedev);
0167             kfree(fakebus);
0168             return -ENOMEM;
0169         }
0170 
0171         fakedev->devfn = dev_num << 3;
0172         fakedev->bus = fakebus;
0173         fakebus->number = bus_num;
0174         dbg("%s: dev %d, bus %d, pin %d, num %d\n",
0175             __func__, dev_num, bus_num, int_pin, irq_num);
0176         rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
0177         kfree(fakedev);
0178         kfree(fakebus);
0179         dbg("%s: rc %d\n", __func__, rc);
0180         if (!rc)
0181             return !rc;
0182 
0183         /* set the Edge Level Control Register (ELCR) */
0184         temp_word = inb(0x4d0);
0185         temp_word |= inb(0x4d1) << 8;
0186 
0187         temp_word |= 0x01 << irq_num;
0188 
0189         /* This should only be for x86 as it sets the Edge Level
0190          * Control Register
0191          */
0192         outb((u8)(temp_word & 0xFF), 0x4d0);
0193         outb((u8)((temp_word & 0xFF00) >> 8), 0x4d1);
0194         rc = 0;
0195     }
0196 
0197     return rc;
0198 }
0199 
0200 
0201 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num)
0202 {
0203     u16 tdevice;
0204     u32 work;
0205     u8 tbus;
0206 
0207     ctrl->pci_bus->number = bus_num;
0208 
0209     for (tdevice = 0; tdevice < 0xFF; tdevice++) {
0210         /* Scan for access first */
0211         if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
0212             continue;
0213         dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
0214         /* Yep we got one. Not a bridge ? */
0215         if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
0216             *dev_num = tdevice;
0217             dbg("found it !\n");
0218             return 0;
0219         }
0220     }
0221     for (tdevice = 0; tdevice < 0xFF; tdevice++) {
0222         /* Scan for access first */
0223         if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
0224             continue;
0225         dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
0226         /* Yep we got one. bridge ? */
0227         if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
0228             pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
0229             /* XXX: no recursion, wtf? */
0230             dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
0231             return 0;
0232         }
0233     }
0234 
0235     return -1;
0236 }
0237 
0238 
0239 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
0240 {
0241     int loop, len;
0242     u32 work;
0243     u8 tbus, tdevice, tslot;
0244 
0245     len = cpqhp_routing_table_length();
0246     for (loop = 0; loop < len; ++loop) {
0247         tbus = cpqhp_routing_table->slots[loop].bus;
0248         tdevice = cpqhp_routing_table->slots[loop].devfn;
0249         tslot = cpqhp_routing_table->slots[loop].slot;
0250 
0251         if (tslot == slot) {
0252             *bus_num = tbus;
0253             *dev_num = tdevice;
0254             ctrl->pci_bus->number = tbus;
0255             pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
0256             if (!nobridge || (work == 0xffffffff))
0257                 return 0;
0258 
0259             dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
0260             pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
0261             dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
0262 
0263             if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
0264                 pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
0265                 dbg("Scan bus for Non Bridge: bus %d\n", tbus);
0266                 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
0267                     *bus_num = tbus;
0268                     return 0;
0269                 }
0270             } else
0271                 return 0;
0272         }
0273     }
0274     return -1;
0275 }
0276 
0277 
0278 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot)
0279 {
0280     /* plain (bridges allowed) */
0281     return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
0282 }
0283 
0284 
0285 /* More PCI configuration routines; this time centered around hotplug
0286  * controller
0287  */
0288 
0289 
0290 /*
0291  * cpqhp_save_config
0292  *
0293  * Reads configuration for all slots in a PCI bus and saves info.
0294  *
0295  * Note:  For non-hot plug buses, the slot # saved is the device #
0296  *
0297  * returns 0 if success
0298  */
0299 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
0300 {
0301     long rc;
0302     u8 class_code;
0303     u8 header_type;
0304     u32 ID;
0305     u8 secondary_bus;
0306     struct pci_func *new_slot;
0307     int sub_bus;
0308     int FirstSupported;
0309     int LastSupported;
0310     int max_functions;
0311     int function;
0312     u8 DevError;
0313     int device = 0;
0314     int cloop = 0;
0315     int stop_it;
0316     int index;
0317     u16 devfn;
0318 
0319     /* Decide which slots are supported */
0320 
0321     if (is_hot_plug) {
0322         /*
0323          * is_hot_plug is the slot mask
0324          */
0325         FirstSupported = is_hot_plug >> 4;
0326         LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
0327     } else {
0328         FirstSupported = 0;
0329         LastSupported = 0x1F;
0330     }
0331 
0332     /* Save PCI configuration space for all devices in supported slots */
0333     ctrl->pci_bus->number = busnumber;
0334     for (device = FirstSupported; device <= LastSupported; device++) {
0335         ID = 0xFFFFFFFF;
0336         rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
0337 
0338         if (ID == 0xFFFFFFFF) {
0339             if (is_hot_plug) {
0340                 /* Setup slot structure with entry for empty
0341                  * slot
0342                  */
0343                 new_slot = cpqhp_slot_create(busnumber);
0344                 if (new_slot == NULL)
0345                     return 1;
0346 
0347                 new_slot->bus = (u8) busnumber;
0348                 new_slot->device = (u8) device;
0349                 new_slot->function = 0;
0350                 new_slot->is_a_board = 0;
0351                 new_slot->presence_save = 0;
0352                 new_slot->switch_save = 0;
0353             }
0354             continue;
0355         }
0356 
0357         rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
0358         if (rc)
0359             return rc;
0360 
0361         rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
0362         if (rc)
0363             return rc;
0364 
0365         /* If multi-function device, set max_functions to 8 */
0366         if (header_type & 0x80)
0367             max_functions = 8;
0368         else
0369             max_functions = 1;
0370 
0371         function = 0;
0372 
0373         do {
0374             DevError = 0;
0375             if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
0376                 /* Recurse the subordinate bus
0377                  * get the subordinate bus number
0378                  */
0379                 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
0380                 if (rc) {
0381                     return rc;
0382                 } else {
0383                     sub_bus = (int) secondary_bus;
0384 
0385                     /* Save secondary bus cfg spc
0386                      * with this recursive call.
0387                      */
0388                     rc = cpqhp_save_config(ctrl, sub_bus, 0);
0389                     if (rc)
0390                         return rc;
0391                     ctrl->pci_bus->number = busnumber;
0392                 }
0393             }
0394 
0395             index = 0;
0396             new_slot = cpqhp_slot_find(busnumber, device, index++);
0397             while (new_slot &&
0398                    (new_slot->function != (u8) function))
0399                 new_slot = cpqhp_slot_find(busnumber, device, index++);
0400 
0401             if (!new_slot) {
0402                 /* Setup slot structure. */
0403                 new_slot = cpqhp_slot_create(busnumber);
0404                 if (new_slot == NULL)
0405                     return 1;
0406             }
0407 
0408             new_slot->bus = (u8) busnumber;
0409             new_slot->device = (u8) device;
0410             new_slot->function = (u8) function;
0411             new_slot->is_a_board = 1;
0412             new_slot->switch_save = 0x10;
0413             /* In case of unsupported board */
0414             new_slot->status = DevError;
0415             devfn = (new_slot->device << 3) | new_slot->function;
0416             new_slot->pci_dev = pci_get_domain_bus_and_slot(0,
0417                             new_slot->bus, devfn);
0418 
0419             for (cloop = 0; cloop < 0x20; cloop++) {
0420                 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
0421                 if (rc)
0422                     return rc;
0423             }
0424 
0425             pci_dev_put(new_slot->pci_dev);
0426 
0427             function++;
0428 
0429             stop_it = 0;
0430 
0431             /* this loop skips to the next present function
0432              * reading in Class Code and Header type.
0433              */
0434             while ((function < max_functions) && (!stop_it)) {
0435                 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
0436                 if (ID == 0xFFFFFFFF) {
0437                     function++;
0438                     continue;
0439                 }
0440                 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
0441                 if (rc)
0442                     return rc;
0443 
0444                 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
0445                 if (rc)
0446                     return rc;
0447 
0448                 stop_it++;
0449             }
0450 
0451         } while (function < max_functions);
0452     }           /* End of FOR loop */
0453 
0454     return 0;
0455 }
0456 
0457 
0458 /*
0459  * cpqhp_save_slot_config
0460  *
0461  * Saves configuration info for all PCI devices in a given slot
0462  * including subordinate buses.
0463  *
0464  * returns 0 if success
0465  */
0466 int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot)
0467 {
0468     long rc;
0469     u8 class_code;
0470     u8 header_type;
0471     u32 ID;
0472     u8 secondary_bus;
0473     int sub_bus;
0474     int max_functions;
0475     int function = 0;
0476     int cloop;
0477     int stop_it;
0478 
0479     ID = 0xFFFFFFFF;
0480 
0481     ctrl->pci_bus->number = new_slot->bus;
0482     pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
0483 
0484     if (ID == 0xFFFFFFFF)
0485         return 2;
0486 
0487     pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
0488     pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
0489 
0490     if (header_type & 0x80) /* Multi-function device */
0491         max_functions = 8;
0492     else
0493         max_functions = 1;
0494 
0495     while (function < max_functions) {
0496         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
0497             /*  Recurse the subordinate bus */
0498             pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
0499 
0500             sub_bus = (int) secondary_bus;
0501 
0502             /* Save the config headers for the secondary
0503              * bus.
0504              */
0505             rc = cpqhp_save_config(ctrl, sub_bus, 0);
0506             if (rc)
0507                 return(rc);
0508             ctrl->pci_bus->number = new_slot->bus;
0509 
0510         }
0511 
0512         new_slot->status = 0;
0513 
0514         for (cloop = 0; cloop < 0x20; cloop++)
0515             pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
0516 
0517         function++;
0518 
0519         stop_it = 0;
0520 
0521         /* this loop skips to the next present function
0522          * reading in the Class Code and the Header type.
0523          */
0524         while ((function < max_functions) && (!stop_it)) {
0525             pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
0526 
0527             if (ID == 0xFFFFFFFF)
0528                 function++;
0529             else {
0530                 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
0531                 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
0532                 stop_it++;
0533             }
0534         }
0535 
0536     }
0537 
0538     return 0;
0539 }
0540 
0541 
0542 /*
0543  * cpqhp_save_base_addr_length
0544  *
0545  * Saves the length of all base address registers for the
0546  * specified slot.  this is for hot plug REPLACE
0547  *
0548  * returns 0 if success
0549  */
0550 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func)
0551 {
0552     u8 cloop;
0553     u8 header_type;
0554     u8 secondary_bus;
0555     u8 type;
0556     int sub_bus;
0557     u32 temp_register;
0558     u32 base;
0559     u32 rc;
0560     struct pci_func *next;
0561     int index = 0;
0562     struct pci_bus *pci_bus = ctrl->pci_bus;
0563     unsigned int devfn;
0564 
0565     func = cpqhp_slot_find(func->bus, func->device, index++);
0566 
0567     while (func != NULL) {
0568         pci_bus->number = func->bus;
0569         devfn = PCI_DEVFN(func->device, func->function);
0570 
0571         /* Check for Bridge */
0572         pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
0573 
0574         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
0575             pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
0576 
0577             sub_bus = (int) secondary_bus;
0578 
0579             next = cpqhp_slot_list[sub_bus];
0580 
0581             while (next != NULL) {
0582                 rc = cpqhp_save_base_addr_length(ctrl, next);
0583                 if (rc)
0584                     return rc;
0585 
0586                 next = next->next;
0587             }
0588             pci_bus->number = func->bus;
0589 
0590             /* FIXME: this loop is duplicated in the non-bridge
0591              * case.  The two could be rolled together Figure out
0592              * IO and memory base lengths
0593              */
0594             for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
0595                 temp_register = 0xFFFFFFFF;
0596                 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
0597                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
0598                 /* If this register is implemented */
0599                 if (base) {
0600                     if (base & 0x01L) {
0601                         /* IO base
0602                          * set base = amount of IO space
0603                          * requested
0604                          */
0605                         base = base & 0xFFFFFFFE;
0606                         base = (~base) + 1;
0607 
0608                         type = 1;
0609                     } else {
0610                         /* memory base */
0611                         base = base & 0xFFFFFFF0;
0612                         base = (~base) + 1;
0613 
0614                         type = 0;
0615                     }
0616                 } else {
0617                     base = 0x0L;
0618                     type = 0;
0619                 }
0620 
0621                 /* Save information in slot structure */
0622                 func->base_length[(cloop - 0x10) >> 2] =
0623                 base;
0624                 func->base_type[(cloop - 0x10) >> 2] = type;
0625 
0626             }   /* End of base register loop */
0627 
0628         } else if ((header_type & 0x7F) == 0x00) {
0629             /* Figure out IO and memory base lengths */
0630             for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
0631                 temp_register = 0xFFFFFFFF;
0632                 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
0633                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
0634 
0635                 /* If this register is implemented */
0636                 if (base) {
0637                     if (base & 0x01L) {
0638                         /* IO base
0639                          * base = amount of IO space
0640                          * requested
0641                          */
0642                         base = base & 0xFFFFFFFE;
0643                         base = (~base) + 1;
0644 
0645                         type = 1;
0646                     } else {
0647                         /* memory base
0648                          * base = amount of memory
0649                          * space requested
0650                          */
0651                         base = base & 0xFFFFFFF0;
0652                         base = (~base) + 1;
0653 
0654                         type = 0;
0655                     }
0656                 } else {
0657                     base = 0x0L;
0658                     type = 0;
0659                 }
0660 
0661                 /* Save information in slot structure */
0662                 func->base_length[(cloop - 0x10) >> 2] = base;
0663                 func->base_type[(cloop - 0x10) >> 2] = type;
0664 
0665             }   /* End of base register loop */
0666 
0667         } else {      /* Some other unknown header type */
0668         }
0669 
0670         /* find the next device in this slot */
0671         func = cpqhp_slot_find(func->bus, func->device, index++);
0672     }
0673 
0674     return(0);
0675 }
0676 
0677 
0678 /*
0679  * cpqhp_save_used_resources
0680  *
0681  * Stores used resource information for existing boards.  this is
0682  * for boards that were in the system when this driver was loaded.
0683  * this function is for hot plug ADD
0684  *
0685  * returns 0 if success
0686  */
0687 int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func)
0688 {
0689     u8 cloop;
0690     u8 header_type;
0691     u8 secondary_bus;
0692     u8 temp_byte;
0693     u8 b_base;
0694     u8 b_length;
0695     u16 command;
0696     u16 save_command;
0697     u16 w_base;
0698     u16 w_length;
0699     u32 temp_register;
0700     u32 save_base;
0701     u32 base;
0702     int index = 0;
0703     struct pci_resource *mem_node;
0704     struct pci_resource *p_mem_node;
0705     struct pci_resource *io_node;
0706     struct pci_resource *bus_node;
0707     struct pci_bus *pci_bus = ctrl->pci_bus;
0708     unsigned int devfn;
0709 
0710     func = cpqhp_slot_find(func->bus, func->device, index++);
0711 
0712     while ((func != NULL) && func->is_a_board) {
0713         pci_bus->number = func->bus;
0714         devfn = PCI_DEVFN(func->device, func->function);
0715 
0716         /* Save the command register */
0717         pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
0718 
0719         /* disable card */
0720         command = 0x00;
0721         pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
0722 
0723         /* Check for Bridge */
0724         pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
0725 
0726         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
0727             /* Clear Bridge Control Register */
0728             command = 0x00;
0729             pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
0730             pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
0731             pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
0732 
0733             bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
0734             if (!bus_node)
0735                 return -ENOMEM;
0736 
0737             bus_node->base = secondary_bus;
0738             bus_node->length = temp_byte - secondary_bus + 1;
0739 
0740             bus_node->next = func->bus_head;
0741             func->bus_head = bus_node;
0742 
0743             /* Save IO base and Limit registers */
0744             pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
0745             pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
0746 
0747             if ((b_base <= b_length) && (save_command & 0x01)) {
0748                 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
0749                 if (!io_node)
0750                     return -ENOMEM;
0751 
0752                 io_node->base = (b_base & 0xF0) << 8;
0753                 io_node->length = (b_length - b_base + 0x10) << 8;
0754 
0755                 io_node->next = func->io_head;
0756                 func->io_head = io_node;
0757             }
0758 
0759             /* Save memory base and Limit registers */
0760             pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
0761             pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
0762 
0763             if ((w_base <= w_length) && (save_command & 0x02)) {
0764                 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
0765                 if (!mem_node)
0766                     return -ENOMEM;
0767 
0768                 mem_node->base = w_base << 16;
0769                 mem_node->length = (w_length - w_base + 0x10) << 16;
0770 
0771                 mem_node->next = func->mem_head;
0772                 func->mem_head = mem_node;
0773             }
0774 
0775             /* Save prefetchable memory base and Limit registers */
0776             pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
0777             pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
0778 
0779             if ((w_base <= w_length) && (save_command & 0x02)) {
0780                 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
0781                 if (!p_mem_node)
0782                     return -ENOMEM;
0783 
0784                 p_mem_node->base = w_base << 16;
0785                 p_mem_node->length = (w_length - w_base + 0x10) << 16;
0786 
0787                 p_mem_node->next = func->p_mem_head;
0788                 func->p_mem_head = p_mem_node;
0789             }
0790             /* Figure out IO and memory base lengths */
0791             for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
0792                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
0793 
0794                 temp_register = 0xFFFFFFFF;
0795                 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
0796                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
0797 
0798                 temp_register = base;
0799 
0800                 /* If this register is implemented */
0801                 if (base) {
0802                     if (((base & 0x03L) == 0x01)
0803                         && (save_command & 0x01)) {
0804                         /* IO base
0805                          * set temp_register = amount
0806                          * of IO space requested
0807                          */
0808                         temp_register = base & 0xFFFFFFFE;
0809                         temp_register = (~temp_register) + 1;
0810 
0811                         io_node = kmalloc(sizeof(*io_node),
0812                                 GFP_KERNEL);
0813                         if (!io_node)
0814                             return -ENOMEM;
0815 
0816                         io_node->base =
0817                         save_base & (~0x03L);
0818                         io_node->length = temp_register;
0819 
0820                         io_node->next = func->io_head;
0821                         func->io_head = io_node;
0822                     } else
0823                         if (((base & 0x0BL) == 0x08)
0824                             && (save_command & 0x02)) {
0825                         /* prefetchable memory base */
0826                         temp_register = base & 0xFFFFFFF0;
0827                         temp_register = (~temp_register) + 1;
0828 
0829                         p_mem_node = kmalloc(sizeof(*p_mem_node),
0830                                 GFP_KERNEL);
0831                         if (!p_mem_node)
0832                             return -ENOMEM;
0833 
0834                         p_mem_node->base = save_base & (~0x0FL);
0835                         p_mem_node->length = temp_register;
0836 
0837                         p_mem_node->next = func->p_mem_head;
0838                         func->p_mem_head = p_mem_node;
0839                     } else
0840                         if (((base & 0x0BL) == 0x00)
0841                             && (save_command & 0x02)) {
0842                         /* prefetchable memory base */
0843                         temp_register = base & 0xFFFFFFF0;
0844                         temp_register = (~temp_register) + 1;
0845 
0846                         mem_node = kmalloc(sizeof(*mem_node),
0847                                 GFP_KERNEL);
0848                         if (!mem_node)
0849                             return -ENOMEM;
0850 
0851                         mem_node->base = save_base & (~0x0FL);
0852                         mem_node->length = temp_register;
0853 
0854                         mem_node->next = func->mem_head;
0855                         func->mem_head = mem_node;
0856                     } else
0857                         return(1);
0858                 }
0859             }   /* End of base register loop */
0860         /* Standard header */
0861         } else if ((header_type & 0x7F) == 0x00) {
0862             /* Figure out IO and memory base lengths */
0863             for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
0864                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
0865 
0866                 temp_register = 0xFFFFFFFF;
0867                 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
0868                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
0869 
0870                 temp_register = base;
0871 
0872                 /* If this register is implemented */
0873                 if (base) {
0874                     if (((base & 0x03L) == 0x01)
0875                         && (save_command & 0x01)) {
0876                         /* IO base
0877                          * set temp_register = amount
0878                          * of IO space requested
0879                          */
0880                         temp_register = base & 0xFFFFFFFE;
0881                         temp_register = (~temp_register) + 1;
0882 
0883                         io_node = kmalloc(sizeof(*io_node),
0884                                 GFP_KERNEL);
0885                         if (!io_node)
0886                             return -ENOMEM;
0887 
0888                         io_node->base = save_base & (~0x01L);
0889                         io_node->length = temp_register;
0890 
0891                         io_node->next = func->io_head;
0892                         func->io_head = io_node;
0893                     } else
0894                         if (((base & 0x0BL) == 0x08)
0895                             && (save_command & 0x02)) {
0896                         /* prefetchable memory base */
0897                         temp_register = base & 0xFFFFFFF0;
0898                         temp_register = (~temp_register) + 1;
0899 
0900                         p_mem_node = kmalloc(sizeof(*p_mem_node),
0901                                 GFP_KERNEL);
0902                         if (!p_mem_node)
0903                             return -ENOMEM;
0904 
0905                         p_mem_node->base = save_base & (~0x0FL);
0906                         p_mem_node->length = temp_register;
0907 
0908                         p_mem_node->next = func->p_mem_head;
0909                         func->p_mem_head = p_mem_node;
0910                     } else
0911                         if (((base & 0x0BL) == 0x00)
0912                             && (save_command & 0x02)) {
0913                         /* prefetchable memory base */
0914                         temp_register = base & 0xFFFFFFF0;
0915                         temp_register = (~temp_register) + 1;
0916 
0917                         mem_node = kmalloc(sizeof(*mem_node),
0918                                 GFP_KERNEL);
0919                         if (!mem_node)
0920                             return -ENOMEM;
0921 
0922                         mem_node->base = save_base & (~0x0FL);
0923                         mem_node->length = temp_register;
0924 
0925                         mem_node->next = func->mem_head;
0926                         func->mem_head = mem_node;
0927                     } else
0928                         return(1);
0929                 }
0930             }   /* End of base register loop */
0931         }
0932 
0933         /* find the next device in this slot */
0934         func = cpqhp_slot_find(func->bus, func->device, index++);
0935     }
0936 
0937     return 0;
0938 }
0939 
0940 
0941 /*
0942  * cpqhp_configure_board
0943  *
0944  * Copies saved configuration information to one slot.
0945  * this is called recursively for bridge devices.
0946  * this is for hot plug REPLACE!
0947  *
0948  * returns 0 if success
0949  */
0950 int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func)
0951 {
0952     int cloop;
0953     u8 header_type;
0954     u8 secondary_bus;
0955     int sub_bus;
0956     struct pci_func *next;
0957     u32 temp;
0958     u32 rc;
0959     int index = 0;
0960     struct pci_bus *pci_bus = ctrl->pci_bus;
0961     unsigned int devfn;
0962 
0963     func = cpqhp_slot_find(func->bus, func->device, index++);
0964 
0965     while (func != NULL) {
0966         pci_bus->number = func->bus;
0967         devfn = PCI_DEVFN(func->device, func->function);
0968 
0969         /* Start at the top of config space so that the control
0970          * registers are programmed last
0971          */
0972         for (cloop = 0x3C; cloop > 0; cloop -= 4)
0973             pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
0974 
0975         pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
0976 
0977         /* If this is a bridge device, restore subordinate devices */
0978         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
0979             pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
0980 
0981             sub_bus = (int) secondary_bus;
0982 
0983             next = cpqhp_slot_list[sub_bus];
0984 
0985             while (next != NULL) {
0986                 rc = cpqhp_configure_board(ctrl, next);
0987                 if (rc)
0988                     return rc;
0989 
0990                 next = next->next;
0991             }
0992         } else {
0993 
0994             /* Check all the base Address Registers to make sure
0995              * they are the same.  If not, the board is different.
0996              */
0997 
0998             for (cloop = 16; cloop < 40; cloop += 4) {
0999                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp);
1000 
1001                 if (temp != func->config_space[cloop >> 2]) {
1002                     dbg("Config space compare failure!!! offset = %x\n", cloop);
1003                     dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
1004                     dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
1005                     return 1;
1006                 }
1007             }
1008         }
1009 
1010         func->configured = 1;
1011 
1012         func = cpqhp_slot_find(func->bus, func->device, index++);
1013     }
1014 
1015     return 0;
1016 }
1017 
1018 
1019 /*
1020  * cpqhp_valid_replace
1021  *
1022  * this function checks to see if a board is the same as the
1023  * one it is replacing.  this check will detect if the device's
1024  * vendor or device id's are the same
1025  *
1026  * returns 0 if the board is the same nonzero otherwise
1027  */
1028 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func)
1029 {
1030     u8 cloop;
1031     u8 header_type;
1032     u8 secondary_bus;
1033     u8 type;
1034     u32 temp_register = 0;
1035     u32 base;
1036     u32 rc;
1037     struct pci_func *next;
1038     int index = 0;
1039     struct pci_bus *pci_bus = ctrl->pci_bus;
1040     unsigned int devfn;
1041 
1042     if (!func->is_a_board)
1043         return(ADD_NOT_SUPPORTED);
1044 
1045     func = cpqhp_slot_find(func->bus, func->device, index++);
1046 
1047     while (func != NULL) {
1048         pci_bus->number = func->bus;
1049         devfn = PCI_DEVFN(func->device, func->function);
1050 
1051         pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
1052 
1053         /* No adapter present */
1054         if (temp_register == 0xFFFFFFFF)
1055             return(NO_ADAPTER_PRESENT);
1056 
1057         if (temp_register != func->config_space[0])
1058             return(ADAPTER_NOT_SAME);
1059 
1060         /* Check for same revision number and class code */
1061         pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
1062 
1063         /* Adapter not the same */
1064         if (temp_register != func->config_space[0x08 >> 2])
1065             return(ADAPTER_NOT_SAME);
1066 
1067         /* Check for Bridge */
1068         pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1069 
1070         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1071             /* In order to continue checking, we must program the
1072              * bus registers in the bridge to respond to accesses
1073              * for its subordinate bus(es)
1074              */
1075 
1076             temp_register = func->config_space[0x18 >> 2];
1077             pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
1078 
1079             secondary_bus = (temp_register >> 8) & 0xFF;
1080 
1081             next = cpqhp_slot_list[secondary_bus];
1082 
1083             while (next != NULL) {
1084                 rc = cpqhp_valid_replace(ctrl, next);
1085                 if (rc)
1086                     return rc;
1087 
1088                 next = next->next;
1089             }
1090 
1091         }
1092         /* Check to see if it is a standard config header */
1093         else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
1094             /* Check subsystem vendor and ID */
1095             pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
1096 
1097             if (temp_register != func->config_space[0x2C >> 2]) {
1098                 /* If it's a SMART-2 and the register isn't
1099                  * filled in, ignore the difference because
1100                  * they just have an old rev of the firmware
1101                  */
1102                 if (!((func->config_space[0] == 0xAE100E11)
1103                       && (temp_register == 0x00L)))
1104                     return(ADAPTER_NOT_SAME);
1105             }
1106             /* Figure out IO and memory base lengths */
1107             for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
1108                 temp_register = 0xFFFFFFFF;
1109                 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
1110                 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
1111 
1112                 /* If this register is implemented */
1113                 if (base) {
1114                     if (base & 0x01L) {
1115                         /* IO base
1116                          * set base = amount of IO
1117                          * space requested
1118                          */
1119                         base = base & 0xFFFFFFFE;
1120                         base = (~base) + 1;
1121 
1122                         type = 1;
1123                     } else {
1124                         /* memory base */
1125                         base = base & 0xFFFFFFF0;
1126                         base = (~base) + 1;
1127 
1128                         type = 0;
1129                     }
1130                 } else {
1131                     base = 0x0L;
1132                     type = 0;
1133                 }
1134 
1135                 /* Check information in slot structure */
1136                 if (func->base_length[(cloop - 0x10) >> 2] != base)
1137                     return(ADAPTER_NOT_SAME);
1138 
1139                 if (func->base_type[(cloop - 0x10) >> 2] != type)
1140                     return(ADAPTER_NOT_SAME);
1141 
1142             }   /* End of base register loop */
1143 
1144         }       /* End of (type 0 config space) else */
1145         else {
1146             /* this is not a type 0 or 1 config space header so
1147              * we don't know how to do it
1148              */
1149             return(DEVICE_TYPE_NOT_SUPPORTED);
1150         }
1151 
1152         /* Get the next function */
1153         func = cpqhp_slot_find(func->bus, func->device, index++);
1154     }
1155 
1156 
1157     return 0;
1158 }
1159 
1160 
1161 /*
1162  * cpqhp_find_available_resources
1163  *
1164  * Finds available memory, IO, and IRQ resources for programming
1165  * devices which may be added to the system
1166  * this function is for hot plug ADD!
1167  *
1168  * returns 0 if success
1169  */
1170 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
1171 {
1172     u8 temp;
1173     u8 populated_slot;
1174     u8 bridged_slot;
1175     void __iomem *one_slot;
1176     void __iomem *rom_resource_table;
1177     struct pci_func *func = NULL;
1178     int i = 10, index;
1179     u32 temp_dword, rc;
1180     struct pci_resource *mem_node;
1181     struct pci_resource *p_mem_node;
1182     struct pci_resource *io_node;
1183     struct pci_resource *bus_node;
1184 
1185     rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
1186     dbg("rom_resource_table = %p\n", rom_resource_table);
1187 
1188     if (rom_resource_table == NULL)
1189         return -ENODEV;
1190 
1191     /* Sum all resources and setup resource maps */
1192     unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
1193     dbg("unused_IRQ = %x\n", unused_IRQ);
1194 
1195     temp = 0;
1196     while (unused_IRQ) {
1197         if (unused_IRQ & 1) {
1198             cpqhp_disk_irq = temp;
1199             break;
1200         }
1201         unused_IRQ = unused_IRQ >> 1;
1202         temp++;
1203     }
1204 
1205     dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
1206     unused_IRQ = unused_IRQ >> 1;
1207     temp++;
1208 
1209     while (unused_IRQ) {
1210         if (unused_IRQ & 1) {
1211             cpqhp_nic_irq = temp;
1212             break;
1213         }
1214         unused_IRQ = unused_IRQ >> 1;
1215         temp++;
1216     }
1217 
1218     dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
1219     unused_IRQ = readl(rom_resource_table + PCIIRQ);
1220 
1221     temp = 0;
1222 
1223     if (!cpqhp_nic_irq)
1224         cpqhp_nic_irq = ctrl->cfgspc_irq;
1225 
1226     if (!cpqhp_disk_irq)
1227         cpqhp_disk_irq = ctrl->cfgspc_irq;
1228 
1229     dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
1230 
1231     rc = compaq_nvram_load(rom_start, ctrl);
1232     if (rc)
1233         return rc;
1234 
1235     one_slot = rom_resource_table + sizeof(struct hrt);
1236 
1237     i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
1238     dbg("number_of_entries = %d\n", i);
1239 
1240     if (!readb(one_slot + SECONDARY_BUS))
1241         return 1;
1242 
1243     dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1244 
1245     while (i && readb(one_slot + SECONDARY_BUS)) {
1246         u8 dev_func = readb(one_slot + DEV_FUNC);
1247         u8 primary_bus = readb(one_slot + PRIMARY_BUS);
1248         u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
1249         u8 max_bus = readb(one_slot + MAX_BUS);
1250         u16 io_base = readw(one_slot + IO_BASE);
1251         u16 io_length = readw(one_slot + IO_LENGTH);
1252         u16 mem_base = readw(one_slot + MEM_BASE);
1253         u16 mem_length = readw(one_slot + MEM_LENGTH);
1254         u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
1255         u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
1256 
1257         dbg("%2.2x | %4.4x  | %4.4x | %4.4x   | %4.4x | %4.4x   | %4.4x |%2.2x %2.2x %2.2x\n",
1258             dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
1259             primary_bus, secondary_bus, max_bus);
1260 
1261         /* If this entry isn't for our controller's bus, ignore it */
1262         if (primary_bus != ctrl->bus) {
1263             i--;
1264             one_slot += sizeof(struct slot_rt);
1265             continue;
1266         }
1267         /* find out if this entry is for an occupied slot */
1268         ctrl->pci_bus->number = primary_bus;
1269         pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
1270         dbg("temp_D_word = %x\n", temp_dword);
1271 
1272         if (temp_dword != 0xFFFFFFFF) {
1273             index = 0;
1274             func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
1275 
1276             while (func && (func->function != (dev_func & 0x07))) {
1277                 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
1278                 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
1279             }
1280 
1281             /* If we can't find a match, skip this table entry */
1282             if (!func) {
1283                 i--;
1284                 one_slot += sizeof(struct slot_rt);
1285                 continue;
1286             }
1287             /* this may not work and shouldn't be used */
1288             if (secondary_bus != primary_bus)
1289                 bridged_slot = 1;
1290             else
1291                 bridged_slot = 0;
1292 
1293             populated_slot = 1;
1294         } else {
1295             populated_slot = 0;
1296             bridged_slot = 0;
1297         }
1298 
1299 
1300         /* If we've got a valid IO base, use it */
1301 
1302         temp_dword = io_base + io_length;
1303 
1304         if ((io_base) && (temp_dword < 0x10000)) {
1305             io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
1306             if (!io_node)
1307                 return -ENOMEM;
1308 
1309             io_node->base = io_base;
1310             io_node->length = io_length;
1311 
1312             dbg("found io_node(base, length) = %x, %x\n",
1313                     io_node->base, io_node->length);
1314             dbg("populated slot =%d \n", populated_slot);
1315             if (!populated_slot) {
1316                 io_node->next = ctrl->io_head;
1317                 ctrl->io_head = io_node;
1318             } else {
1319                 io_node->next = func->io_head;
1320                 func->io_head = io_node;
1321             }
1322         }
1323 
1324         /* If we've got a valid memory base, use it */
1325         temp_dword = mem_base + mem_length;
1326         if ((mem_base) && (temp_dword < 0x10000)) {
1327             mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
1328             if (!mem_node)
1329                 return -ENOMEM;
1330 
1331             mem_node->base = mem_base << 16;
1332 
1333             mem_node->length = mem_length << 16;
1334 
1335             dbg("found mem_node(base, length) = %x, %x\n",
1336                     mem_node->base, mem_node->length);
1337             dbg("populated slot =%d \n", populated_slot);
1338             if (!populated_slot) {
1339                 mem_node->next = ctrl->mem_head;
1340                 ctrl->mem_head = mem_node;
1341             } else {
1342                 mem_node->next = func->mem_head;
1343                 func->mem_head = mem_node;
1344             }
1345         }
1346 
1347         /* If we've got a valid prefetchable memory base, and
1348          * the base + length isn't greater than 0xFFFF
1349          */
1350         temp_dword = pre_mem_base + pre_mem_length;
1351         if ((pre_mem_base) && (temp_dword < 0x10000)) {
1352             p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
1353             if (!p_mem_node)
1354                 return -ENOMEM;
1355 
1356             p_mem_node->base = pre_mem_base << 16;
1357 
1358             p_mem_node->length = pre_mem_length << 16;
1359             dbg("found p_mem_node(base, length) = %x, %x\n",
1360                     p_mem_node->base, p_mem_node->length);
1361             dbg("populated slot =%d \n", populated_slot);
1362 
1363             if (!populated_slot) {
1364                 p_mem_node->next = ctrl->p_mem_head;
1365                 ctrl->p_mem_head = p_mem_node;
1366             } else {
1367                 p_mem_node->next = func->p_mem_head;
1368                 func->p_mem_head = p_mem_node;
1369             }
1370         }
1371 
1372         /* If we've got a valid bus number, use it
1373          * The second condition is to ignore bus numbers on
1374          * populated slots that don't have PCI-PCI bridges
1375          */
1376         if (secondary_bus && (secondary_bus != primary_bus)) {
1377             bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
1378             if (!bus_node)
1379                 return -ENOMEM;
1380 
1381             bus_node->base = secondary_bus;
1382             bus_node->length = max_bus - secondary_bus + 1;
1383             dbg("found bus_node(base, length) = %x, %x\n",
1384                     bus_node->base, bus_node->length);
1385             dbg("populated slot =%d \n", populated_slot);
1386             if (!populated_slot) {
1387                 bus_node->next = ctrl->bus_head;
1388                 ctrl->bus_head = bus_node;
1389             } else {
1390                 bus_node->next = func->bus_head;
1391                 func->bus_head = bus_node;
1392             }
1393         }
1394 
1395         i--;
1396         one_slot += sizeof(struct slot_rt);
1397     }
1398 
1399     /* If all of the following fail, we don't have any resources for
1400      * hot plug add
1401      */
1402     rc = 1;
1403     rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
1404     rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
1405     rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
1406     rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
1407 
1408     return rc;
1409 }
1410 
1411 
1412 /*
1413  * cpqhp_return_board_resources
1414  *
1415  * this routine returns all resources allocated to a board to
1416  * the available pool.
1417  *
1418  * returns 0 if success
1419  */
1420 int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources)
1421 {
1422     int rc = 0;
1423     struct pci_resource *node;
1424     struct pci_resource *t_node;
1425     dbg("%s\n", __func__);
1426 
1427     if (!func)
1428         return 1;
1429 
1430     node = func->io_head;
1431     func->io_head = NULL;
1432     while (node) {
1433         t_node = node->next;
1434         return_resource(&(resources->io_head), node);
1435         node = t_node;
1436     }
1437 
1438     node = func->mem_head;
1439     func->mem_head = NULL;
1440     while (node) {
1441         t_node = node->next;
1442         return_resource(&(resources->mem_head), node);
1443         node = t_node;
1444     }
1445 
1446     node = func->p_mem_head;
1447     func->p_mem_head = NULL;
1448     while (node) {
1449         t_node = node->next;
1450         return_resource(&(resources->p_mem_head), node);
1451         node = t_node;
1452     }
1453 
1454     node = func->bus_head;
1455     func->bus_head = NULL;
1456     while (node) {
1457         t_node = node->next;
1458         return_resource(&(resources->bus_head), node);
1459         node = t_node;
1460     }
1461 
1462     rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
1463     rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
1464     rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
1465     rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
1466 
1467     return rc;
1468 }
1469 
1470 
1471 /*
1472  * cpqhp_destroy_resource_list
1473  *
1474  * Puts node back in the resource list pointed to by head
1475  */
1476 void cpqhp_destroy_resource_list(struct resource_lists *resources)
1477 {
1478     struct pci_resource *res, *tres;
1479 
1480     res = resources->io_head;
1481     resources->io_head = NULL;
1482 
1483     while (res) {
1484         tres = res;
1485         res = res->next;
1486         kfree(tres);
1487     }
1488 
1489     res = resources->mem_head;
1490     resources->mem_head = NULL;
1491 
1492     while (res) {
1493         tres = res;
1494         res = res->next;
1495         kfree(tres);
1496     }
1497 
1498     res = resources->p_mem_head;
1499     resources->p_mem_head = NULL;
1500 
1501     while (res) {
1502         tres = res;
1503         res = res->next;
1504         kfree(tres);
1505     }
1506 
1507     res = resources->bus_head;
1508     resources->bus_head = NULL;
1509 
1510     while (res) {
1511         tres = res;
1512         res = res->next;
1513         kfree(tres);
1514     }
1515 }
1516 
1517 
1518 /*
1519  * cpqhp_destroy_board_resources
1520  *
1521  * Puts node back in the resource list pointed to by head
1522  */
1523 void cpqhp_destroy_board_resources(struct pci_func *func)
1524 {
1525     struct pci_resource *res, *tres;
1526 
1527     res = func->io_head;
1528     func->io_head = NULL;
1529 
1530     while (res) {
1531         tres = res;
1532         res = res->next;
1533         kfree(tres);
1534     }
1535 
1536     res = func->mem_head;
1537     func->mem_head = NULL;
1538 
1539     while (res) {
1540         tres = res;
1541         res = res->next;
1542         kfree(tres);
1543     }
1544 
1545     res = func->p_mem_head;
1546     func->p_mem_head = NULL;
1547 
1548     while (res) {
1549         tres = res;
1550         res = res->next;
1551         kfree(tres);
1552     }
1553 
1554     res = func->bus_head;
1555     func->bus_head = NULL;
1556 
1557     while (res) {
1558         tres = res;
1559         res = res->next;
1560         kfree(tres);
1561     }
1562 }
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