pci/hotplug/cpcihp_zt5550.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * cpcihp_zt5550.h
0004  *
0005  * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions
0006  *
0007  * Copyright 2002 SOMA Networks, Inc.
0008  * Copyright 2001 Intel San Luis Obispo
0009  * Copyright 2000,2001 MontaVista Software Inc.
0010  *
0011  * Send feedback to <scottm@somanetworks.com>
0012  */
0013
0014 #ifndef _CPCIHP_ZT5550_H
0015 #define _CPCIHP_ZT5550_H
0016
0017 /* Direct registers */
0018 #define CSR_HCINDEX     0x00
0019 #define CSR_HCDATA      0x04
0020 #define CSR_INTSTAT     0x08
0021 #define CSR_INTMASK     0x09
0022 #define CSR_CNT0CMD     0x0C
0023 #define CSR_CNT1CMD     0x0E
0024 #define CSR_CNT0        0x10
0025 #define CSR_CNT1        0x14
0026
0027 /* Masks for interrupt bits in CSR_INTMASK direct register */
0028 #define CNT0_INT_MASK       0x01
0029 #define CNT1_INT_MASK       0x02
0030 #define ENUM_INT_MASK       0x04
0031 #define ALL_DIRECT_INTS_MASK    0x07
0032
0033 /* Indexed registers (through CSR_INDEX, CSR_DATA) */
0034 #define HC_INT_MASK_REG     0x04
0035 #define HC_STATUS_REG       0x08
0036 #define HC_CMD_REG      0x0C
0037 #define ARB_CONFIG_GNT_REG  0x10
0038 #define ARB_CONFIG_CFG_REG  0x12
0039 #define ARB_CONFIG_REG      0x10
0040 #define ISOL_CONFIG_REG     0x18
0041 #define FAULT_STATUS_REG    0x20
0042 #define FAULT_CONFIG_REG    0x24
0043 #define WD_CONFIG_REG       0x2C
0044 #define HC_DIAG_REG     0x30
0045 #define SERIAL_COMM_REG     0x34
0046 #define SERIAL_OUT_REG      0x38
0047 #define SERIAL_IN_REG       0x3C
0048
0049 /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */
0050 #define SERIAL_INT_MASK     0x01
0051 #define FAULT_INT_MASK      0x02
0052 #define HCF_INT_MASK        0x04
0053 #define ALL_INDEXED_INTS_MASK   0x07
0054
0055 /* Digital I/O port storing ENUM# */
0056 #define ENUM_PORT   0xE1
0057 /* Mask to get to the ENUM# bit on the bus */
0058 #define ENUM_MASK   0x40
0059
0060 #endif              /* _CPCIHP_ZT5550_H */