pci/hotplug/cpcihp_zt5550.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * cpcihp_zt5550.c
0004  *
0005  * Intel/Ziatech ZT5550 CompactPCI Host Controller driver
0006  *
0007  * Copyright 2002 SOMA Networks, Inc.
0008  * Copyright 2001 Intel San Luis Obispo
0009  * Copyright 2000,2001 MontaVista Software Inc.
0010  *
0011  * Send feedback to <scottm@somanetworks.com>
0012  */
0013
0014 #include <linux/module.h>
0015 #include <linux/moduleparam.h>
0016 #include <linux/init.h>
0017 #include <linux/errno.h>
0018 #include <linux/pci.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/signal.h>   /* IRQF_SHARED */
0021 #include "cpci_hotplug.h"
0022 #include "cpcihp_zt5550.h"
0023
0024 #define DRIVER_VERSION  "0.2"
0025 #define DRIVER_AUTHOR   "Scott Murray <scottm@somanetworks.com>"
0026 #define DRIVER_DESC "ZT5550 CompactPCI Hot Plug Driver"
0027
0028 #define MY_NAME "cpcihp_zt5550"
0029
0030 #define dbg(format, arg...)                 \
0031     do {                            \
0032         if (debug)                  \
0033             printk(KERN_DEBUG "%s: " format "\n",   \
0034                 MY_NAME, ## arg);       \
0035     } while (0)
0036 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
0037 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
0038 #define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
0039
0040 /* local variables */
0041 static bool debug;
0042 static bool poll;
0043 static struct cpci_hp_controller_ops zt5550_hpc_ops;
0044 static struct cpci_hp_controller zt5550_hpc;
0045
0046 /* Primary cPCI bus bridge device */
0047 static struct pci_dev *bus0_dev;
0048 static struct pci_bus *bus0;
0049
0050 /* Host controller device */
0051 static struct pci_dev *hc_dev;
0052
0053 /* Host controller register addresses */
0054 static void __iomem *hc_registers;
0055 static void __iomem *csr_hc_index;
0056 static void __iomem *csr_hc_data;
0057 static void __iomem *csr_int_status;
0058 static void __iomem *csr_int_mask;
0059
0060
0061 static int zt5550_hc_config(struct pci_dev *pdev)
0062 {
0063     int ret;
0064
0065     /* Since we know that no boards exist with two HC chips, treat it as an error */
0066     if (hc_dev) {
0067         err("too many host controller devices?");
0068         return -EBUSY;
0069     }
0070
0071     ret = pci_enable_device(pdev);
0072     if (ret) {
0073         err("cannot enable %s\n", pci_name(pdev));
0074         return ret;
0075     }
0076
0077     hc_dev = pdev;
0078     dbg("hc_dev = %p", hc_dev);
0079     dbg("pci resource start %llx", (unsigned long long)pci_resource_start(hc_dev, 1));
0080     dbg("pci resource len %llx", (unsigned long long)pci_resource_len(hc_dev, 1));
0081
0082     if (!request_mem_region(pci_resource_start(hc_dev, 1),
0083                 pci_resource_len(hc_dev, 1), MY_NAME)) {
0084         err("cannot reserve MMIO region");
0085         ret = -ENOMEM;
0086         goto exit_disable_device;
0087     }
0088
0089     hc_registers =
0090         ioremap(pci_resource_start(hc_dev, 1), pci_resource_len(hc_dev, 1));
0091     if (!hc_registers) {
0092         err("cannot remap MMIO region %llx @ %llx",
0093             (unsigned long long)pci_resource_len(hc_dev, 1),
0094             (unsigned long long)pci_resource_start(hc_dev, 1));
0095         ret = -ENODEV;
0096         goto exit_release_region;
0097     }
0098
0099     csr_hc_index = hc_registers + CSR_HCINDEX;
0100     csr_hc_data = hc_registers + CSR_HCDATA;
0101     csr_int_status = hc_registers + CSR_INTSTAT;
0102     csr_int_mask = hc_registers + CSR_INTMASK;
0103
0104     /*
0105      * Disable host control, fault and serial interrupts
0106      */
0107     dbg("disabling host control, fault and serial interrupts");
0108     writeb((u8) HC_INT_MASK_REG, csr_hc_index);
0109     writeb((u8) ALL_INDEXED_INTS_MASK, csr_hc_data);
0110     dbg("disabled host control, fault and serial interrupts");
0111
0112     /*
0113      * Disable timer0, timer1 and ENUM interrupts
0114      */
0115     dbg("disabling timer0, timer1 and ENUM interrupts");
0116     writeb((u8) ALL_DIRECT_INTS_MASK, csr_int_mask);
0117     dbg("disabled timer0, timer1 and ENUM interrupts");
0118     return 0;
0119
0120 exit_release_region:
0121     release_mem_region(pci_resource_start(hc_dev, 1),
0122                pci_resource_len(hc_dev, 1));
0123 exit_disable_device:
0124     pci_disable_device(hc_dev);
0125     return ret;
0126 }
0127
0128 static int zt5550_hc_cleanup(void)
0129 {
0130     if (!hc_dev)
0131         return -ENODEV;
0132
0133     iounmap(hc_registers);
0134     release_mem_region(pci_resource_start(hc_dev, 1),
0135                pci_resource_len(hc_dev, 1));
0136     pci_disable_device(hc_dev);
0137     return 0;
0138 }
0139
0140 static int zt5550_hc_query_enum(void)
0141 {
0142     u8 value;
0143
0144     value = inb_p(ENUM_PORT);
0145     return ((value & ENUM_MASK) == ENUM_MASK);
0146 }
0147
0148 static int zt5550_hc_check_irq(void *dev_id)
0149 {
0150     int ret;
0151     u8 reg;
0152
0153     ret = 0;
0154     if (dev_id == zt5550_hpc.dev_id) {
0155         reg = readb(csr_int_status);
0156         if (reg)
0157             ret = 1;
0158     }
0159     return ret;
0160 }
0161
0162 static int zt5550_hc_enable_irq(void)
0163 {
0164     u8 reg;
0165
0166     if (hc_dev == NULL)
0167         return -ENODEV;
0168
0169     reg = readb(csr_int_mask);
0170     reg = reg & ~ENUM_INT_MASK;
0171     writeb(reg, csr_int_mask);
0172     return 0;
0173 }
0174
0175 static int zt5550_hc_disable_irq(void)
0176 {
0177     u8 reg;
0178
0179     if (hc_dev == NULL)
0180         return -ENODEV;
0181
0182     reg = readb(csr_int_mask);
0183     reg = reg | ENUM_INT_MASK;
0184     writeb(reg, csr_int_mask);
0185     return 0;
0186 }
0187
0188 static int zt5550_hc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0189 {
0190     int status;
0191
0192     status = zt5550_hc_config(pdev);
0193     if (status != 0)
0194         return status;
0195
0196     dbg("returned from zt5550_hc_config");
0197
0198     memset(&zt5550_hpc, 0, sizeof(struct cpci_hp_controller));
0199     zt5550_hpc_ops.query_enum = zt5550_hc_query_enum;
0200     zt5550_hpc.ops = &zt5550_hpc_ops;
0201     if (!poll) {
0202         zt5550_hpc.irq = hc_dev->irq;
0203         zt5550_hpc.irq_flags = IRQF_SHARED;
0204         zt5550_hpc.dev_id = hc_dev;
0205
0206         zt5550_hpc_ops.enable_irq = zt5550_hc_enable_irq;
0207         zt5550_hpc_ops.disable_irq = zt5550_hc_disable_irq;
0208         zt5550_hpc_ops.check_irq = zt5550_hc_check_irq;
0209     } else {
0210         info("using ENUM# polling mode");
0211     }
0212
0213     status = cpci_hp_register_controller(&zt5550_hpc);
0214     if (status != 0) {
0215         err("could not register cPCI hotplug controller");
0216         goto init_hc_error;
0217     }
0218     dbg("registered controller");
0219
0220     /* Look for first device matching cPCI bus's bridge vendor and device IDs */
0221     bus0_dev = pci_get_device(PCI_VENDOR_ID_DEC,
0222                   PCI_DEVICE_ID_DEC_21154, NULL);
0223     if (!bus0_dev) {
0224         status = -ENODEV;
0225         goto init_register_error;
0226     }
0227     bus0 = bus0_dev->subordinate;
0228     pci_dev_put(bus0_dev);
0229
0230     status = cpci_hp_register_bus(bus0, 0x0a, 0x0f);
0231     if (status != 0) {
0232         err("could not register cPCI hotplug bus");
0233         goto init_register_error;
0234     }
0235     dbg("registered bus");
0236
0237     status = cpci_hp_start();
0238     if (status != 0) {
0239         err("could not started cPCI hotplug system");
0240         cpci_hp_unregister_bus(bus0);
0241         goto init_register_error;
0242     }
0243     dbg("started cpci hp system");
0244
0245     return 0;
0246 init_register_error:
0247     cpci_hp_unregister_controller(&zt5550_hpc);
0248 init_hc_error:
0249     err("status = %d", status);
0250     zt5550_hc_cleanup();
0251     return status;
0252
0253 }
0254
0255 static void zt5550_hc_remove_one(struct pci_dev *pdev)
0256 {
0257     cpci_hp_stop();
0258     cpci_hp_unregister_bus(bus0);
0259     cpci_hp_unregister_controller(&zt5550_hpc);
0260     zt5550_hc_cleanup();
0261 }
0262
0263
0264 static const struct pci_device_id zt5550_hc_pci_tbl[] = {
0265     { PCI_VENDOR_ID_ZIATECH, PCI_DEVICE_ID_ZIATECH_5550_HC, PCI_ANY_ID, PCI_ANY_ID, },
0266     { 0, }
0267 };
0268 MODULE_DEVICE_TABLE(pci, zt5550_hc_pci_tbl);
0269
0270 static struct pci_driver zt5550_hc_driver = {
0271     .name       = "zt5550_hc",
0272     .id_table   = zt5550_hc_pci_tbl,
0273     .probe      = zt5550_hc_init_one,
0274     .remove     = zt5550_hc_remove_one,
0275 };
0276
0277 static int __init zt5550_init(void)
0278 {
0279     struct resource *r;
0280     int rc;
0281
0282     info(DRIVER_DESC " version: " DRIVER_VERSION);
0283     r = request_region(ENUM_PORT, 1, "#ENUM hotswap signal register");
0284     if (!r)
0285         return -EBUSY;
0286
0287     rc = pci_register_driver(&zt5550_hc_driver);
0288     if (rc < 0)
0289         release_region(ENUM_PORT, 1);
0290     return rc;
0291 }
0292
0293 static void __exit
0294 zt5550_exit(void)
0295 {
0296     pci_unregister_driver(&zt5550_hc_driver);
0297     release_region(ENUM_PORT, 1);
0298 }
0299
0300 module_init(zt5550_init);
0301 module_exit(zt5550_exit);
0302
0303 MODULE_AUTHOR(DRIVER_AUTHOR);
0304 MODULE_DESCRIPTION(DRIVER_DESC);
0305 MODULE_LICENSE("GPL");
0306 module_param(debug, bool, 0644);
0307 MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
0308 module_param(poll, bool, 0644);
0309 MODULE_PARM_DESC(poll, "#ENUM polling mode enabled or not");