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0039 #include <linux/delay.h>
0040 #include <linux/io.h>
0041 #include <linux/module.h>
0042 #include <linux/slab.h>
0043
0044 #include <linux/pci-epc.h>
0045 #include <linux/pci-epf.h>
0046 #include <linux/ntb.h>
0047
0048 static struct workqueue_struct *kpcintb_workqueue;
0049
0050 #define COMMAND_CONFIGURE_DOORBELL 1
0051 #define COMMAND_TEARDOWN_DOORBELL 2
0052 #define COMMAND_CONFIGURE_MW 3
0053 #define COMMAND_TEARDOWN_MW 4
0054 #define COMMAND_LINK_UP 5
0055 #define COMMAND_LINK_DOWN 6
0056
0057 #define COMMAND_STATUS_OK 1
0058 #define COMMAND_STATUS_ERROR 2
0059
0060 #define LINK_STATUS_UP BIT(0)
0061
0062 #define SPAD_COUNT 64
0063 #define DB_COUNT 4
0064 #define NTB_MW_OFFSET 2
0065 #define DB_COUNT_MASK GENMASK(15, 0)
0066 #define MSIX_ENABLE BIT(16)
0067 #define MAX_DB_COUNT 32
0068 #define MAX_MW 4
0069
0070 enum epf_ntb_bar {
0071 BAR_CONFIG,
0072 BAR_DB,
0073 BAR_MW0,
0074 BAR_MW1,
0075 BAR_MW2,
0076 };
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101 struct epf_ntb_ctrl {
0102 u32 command;
0103 u32 argument;
0104 u16 command_status;
0105 u16 link_status;
0106 u32 topology;
0107 u64 addr;
0108 u64 size;
0109 u32 num_mws;
0110 u32 reserved;
0111 u32 spad_offset;
0112 u32 spad_count;
0113 u32 db_entry_size;
0114 u32 db_data[MAX_DB_COUNT];
0115 u32 db_offset[MAX_DB_COUNT];
0116 } __packed;
0117
0118 struct epf_ntb {
0119 struct ntb_dev ntb;
0120 struct pci_epf *epf;
0121 struct config_group group;
0122
0123 u32 num_mws;
0124 u32 db_count;
0125 u32 spad_count;
0126 u64 mws_size[MAX_MW];
0127 u64 db;
0128 u32 vbus_number;
0129 u16 vntb_pid;
0130 u16 vntb_vid;
0131
0132 bool linkup;
0133 u32 spad_size;
0134
0135 enum pci_barno epf_ntb_bar[6];
0136
0137 struct epf_ntb_ctrl *reg;
0138
0139 phys_addr_t epf_db_phy;
0140 void __iomem *epf_db;
0141
0142 phys_addr_t vpci_mw_phy[MAX_MW];
0143 void __iomem *vpci_mw_addr[MAX_MW];
0144
0145 struct delayed_work cmd_handler;
0146 };
0147
0148 #define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group)
0149 #define ntb_ndev(__ntb) container_of(__ntb, struct epf_ntb, ntb)
0150
0151 static struct pci_epf_header epf_ntb_header = {
0152 .vendorid = PCI_ANY_ID,
0153 .deviceid = PCI_ANY_ID,
0154 .baseclass_code = PCI_BASE_CLASS_MEMORY,
0155 .interrupt_pin = PCI_INTERRUPT_INTA,
0156 };
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166 static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
0167 {
0168 if (link_up)
0169 ntb->reg->link_status |= LINK_STATUS_UP;
0170 else
0171 ntb->reg->link_status &= ~LINK_STATUS_UP;
0172
0173 ntb_link_event(&ntb->ntb);
0174 return 0;
0175 }
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199 static int epf_ntb_configure_mw(struct epf_ntb *ntb, u32 mw)
0200 {
0201 phys_addr_t phys_addr;
0202 u8 func_no, vfunc_no;
0203 u64 addr, size;
0204 int ret = 0;
0205
0206 phys_addr = ntb->vpci_mw_phy[mw];
0207 addr = ntb->reg->addr;
0208 size = ntb->reg->size;
0209
0210 func_no = ntb->epf->func_no;
0211 vfunc_no = ntb->epf->vfunc_no;
0212
0213 ret = pci_epc_map_addr(ntb->epf->epc, func_no, vfunc_no, phys_addr, addr, size);
0214 if (ret)
0215 dev_err(&ntb->epf->epc->dev,
0216 "Failed to map memory window %d address\n", mw);
0217 return ret;
0218 }
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228 static void epf_ntb_teardown_mw(struct epf_ntb *ntb, u32 mw)
0229 {
0230 pci_epc_unmap_addr(ntb->epf->epc,
0231 ntb->epf->func_no,
0232 ntb->epf->vfunc_no,
0233 ntb->vpci_mw_phy[mw]);
0234 }
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244
0245 static void epf_ntb_cmd_handler(struct work_struct *work)
0246 {
0247 struct epf_ntb_ctrl *ctrl;
0248 u32 command, argument;
0249 struct epf_ntb *ntb;
0250 struct device *dev;
0251 int ret;
0252 int i;
0253
0254 ntb = container_of(work, struct epf_ntb, cmd_handler.work);
0255
0256 for (i = 1; i < ntb->db_count; i++) {
0257 if (readl(ntb->epf_db + i * 4)) {
0258 if (readl(ntb->epf_db + i * 4))
0259 ntb->db |= 1 << (i - 1);
0260
0261 ntb_db_event(&ntb->ntb, i);
0262 writel(0, ntb->epf_db + i * 4);
0263 }
0264 }
0265
0266 ctrl = ntb->reg;
0267 command = ctrl->command;
0268 if (!command)
0269 goto reset_handler;
0270 argument = ctrl->argument;
0271
0272 ctrl->command = 0;
0273 ctrl->argument = 0;
0274
0275 ctrl = ntb->reg;
0276 dev = &ntb->epf->dev;
0277
0278 switch (command) {
0279 case COMMAND_CONFIGURE_DOORBELL:
0280 ctrl->command_status = COMMAND_STATUS_OK;
0281 break;
0282 case COMMAND_TEARDOWN_DOORBELL:
0283 ctrl->command_status = COMMAND_STATUS_OK;
0284 break;
0285 case COMMAND_CONFIGURE_MW:
0286 ret = epf_ntb_configure_mw(ntb, argument);
0287 if (ret < 0)
0288 ctrl->command_status = COMMAND_STATUS_ERROR;
0289 else
0290 ctrl->command_status = COMMAND_STATUS_OK;
0291 break;
0292 case COMMAND_TEARDOWN_MW:
0293 epf_ntb_teardown_mw(ntb, argument);
0294 ctrl->command_status = COMMAND_STATUS_OK;
0295 break;
0296 case COMMAND_LINK_UP:
0297 ntb->linkup = true;
0298 ret = epf_ntb_link_up(ntb, true);
0299 if (ret < 0)
0300 ctrl->command_status = COMMAND_STATUS_ERROR;
0301 else
0302 ctrl->command_status = COMMAND_STATUS_OK;
0303 goto reset_handler;
0304 case COMMAND_LINK_DOWN:
0305 ntb->linkup = false;
0306 ret = epf_ntb_link_up(ntb, false);
0307 if (ret < 0)
0308 ctrl->command_status = COMMAND_STATUS_ERROR;
0309 else
0310 ctrl->command_status = COMMAND_STATUS_OK;
0311 break;
0312 default:
0313 dev_err(dev, "UNKNOWN command: %d\n", command);
0314 break;
0315 }
0316
0317 reset_handler:
0318 queue_delayed_work(kpcintb_workqueue, &ntb->cmd_handler,
0319 msecs_to_jiffies(5));
0320 }
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335
0336
0337 static void epf_ntb_config_sspad_bar_clear(struct epf_ntb *ntb)
0338 {
0339 struct pci_epf_bar *epf_bar;
0340 enum pci_barno barno;
0341
0342 barno = ntb->epf_ntb_bar[BAR_CONFIG];
0343 epf_bar = &ntb->epf->bar[barno];
0344
0345 pci_epc_clear_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar);
0346 }
0347
0348
0349
0350
0351
0352
0353
0354
0355
0356
0357
0358 static int epf_ntb_config_sspad_bar_set(struct epf_ntb *ntb)
0359 {
0360 struct pci_epf_bar *epf_bar;
0361 enum pci_barno barno;
0362 u8 func_no, vfunc_no;
0363 struct device *dev;
0364 int ret;
0365
0366 dev = &ntb->epf->dev;
0367 func_no = ntb->epf->func_no;
0368 vfunc_no = ntb->epf->vfunc_no;
0369 barno = ntb->epf_ntb_bar[BAR_CONFIG];
0370 epf_bar = &ntb->epf->bar[barno];
0371
0372 ret = pci_epc_set_bar(ntb->epf->epc, func_no, vfunc_no, epf_bar);
0373 if (ret) {
0374 dev_err(dev, "inft: Config/Status/SPAD BAR set failed\n");
0375 return ret;
0376 }
0377 return 0;
0378 }
0379
0380
0381
0382
0383
0384
0385 static void epf_ntb_config_spad_bar_free(struct epf_ntb *ntb)
0386 {
0387 enum pci_barno barno;
0388
0389 barno = ntb->epf_ntb_bar[BAR_CONFIG];
0390 pci_epf_free_space(ntb->epf, ntb->reg, barno, 0);
0391 }
0392
0393
0394
0395
0396
0397
0398
0399
0400
0401
0402 static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb)
0403 {
0404 size_t align;
0405 enum pci_barno barno;
0406 struct epf_ntb_ctrl *ctrl;
0407 u32 spad_size, ctrl_size;
0408 u64 size;
0409 struct pci_epf *epf = ntb->epf;
0410 struct device *dev = &epf->dev;
0411 u32 spad_count;
0412 void *base;
0413 int i;
0414 const struct pci_epc_features *epc_features = pci_epc_get_features(epf->epc,
0415 epf->func_no,
0416 epf->vfunc_no);
0417 barno = ntb->epf_ntb_bar[BAR_CONFIG];
0418 size = epc_features->bar_fixed_size[barno];
0419 align = epc_features->align;
0420
0421 if ((!IS_ALIGNED(size, align)))
0422 return -EINVAL;
0423
0424 spad_count = ntb->spad_count;
0425
0426 ctrl_size = sizeof(struct epf_ntb_ctrl);
0427 spad_size = 2 * spad_count * 4;
0428
0429 if (!align) {
0430 ctrl_size = roundup_pow_of_two(ctrl_size);
0431 spad_size = roundup_pow_of_two(spad_size);
0432 } else {
0433 ctrl_size = ALIGN(ctrl_size, align);
0434 spad_size = ALIGN(spad_size, align);
0435 }
0436
0437 if (!size)
0438 size = ctrl_size + spad_size;
0439 else if (size < ctrl_size + spad_size)
0440 return -EINVAL;
0441
0442 base = pci_epf_alloc_space(epf, size, barno, align, 0);
0443 if (!base) {
0444 dev_err(dev, "Config/Status/SPAD alloc region fail\n");
0445 return -ENOMEM;
0446 }
0447
0448 ntb->reg = base;
0449
0450 ctrl = ntb->reg;
0451 ctrl->spad_offset = ctrl_size;
0452
0453 ctrl->spad_count = spad_count;
0454 ctrl->num_mws = ntb->num_mws;
0455 ntb->spad_size = spad_size;
0456
0457 ctrl->db_entry_size = 4;
0458
0459 for (i = 0; i < ntb->db_count; i++) {
0460 ntb->reg->db_data[i] = 1 + i;
0461 ntb->reg->db_offset[i] = 0;
0462 }
0463
0464 return 0;
0465 }
0466
0467
0468
0469
0470
0471
0472
0473
0474 static int epf_ntb_configure_interrupt(struct epf_ntb *ntb)
0475 {
0476 const struct pci_epc_features *epc_features;
0477 struct device *dev;
0478 u32 db_count;
0479 int ret;
0480
0481 dev = &ntb->epf->dev;
0482
0483 epc_features = pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no);
0484
0485 if (!(epc_features->msix_capable || epc_features->msi_capable)) {
0486 dev_err(dev, "MSI or MSI-X is required for doorbell\n");
0487 return -EINVAL;
0488 }
0489
0490 db_count = ntb->db_count;
0491 if (db_count > MAX_DB_COUNT) {
0492 dev_err(dev, "DB count cannot be more than %d\n", MAX_DB_COUNT);
0493 return -EINVAL;
0494 }
0495
0496 ntb->db_count = db_count;
0497
0498 if (epc_features->msi_capable) {
0499 ret = pci_epc_set_msi(ntb->epf->epc,
0500 ntb->epf->func_no,
0501 ntb->epf->vfunc_no,
0502 16);
0503 if (ret) {
0504 dev_err(dev, "MSI configuration failed\n");
0505 return ret;
0506 }
0507 }
0508
0509 return 0;
0510 }
0511
0512
0513
0514
0515
0516 static int epf_ntb_db_bar_init(struct epf_ntb *ntb)
0517 {
0518 const struct pci_epc_features *epc_features;
0519 u32 align;
0520 struct device *dev = &ntb->epf->dev;
0521 int ret;
0522 struct pci_epf_bar *epf_bar;
0523 void __iomem *mw_addr;
0524 enum pci_barno barno;
0525 size_t size = 4 * ntb->db_count;
0526
0527 epc_features = pci_epc_get_features(ntb->epf->epc,
0528 ntb->epf->func_no,
0529 ntb->epf->vfunc_no);
0530 align = epc_features->align;
0531
0532 if (size < 128)
0533 size = 128;
0534
0535 if (align)
0536 size = ALIGN(size, align);
0537 else
0538 size = roundup_pow_of_two(size);
0539
0540 barno = ntb->epf_ntb_bar[BAR_DB];
0541
0542 mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0);
0543 if (!mw_addr) {
0544 dev_err(dev, "Failed to allocate OB address\n");
0545 return -ENOMEM;
0546 }
0547
0548 ntb->epf_db = mw_addr;
0549
0550 epf_bar = &ntb->epf->bar[barno];
0551
0552 ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar);
0553 if (ret) {
0554 dev_err(dev, "Doorbell BAR set failed\n");
0555 goto err_alloc_peer_mem;
0556 }
0557 return ret;
0558
0559 err_alloc_peer_mem:
0560 pci_epc_mem_free_addr(ntb->epf->epc, epf_bar->phys_addr, mw_addr, epf_bar->size);
0561 return -1;
0562 }
0563
0564 static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws);
0565
0566
0567
0568
0569
0570
0571 static void epf_ntb_db_bar_clear(struct epf_ntb *ntb)
0572 {
0573 enum pci_barno barno;
0574
0575 barno = ntb->epf_ntb_bar[BAR_DB];
0576 pci_epf_free_space(ntb->epf, ntb->epf_db, barno, 0);
0577 pci_epc_clear_bar(ntb->epf->epc,
0578 ntb->epf->func_no,
0579 ntb->epf->vfunc_no,
0580 &ntb->epf->bar[barno]);
0581 }
0582
0583
0584
0585
0586
0587
0588 static int epf_ntb_mw_bar_init(struct epf_ntb *ntb)
0589 {
0590 int ret = 0;
0591 int i;
0592 u64 size;
0593 enum pci_barno barno;
0594 struct device *dev = &ntb->epf->dev;
0595
0596 for (i = 0; i < ntb->num_mws; i++) {
0597 size = ntb->mws_size[i];
0598 barno = ntb->epf_ntb_bar[BAR_MW0 + i];
0599
0600 ntb->epf->bar[barno].barno = barno;
0601 ntb->epf->bar[barno].size = size;
0602 ntb->epf->bar[barno].addr = NULL;
0603 ntb->epf->bar[barno].phys_addr = 0;
0604 ntb->epf->bar[barno].flags |= upper_32_bits(size) ?
0605 PCI_BASE_ADDRESS_MEM_TYPE_64 :
0606 PCI_BASE_ADDRESS_MEM_TYPE_32;
0607
0608 ret = pci_epc_set_bar(ntb->epf->epc,
0609 ntb->epf->func_no,
0610 ntb->epf->vfunc_no,
0611 &ntb->epf->bar[barno]);
0612 if (ret) {
0613 dev_err(dev, "MW set failed\n");
0614 goto err_alloc_mem;
0615 }
0616
0617
0618 ntb->vpci_mw_addr[i] = pci_epc_mem_alloc_addr(ntb->epf->epc,
0619 &ntb->vpci_mw_phy[i],
0620 size);
0621 if (!ntb->vpci_mw_addr[i]) {
0622 ret = -ENOMEM;
0623 dev_err(dev, "Failed to allocate source address\n");
0624 goto err_set_bar;
0625 }
0626 }
0627
0628 return ret;
0629
0630 err_set_bar:
0631 pci_epc_clear_bar(ntb->epf->epc,
0632 ntb->epf->func_no,
0633 ntb->epf->vfunc_no,
0634 &ntb->epf->bar[barno]);
0635 err_alloc_mem:
0636 epf_ntb_mw_bar_clear(ntb, i);
0637 return ret;
0638 }
0639
0640
0641
0642
0643
0644 static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws)
0645 {
0646 enum pci_barno barno;
0647 int i;
0648
0649 for (i = 0; i < num_mws; i++) {
0650 barno = ntb->epf_ntb_bar[BAR_MW0 + i];
0651 pci_epc_clear_bar(ntb->epf->epc,
0652 ntb->epf->func_no,
0653 ntb->epf->vfunc_no,
0654 &ntb->epf->bar[barno]);
0655
0656 pci_epc_mem_free_addr(ntb->epf->epc,
0657 ntb->vpci_mw_phy[i],
0658 ntb->vpci_mw_addr[i],
0659 ntb->mws_size[i]);
0660 }
0661 }
0662
0663
0664
0665
0666
0667
0668
0669 static void epf_ntb_epc_destroy(struct epf_ntb *ntb)
0670 {
0671 pci_epc_remove_epf(ntb->epf->epc, ntb->epf, 0);
0672 pci_epc_put(ntb->epf->epc);
0673 }
0674
0675
0676
0677
0678
0679
0680 static int epf_ntb_init_epc_bar(struct epf_ntb *ntb)
0681 {
0682 const struct pci_epc_features *epc_features;
0683 enum pci_barno barno;
0684 enum epf_ntb_bar bar;
0685 struct device *dev;
0686 u32 num_mws;
0687 int i;
0688
0689 barno = BAR_0;
0690 num_mws = ntb->num_mws;
0691 dev = &ntb->epf->dev;
0692 epc_features = pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no);
0693
0694
0695 for (bar = BAR_CONFIG; bar <= BAR_MW0; bar++, barno++) {
0696 barno = pci_epc_get_next_free_bar(epc_features, barno);
0697 if (barno < 0) {
0698 dev_err(dev, "Fail to get NTB function BAR\n");
0699 return barno;
0700 }
0701 ntb->epf_ntb_bar[bar] = barno;
0702 }
0703
0704
0705 for (bar = BAR_MW1, i = 1; i < num_mws; bar++, barno++, i++) {
0706 barno = pci_epc_get_next_free_bar(epc_features, barno);
0707 if (barno < 0) {
0708 ntb->num_mws = i;
0709 dev_dbg(dev, "BAR not available for > MW%d\n", i + 1);
0710 }
0711 ntb->epf_ntb_bar[bar] = barno;
0712 }
0713
0714 return 0;
0715 }
0716
0717
0718
0719
0720
0721
0722
0723
0724
0725 static int epf_ntb_epc_init(struct epf_ntb *ntb)
0726 {
0727 u8 func_no, vfunc_no;
0728 struct pci_epc *epc;
0729 struct pci_epf *epf;
0730 struct device *dev;
0731 int ret;
0732
0733 epf = ntb->epf;
0734 dev = &epf->dev;
0735 epc = epf->epc;
0736 func_no = ntb->epf->func_no;
0737 vfunc_no = ntb->epf->vfunc_no;
0738
0739 ret = epf_ntb_config_sspad_bar_set(ntb);
0740 if (ret) {
0741 dev_err(dev, "Config/self SPAD BAR init failed");
0742 return ret;
0743 }
0744
0745 ret = epf_ntb_configure_interrupt(ntb);
0746 if (ret) {
0747 dev_err(dev, "Interrupt configuration failed\n");
0748 goto err_config_interrupt;
0749 }
0750
0751 ret = epf_ntb_db_bar_init(ntb);
0752 if (ret) {
0753 dev_err(dev, "DB BAR init failed\n");
0754 goto err_db_bar_init;
0755 }
0756
0757 ret = epf_ntb_mw_bar_init(ntb);
0758 if (ret) {
0759 dev_err(dev, "MW BAR init failed\n");
0760 goto err_mw_bar_init;
0761 }
0762
0763 if (vfunc_no <= 1) {
0764 ret = pci_epc_write_header(epc, func_no, vfunc_no, epf->header);
0765 if (ret) {
0766 dev_err(dev, "Configuration header write failed\n");
0767 goto err_write_header;
0768 }
0769 }
0770
0771 INIT_DELAYED_WORK(&ntb->cmd_handler, epf_ntb_cmd_handler);
0772 queue_work(kpcintb_workqueue, &ntb->cmd_handler.work);
0773
0774 return 0;
0775
0776 err_write_header:
0777 epf_ntb_mw_bar_clear(ntb, ntb->num_mws);
0778 err_mw_bar_init:
0779 epf_ntb_db_bar_clear(ntb);
0780 err_db_bar_init:
0781 err_config_interrupt:
0782 epf_ntb_config_sspad_bar_clear(ntb);
0783
0784 return ret;
0785 }
0786
0787
0788
0789
0790
0791
0792
0793
0794 static void epf_ntb_epc_cleanup(struct epf_ntb *ntb)
0795 {
0796 epf_ntb_db_bar_clear(ntb);
0797 epf_ntb_mw_bar_clear(ntb, ntb->num_mws);
0798 }
0799
0800 #define EPF_NTB_R(_name) \
0801 static ssize_t epf_ntb_##_name##_show(struct config_item *item, \
0802 char *page) \
0803 { \
0804 struct config_group *group = to_config_group(item); \
0805 struct epf_ntb *ntb = to_epf_ntb(group); \
0806 \
0807 return sprintf(page, "%d\n", ntb->_name); \
0808 }
0809
0810 #define EPF_NTB_W(_name) \
0811 static ssize_t epf_ntb_##_name##_store(struct config_item *item, \
0812 const char *page, size_t len) \
0813 { \
0814 struct config_group *group = to_config_group(item); \
0815 struct epf_ntb *ntb = to_epf_ntb(group); \
0816 u32 val; \
0817 int ret; \
0818 \
0819 ret = kstrtou32(page, 0, &val); \
0820 if (ret) \
0821 return ret; \
0822 \
0823 ntb->_name = val; \
0824 \
0825 return len; \
0826 }
0827
0828 #define EPF_NTB_MW_R(_name) \
0829 static ssize_t epf_ntb_##_name##_show(struct config_item *item, \
0830 char *page) \
0831 { \
0832 struct config_group *group = to_config_group(item); \
0833 struct epf_ntb *ntb = to_epf_ntb(group); \
0834 struct device *dev = &ntb->epf->dev; \
0835 int win_no; \
0836 \
0837 if (sscanf(#_name, "mw%d", &win_no) != 1) \
0838 return -EINVAL; \
0839 \
0840 if (win_no <= 0 || win_no > ntb->num_mws) { \
0841 dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \
0842 return -EINVAL; \
0843 } \
0844 \
0845 return sprintf(page, "%lld\n", ntb->mws_size[win_no - 1]); \
0846 }
0847
0848 #define EPF_NTB_MW_W(_name) \
0849 static ssize_t epf_ntb_##_name##_store(struct config_item *item, \
0850 const char *page, size_t len) \
0851 { \
0852 struct config_group *group = to_config_group(item); \
0853 struct epf_ntb *ntb = to_epf_ntb(group); \
0854 struct device *dev = &ntb->epf->dev; \
0855 int win_no; \
0856 u64 val; \
0857 int ret; \
0858 \
0859 ret = kstrtou64(page, 0, &val); \
0860 if (ret) \
0861 return ret; \
0862 \
0863 if (sscanf(#_name, "mw%d", &win_no) != 1) \
0864 return -EINVAL; \
0865 \
0866 if (win_no <= 0 || win_no > ntb->num_mws) { \
0867 dev_err(dev, "Invalid num_nws: %d value\n", ntb->num_mws); \
0868 return -EINVAL; \
0869 } \
0870 \
0871 ntb->mws_size[win_no - 1] = val; \
0872 \
0873 return len; \
0874 }
0875
0876 static ssize_t epf_ntb_num_mws_store(struct config_item *item,
0877 const char *page, size_t len)
0878 {
0879 struct config_group *group = to_config_group(item);
0880 struct epf_ntb *ntb = to_epf_ntb(group);
0881 u32 val;
0882 int ret;
0883
0884 ret = kstrtou32(page, 0, &val);
0885 if (ret)
0886 return ret;
0887
0888 if (val > MAX_MW)
0889 return -EINVAL;
0890
0891 ntb->num_mws = val;
0892
0893 return len;
0894 }
0895
0896 EPF_NTB_R(spad_count)
0897 EPF_NTB_W(spad_count)
0898 EPF_NTB_R(db_count)
0899 EPF_NTB_W(db_count)
0900 EPF_NTB_R(num_mws)
0901 EPF_NTB_R(vbus_number)
0902 EPF_NTB_W(vbus_number)
0903 EPF_NTB_R(vntb_pid)
0904 EPF_NTB_W(vntb_pid)
0905 EPF_NTB_R(vntb_vid)
0906 EPF_NTB_W(vntb_vid)
0907 EPF_NTB_MW_R(mw1)
0908 EPF_NTB_MW_W(mw1)
0909 EPF_NTB_MW_R(mw2)
0910 EPF_NTB_MW_W(mw2)
0911 EPF_NTB_MW_R(mw3)
0912 EPF_NTB_MW_W(mw3)
0913 EPF_NTB_MW_R(mw4)
0914 EPF_NTB_MW_W(mw4)
0915
0916 CONFIGFS_ATTR(epf_ntb_, spad_count);
0917 CONFIGFS_ATTR(epf_ntb_, db_count);
0918 CONFIGFS_ATTR(epf_ntb_, num_mws);
0919 CONFIGFS_ATTR(epf_ntb_, mw1);
0920 CONFIGFS_ATTR(epf_ntb_, mw2);
0921 CONFIGFS_ATTR(epf_ntb_, mw3);
0922 CONFIGFS_ATTR(epf_ntb_, mw4);
0923 CONFIGFS_ATTR(epf_ntb_, vbus_number);
0924 CONFIGFS_ATTR(epf_ntb_, vntb_pid);
0925 CONFIGFS_ATTR(epf_ntb_, vntb_vid);
0926
0927 static struct configfs_attribute *epf_ntb_attrs[] = {
0928 &epf_ntb_attr_spad_count,
0929 &epf_ntb_attr_db_count,
0930 &epf_ntb_attr_num_mws,
0931 &epf_ntb_attr_mw1,
0932 &epf_ntb_attr_mw2,
0933 &epf_ntb_attr_mw3,
0934 &epf_ntb_attr_mw4,
0935 &epf_ntb_attr_vbus_number,
0936 &epf_ntb_attr_vntb_pid,
0937 &epf_ntb_attr_vntb_vid,
0938 NULL,
0939 };
0940
0941 static const struct config_item_type ntb_group_type = {
0942 .ct_attrs = epf_ntb_attrs,
0943 .ct_owner = THIS_MODULE,
0944 };
0945
0946
0947
0948
0949
0950
0951
0952
0953
0954
0955 static struct config_group *epf_ntb_add_cfs(struct pci_epf *epf,
0956 struct config_group *group)
0957 {
0958 struct epf_ntb *ntb = epf_get_drvdata(epf);
0959 struct config_group *ntb_group = &ntb->group;
0960 struct device *dev = &epf->dev;
0961
0962 config_group_init_type_name(ntb_group, dev_name(dev), &ntb_group_type);
0963
0964 return ntb_group;
0965 }
0966
0967
0968
0969 static u32 pci_space[] = {
0970 0xffffffff,
0971 0,
0972 0xffffffff,
0973 0x40,
0974 0,
0975 0,
0976 0,
0977 0,
0978 0,
0979 0,
0980 0,
0981 0,
0982 0,
0983 0,
0984 0,
0985 0,
0986 };
0987
0988 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
0989 {
0990 if (devfn == 0) {
0991 memcpy(val, ((u8 *)pci_space) + where, size);
0992 return PCIBIOS_SUCCESSFUL;
0993 }
0994 return PCIBIOS_DEVICE_NOT_FOUND;
0995 }
0996
0997 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
0998 {
0999 return 0;
1000 }
1001
1002 static struct pci_ops vpci_ops = {
1003 .read = pci_read,
1004 .write = pci_write,
1005 };
1006
1007 static int vpci_scan_bus(void *sysdata)
1008 {
1009 struct pci_bus *vpci_bus;
1010 struct epf_ntb *ndev = sysdata;
1011
1012 vpci_bus = pci_scan_bus(ndev->vbus_number, &vpci_ops, sysdata);
1013 if (vpci_bus)
1014 pr_err("create pci bus\n");
1015
1016 pci_bus_add_devices(vpci_bus);
1017
1018 return 0;
1019 }
1020
1021
1022
1023 static int vntb_epf_mw_count(struct ntb_dev *ntb, int pidx)
1024 {
1025 struct epf_ntb *ndev = ntb_ndev(ntb);
1026
1027 return ndev->num_mws;
1028 }
1029
1030 static int vntb_epf_spad_count(struct ntb_dev *ntb)
1031 {
1032 return ntb_ndev(ntb)->spad_count;
1033 }
1034
1035 static int vntb_epf_peer_mw_count(struct ntb_dev *ntb)
1036 {
1037 return ntb_ndev(ntb)->num_mws;
1038 }
1039
1040 static u64 vntb_epf_db_valid_mask(struct ntb_dev *ntb)
1041 {
1042 return BIT_ULL(ntb_ndev(ntb)->db_count) - 1;
1043 }
1044
1045 static int vntb_epf_db_set_mask(struct ntb_dev *ntb, u64 db_bits)
1046 {
1047 return 0;
1048 }
1049
1050 static int vntb_epf_mw_set_trans(struct ntb_dev *ndev, int pidx, int idx,
1051 dma_addr_t addr, resource_size_t size)
1052 {
1053 struct epf_ntb *ntb = ntb_ndev(ndev);
1054 struct pci_epf_bar *epf_bar;
1055 enum pci_barno barno;
1056 int ret;
1057 struct device *dev;
1058
1059 dev = &ntb->ntb.dev;
1060 barno = ntb->epf_ntb_bar[BAR_MW0 + idx];
1061 epf_bar = &ntb->epf->bar[barno];
1062 epf_bar->phys_addr = addr;
1063 epf_bar->barno = barno;
1064 epf_bar->size = size;
1065
1066 ret = pci_epc_set_bar(ntb->epf->epc, 0, 0, epf_bar);
1067 if (ret) {
1068 dev_err(dev, "failure set mw trans\n");
1069 return ret;
1070 }
1071 return 0;
1072 }
1073
1074 static int vntb_epf_mw_clear_trans(struct ntb_dev *ntb, int pidx, int idx)
1075 {
1076 return 0;
1077 }
1078
1079 static int vntb_epf_peer_mw_get_addr(struct ntb_dev *ndev, int idx,
1080 phys_addr_t *base, resource_size_t *size)
1081 {
1082
1083 struct epf_ntb *ntb = ntb_ndev(ndev);
1084
1085 if (base)
1086 *base = ntb->vpci_mw_phy[idx];
1087
1088 if (size)
1089 *size = ntb->mws_size[idx];
1090
1091 return 0;
1092 }
1093
1094 static int vntb_epf_link_enable(struct ntb_dev *ntb,
1095 enum ntb_speed max_speed,
1096 enum ntb_width max_width)
1097 {
1098 return 0;
1099 }
1100
1101 static u32 vntb_epf_spad_read(struct ntb_dev *ndev, int idx)
1102 {
1103 struct epf_ntb *ntb = ntb_ndev(ndev);
1104 int off = ntb->reg->spad_offset, ct = ntb->reg->spad_count * 4;
1105 u32 val;
1106 void __iomem *base = ntb->reg;
1107
1108 val = readl(base + off + ct + idx * 4);
1109 return val;
1110 }
1111
1112 static int vntb_epf_spad_write(struct ntb_dev *ndev, int idx, u32 val)
1113 {
1114 struct epf_ntb *ntb = ntb_ndev(ndev);
1115 struct epf_ntb_ctrl *ctrl = ntb->reg;
1116 int off = ctrl->spad_offset, ct = ctrl->spad_count * 4;
1117 void __iomem *base = ntb->reg;
1118
1119 writel(val, base + off + ct + idx * 4);
1120 return 0;
1121 }
1122
1123 static u32 vntb_epf_peer_spad_read(struct ntb_dev *ndev, int pidx, int idx)
1124 {
1125 struct epf_ntb *ntb = ntb_ndev(ndev);
1126 struct epf_ntb_ctrl *ctrl = ntb->reg;
1127 int off = ctrl->spad_offset;
1128 void __iomem *base = ntb->reg;
1129 u32 val;
1130
1131 val = readl(base + off + idx * 4);
1132 return val;
1133 }
1134
1135 static int vntb_epf_peer_spad_write(struct ntb_dev *ndev, int pidx, int idx, u32 val)
1136 {
1137 struct epf_ntb *ntb = ntb_ndev(ndev);
1138 struct epf_ntb_ctrl *ctrl = ntb->reg;
1139 int off = ctrl->spad_offset;
1140 void __iomem *base = ntb->reg;
1141
1142 writel(val, base + off + idx * 4);
1143 return 0;
1144 }
1145
1146 static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits)
1147 {
1148 u32 interrupt_num = ffs(db_bits) + 1;
1149 struct epf_ntb *ntb = ntb_ndev(ndev);
1150 u8 func_no, vfunc_no;
1151 int ret;
1152
1153 func_no = ntb->epf->func_no;
1154 vfunc_no = ntb->epf->vfunc_no;
1155
1156 ret = pci_epc_raise_irq(ntb->epf->epc,
1157 func_no,
1158 vfunc_no,
1159 PCI_EPC_IRQ_MSI,
1160 interrupt_num + 1);
1161 if (ret)
1162 dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n");
1163
1164 return ret;
1165 }
1166
1167 static u64 vntb_epf_db_read(struct ntb_dev *ndev)
1168 {
1169 struct epf_ntb *ntb = ntb_ndev(ndev);
1170
1171 return ntb->db;
1172 }
1173
1174 static int vntb_epf_mw_get_align(struct ntb_dev *ndev, int pidx, int idx,
1175 resource_size_t *addr_align,
1176 resource_size_t *size_align,
1177 resource_size_t *size_max)
1178 {
1179 struct epf_ntb *ntb = ntb_ndev(ndev);
1180
1181 if (addr_align)
1182 *addr_align = SZ_4K;
1183
1184 if (size_align)
1185 *size_align = 1;
1186
1187 if (size_max)
1188 *size_max = ntb->mws_size[idx];
1189
1190 return 0;
1191 }
1192
1193 static u64 vntb_epf_link_is_up(struct ntb_dev *ndev,
1194 enum ntb_speed *speed,
1195 enum ntb_width *width)
1196 {
1197 struct epf_ntb *ntb = ntb_ndev(ndev);
1198
1199 return ntb->reg->link_status;
1200 }
1201
1202 static int vntb_epf_db_clear_mask(struct ntb_dev *ndev, u64 db_bits)
1203 {
1204 return 0;
1205 }
1206
1207 static int vntb_epf_db_clear(struct ntb_dev *ndev, u64 db_bits)
1208 {
1209 struct epf_ntb *ntb = ntb_ndev(ndev);
1210
1211 ntb->db &= ~db_bits;
1212 return 0;
1213 }
1214
1215 static int vntb_epf_link_disable(struct ntb_dev *ntb)
1216 {
1217 return 0;
1218 }
1219
1220 static const struct ntb_dev_ops vntb_epf_ops = {
1221 .mw_count = vntb_epf_mw_count,
1222 .spad_count = vntb_epf_spad_count,
1223 .peer_mw_count = vntb_epf_peer_mw_count,
1224 .db_valid_mask = vntb_epf_db_valid_mask,
1225 .db_set_mask = vntb_epf_db_set_mask,
1226 .mw_set_trans = vntb_epf_mw_set_trans,
1227 .mw_clear_trans = vntb_epf_mw_clear_trans,
1228 .peer_mw_get_addr = vntb_epf_peer_mw_get_addr,
1229 .link_enable = vntb_epf_link_enable,
1230 .spad_read = vntb_epf_spad_read,
1231 .spad_write = vntb_epf_spad_write,
1232 .peer_spad_read = vntb_epf_peer_spad_read,
1233 .peer_spad_write = vntb_epf_peer_spad_write,
1234 .peer_db_set = vntb_epf_peer_db_set,
1235 .db_read = vntb_epf_db_read,
1236 .mw_get_align = vntb_epf_mw_get_align,
1237 .link_is_up = vntb_epf_link_is_up,
1238 .db_clear_mask = vntb_epf_db_clear_mask,
1239 .db_clear = vntb_epf_db_clear,
1240 .link_disable = vntb_epf_link_disable,
1241 };
1242
1243 static int pci_vntb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1244 {
1245 int ret;
1246 struct epf_ntb *ndev = (struct epf_ntb *)pdev->sysdata;
1247 struct device *dev = &pdev->dev;
1248
1249 ndev->ntb.pdev = pdev;
1250 ndev->ntb.topo = NTB_TOPO_NONE;
1251 ndev->ntb.ops = &vntb_epf_ops;
1252
1253 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
1254 if (ret) {
1255 dev_err(dev, "Cannot set DMA mask\n");
1256 return -EINVAL;
1257 }
1258
1259 ret = ntb_register_device(&ndev->ntb);
1260 if (ret) {
1261 dev_err(dev, "Failed to register NTB device\n");
1262 goto err_register_dev;
1263 }
1264
1265 dev_dbg(dev, "PCI Virtual NTB driver loaded\n");
1266 return 0;
1267
1268 err_register_dev:
1269 return -EINVAL;
1270 }
1271
1272 static struct pci_device_id pci_vntb_table[] = {
1273 {
1274 PCI_DEVICE(0xffff, 0xffff),
1275 },
1276 {},
1277 };
1278
1279 static struct pci_driver vntb_pci_driver = {
1280 .name = "pci-vntb",
1281 .id_table = pci_vntb_table,
1282 .probe = pci_vntb_probe,
1283 };
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296 static int epf_ntb_bind(struct pci_epf *epf)
1297 {
1298 struct epf_ntb *ntb = epf_get_drvdata(epf);
1299 struct device *dev = &epf->dev;
1300 int ret;
1301
1302 if (!epf->epc) {
1303 dev_dbg(dev, "PRIMARY EPC interface not yet bound\n");
1304 return 0;
1305 }
1306
1307 ret = epf_ntb_init_epc_bar(ntb);
1308 if (ret) {
1309 dev_err(dev, "Failed to create NTB EPC\n");
1310 goto err_bar_init;
1311 }
1312
1313 ret = epf_ntb_config_spad_bar_alloc(ntb);
1314 if (ret) {
1315 dev_err(dev, "Failed to allocate BAR memory\n");
1316 goto err_bar_alloc;
1317 }
1318
1319 ret = epf_ntb_epc_init(ntb);
1320 if (ret) {
1321 dev_err(dev, "Failed to initialize EPC\n");
1322 goto err_bar_alloc;
1323 }
1324
1325 epf_set_drvdata(epf, ntb);
1326
1327 pci_space[0] = (ntb->vntb_pid << 16) | ntb->vntb_vid;
1328 pci_vntb_table[0].vendor = ntb->vntb_vid;
1329 pci_vntb_table[0].device = ntb->vntb_pid;
1330
1331 ret = pci_register_driver(&vntb_pci_driver);
1332 if (ret) {
1333 dev_err(dev, "failure register vntb pci driver\n");
1334 goto err_bar_alloc;
1335 }
1336
1337 vpci_scan_bus(ntb);
1338
1339 return 0;
1340
1341 err_bar_alloc:
1342 epf_ntb_config_spad_bar_free(ntb);
1343
1344 err_bar_init:
1345 epf_ntb_epc_destroy(ntb);
1346
1347 return ret;
1348 }
1349
1350
1351
1352
1353
1354
1355
1356 static void epf_ntb_unbind(struct pci_epf *epf)
1357 {
1358 struct epf_ntb *ntb = epf_get_drvdata(epf);
1359
1360 epf_ntb_epc_cleanup(ntb);
1361 epf_ntb_config_spad_bar_free(ntb);
1362 epf_ntb_epc_destroy(ntb);
1363
1364 pci_unregister_driver(&vntb_pci_driver);
1365 }
1366
1367
1368 static struct pci_epf_ops epf_ntb_ops = {
1369 .bind = epf_ntb_bind,
1370 .unbind = epf_ntb_unbind,
1371 .add_cfs = epf_ntb_add_cfs,
1372 };
1373
1374
1375
1376
1377
1378
1379
1380
1381 static int epf_ntb_probe(struct pci_epf *epf)
1382 {
1383 struct epf_ntb *ntb;
1384 struct device *dev;
1385
1386 dev = &epf->dev;
1387
1388 ntb = devm_kzalloc(dev, sizeof(*ntb), GFP_KERNEL);
1389 if (!ntb)
1390 return -ENOMEM;
1391
1392 epf->header = &epf_ntb_header;
1393 ntb->epf = epf;
1394 ntb->vbus_number = 0xff;
1395 epf_set_drvdata(epf, ntb);
1396
1397 dev_info(dev, "pci-ep epf driver loaded\n");
1398 return 0;
1399 }
1400
1401 static const struct pci_epf_device_id epf_ntb_ids[] = {
1402 {
1403 .name = "pci_epf_vntb",
1404 },
1405 {},
1406 };
1407
1408 static struct pci_epf_driver epf_ntb_driver = {
1409 .driver.name = "pci_epf_vntb",
1410 .probe = epf_ntb_probe,
1411 .id_table = epf_ntb_ids,
1412 .ops = &epf_ntb_ops,
1413 .owner = THIS_MODULE,
1414 };
1415
1416 static int __init epf_ntb_init(void)
1417 {
1418 int ret;
1419
1420 kpcintb_workqueue = alloc_workqueue("kpcintb", WQ_MEM_RECLAIM |
1421 WQ_HIGHPRI, 0);
1422 ret = pci_epf_register_driver(&epf_ntb_driver);
1423 if (ret) {
1424 destroy_workqueue(kpcintb_workqueue);
1425 pr_err("Failed to register pci epf ntb driver --> %d\n", ret);
1426 return ret;
1427 }
1428
1429 return 0;
1430 }
1431 module_init(epf_ntb_init);
1432
1433 static void __exit epf_ntb_exit(void)
1434 {
1435 pci_epf_unregister_driver(&epf_ntb_driver);
1436 destroy_workqueue(kpcintb_workqueue);
1437 }
1438 module_exit(epf_ntb_exit);
1439
1440 MODULE_DESCRIPTION("PCI EPF NTB DRIVER");
1441 MODULE_AUTHOR("Frank Li <Frank.li@nxp.com>");
1442 MODULE_LICENSE("GPL v2");