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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2016 Broadcom
0004  */
0005 
0006 #include <linux/device.h>
0007 #include <linux/io.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/pci.h>
0011 #include <linux/pci-ecam.h>
0012 #include <linux/slab.h>
0013 
0014 /*
0015  * On 64-bit systems, we do a single ioremap for the whole config space
0016  * since we have enough virtual address range available.  On 32-bit, we
0017  * ioremap the config space for each bus individually.
0018  */
0019 static const bool per_bus_mapping = !IS_ENABLED(CONFIG_64BIT);
0020 
0021 /*
0022  * Create a PCI config space window
0023  *  - reserve mem region
0024  *  - alloc struct pci_config_window with space for all mappings
0025  *  - ioremap the config space
0026  */
0027 struct pci_config_window *pci_ecam_create(struct device *dev,
0028         struct resource *cfgres, struct resource *busr,
0029         const struct pci_ecam_ops *ops)
0030 {
0031     unsigned int bus_shift = ops->bus_shift;
0032     struct pci_config_window *cfg;
0033     unsigned int bus_range, bus_range_max, bsz;
0034     struct resource *conflict;
0035     int err;
0036 
0037     if (busr->start > busr->end)
0038         return ERR_PTR(-EINVAL);
0039 
0040     cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
0041     if (!cfg)
0042         return ERR_PTR(-ENOMEM);
0043 
0044     /* ECAM-compliant platforms need not supply ops->bus_shift */
0045     if (!bus_shift)
0046         bus_shift = PCIE_ECAM_BUS_SHIFT;
0047 
0048     cfg->parent = dev;
0049     cfg->ops = ops;
0050     cfg->busr.start = busr->start;
0051     cfg->busr.end = busr->end;
0052     cfg->busr.flags = IORESOURCE_BUS;
0053     cfg->bus_shift = bus_shift;
0054     bus_range = resource_size(&cfg->busr);
0055     bus_range_max = resource_size(cfgres) >> bus_shift;
0056     if (bus_range > bus_range_max) {
0057         bus_range = bus_range_max;
0058         cfg->busr.end = busr->start + bus_range - 1;
0059         dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
0060              cfgres, &cfg->busr, busr);
0061     }
0062     bsz = 1 << bus_shift;
0063 
0064     cfg->res.start = cfgres->start;
0065     cfg->res.end = cfgres->end;
0066     cfg->res.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
0067     cfg->res.name = "PCI ECAM";
0068 
0069     conflict = request_resource_conflict(&iomem_resource, &cfg->res);
0070     if (conflict) {
0071         err = -EBUSY;
0072         dev_err(dev, "can't claim ECAM area %pR: address conflict with %s %pR\n",
0073             &cfg->res, conflict->name, conflict);
0074         goto err_exit;
0075     }
0076 
0077     if (per_bus_mapping) {
0078         cfg->winp = kcalloc(bus_range, sizeof(*cfg->winp), GFP_KERNEL);
0079         if (!cfg->winp)
0080             goto err_exit_malloc;
0081     } else {
0082         cfg->win = pci_remap_cfgspace(cfgres->start, bus_range * bsz);
0083         if (!cfg->win)
0084             goto err_exit_iomap;
0085     }
0086 
0087     if (ops->init) {
0088         err = ops->init(cfg);
0089         if (err)
0090             goto err_exit;
0091     }
0092     dev_info(dev, "ECAM at %pR for %pR\n", &cfg->res, &cfg->busr);
0093     return cfg;
0094 
0095 err_exit_iomap:
0096     dev_err(dev, "ECAM ioremap failed\n");
0097 err_exit_malloc:
0098     err = -ENOMEM;
0099 err_exit:
0100     pci_ecam_free(cfg);
0101     return ERR_PTR(err);
0102 }
0103 EXPORT_SYMBOL_GPL(pci_ecam_create);
0104 
0105 void pci_ecam_free(struct pci_config_window *cfg)
0106 {
0107     int i;
0108 
0109     if (per_bus_mapping) {
0110         if (cfg->winp) {
0111             for (i = 0; i < resource_size(&cfg->busr); i++)
0112                 if (cfg->winp[i])
0113                     iounmap(cfg->winp[i]);
0114             kfree(cfg->winp);
0115         }
0116     } else {
0117         if (cfg->win)
0118             iounmap(cfg->win);
0119     }
0120     if (cfg->res.parent)
0121         release_resource(&cfg->res);
0122     kfree(cfg);
0123 }
0124 EXPORT_SYMBOL_GPL(pci_ecam_free);
0125 
0126 static int pci_ecam_add_bus(struct pci_bus *bus)
0127 {
0128     struct pci_config_window *cfg = bus->sysdata;
0129     unsigned int bsz = 1 << cfg->bus_shift;
0130     unsigned int busn = bus->number;
0131     phys_addr_t start;
0132 
0133     if (!per_bus_mapping)
0134         return 0;
0135 
0136     if (busn < cfg->busr.start || busn > cfg->busr.end)
0137         return -EINVAL;
0138 
0139     busn -= cfg->busr.start;
0140     start = cfg->res.start + busn * bsz;
0141 
0142     cfg->winp[busn] = pci_remap_cfgspace(start, bsz);
0143     if (!cfg->winp[busn])
0144         return -ENOMEM;
0145 
0146     return 0;
0147 }
0148 
0149 static void pci_ecam_remove_bus(struct pci_bus *bus)
0150 {
0151     struct pci_config_window *cfg = bus->sysdata;
0152     unsigned int busn = bus->number;
0153 
0154     if (!per_bus_mapping || busn < cfg->busr.start || busn > cfg->busr.end)
0155         return;
0156 
0157     busn -= cfg->busr.start;
0158     if (cfg->winp[busn]) {
0159         iounmap(cfg->winp[busn]);
0160         cfg->winp[busn] = NULL;
0161     }
0162 }
0163 
0164 /*
0165  * Function to implement the pci_ops ->map_bus method
0166  */
0167 void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
0168                    int where)
0169 {
0170     struct pci_config_window *cfg = bus->sysdata;
0171     unsigned int bus_shift = cfg->ops->bus_shift;
0172     unsigned int devfn_shift = cfg->ops->bus_shift - 8;
0173     unsigned int busn = bus->number;
0174     void __iomem *base;
0175     u32 bus_offset, devfn_offset;
0176 
0177     if (busn < cfg->busr.start || busn > cfg->busr.end)
0178         return NULL;
0179 
0180     busn -= cfg->busr.start;
0181     if (per_bus_mapping) {
0182         base = cfg->winp[busn];
0183         busn = 0;
0184     } else
0185         base = cfg->win;
0186 
0187     if (cfg->ops->bus_shift) {
0188         bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift;
0189         devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift;
0190         where &= PCIE_ECAM_REG_MASK;
0191 
0192         return base + (bus_offset | devfn_offset | where);
0193     }
0194 
0195     return base + PCIE_ECAM_OFFSET(busn, devfn, where);
0196 }
0197 EXPORT_SYMBOL_GPL(pci_ecam_map_bus);
0198 
0199 /* ECAM ops */
0200 const struct pci_ecam_ops pci_generic_ecam_ops = {
0201     .pci_ops    = {
0202         .add_bus    = pci_ecam_add_bus,
0203         .remove_bus = pci_ecam_remove_bus,
0204         .map_bus    = pci_ecam_map_bus,
0205         .read       = pci_generic_config_read,
0206         .write      = pci_generic_config_write,
0207     }
0208 };
0209 EXPORT_SYMBOL_GPL(pci_generic_ecam_ops);
0210 
0211 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
0212 /* ECAM ops for 32-bit access only (non-compliant) */
0213 const struct pci_ecam_ops pci_32b_ops = {
0214     .pci_ops    = {
0215         .add_bus    = pci_ecam_add_bus,
0216         .remove_bus = pci_ecam_remove_bus,
0217         .map_bus    = pci_ecam_map_bus,
0218         .read       = pci_generic_config_read32,
0219         .write      = pci_generic_config_write32,
0220     }
0221 };
0222 
0223 /* ECAM ops for 32-bit read only (non-compliant) */
0224 const struct pci_ecam_ops pci_32b_read_ops = {
0225     .pci_ops    = {
0226         .add_bus    = pci_ecam_add_bus,
0227         .remove_bus = pci_ecam_remove_bus,
0228         .map_bus    = pci_ecam_map_bus,
0229         .read       = pci_generic_config_read32,
0230         .write      = pci_generic_config_write,
0231     }
0232 };
0233 #endif
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