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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Rockchip AXI PCIe host controller driver
0004  *
0005  * Copyright (c) 2016 Rockchip, Inc.
0006  *
0007  * Author: Shawn Lin <shawn.lin@rock-chips.com>
0008  *         Wenrui Li <wenrui.li@rock-chips.com>
0009  *
0010  * Bits taken from Synopsys DesignWare Host controller driver and
0011  * ARM PCI Host generic driver.
0012  */
0013 
0014 #include <linux/bitrev.h>
0015 #include <linux/clk.h>
0016 #include <linux/delay.h>
0017 #include <linux/gpio/consumer.h>
0018 #include <linux/init.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/iopoll.h>
0021 #include <linux/irq.h>
0022 #include <linux/irqchip/chained_irq.h>
0023 #include <linux/irqdomain.h>
0024 #include <linux/kernel.h>
0025 #include <linux/mfd/syscon.h>
0026 #include <linux/module.h>
0027 #include <linux/of_address.h>
0028 #include <linux/of_device.h>
0029 #include <linux/of_pci.h>
0030 #include <linux/of_platform.h>
0031 #include <linux/of_irq.h>
0032 #include <linux/pci.h>
0033 #include <linux/pci_ids.h>
0034 #include <linux/phy/phy.h>
0035 #include <linux/platform_device.h>
0036 #include <linux/reset.h>
0037 #include <linux/regmap.h>
0038 
0039 #include "../pci.h"
0040 #include "pcie-rockchip.h"
0041 
0042 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
0043 {
0044     u32 status;
0045 
0046     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
0047     status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
0048     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
0049 }
0050 
0051 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
0052 {
0053     u32 status;
0054 
0055     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
0056     status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
0057     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
0058 }
0059 
0060 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
0061 {
0062     u32 val;
0063 
0064     /* Update Tx credit maximum update interval */
0065     val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
0066     val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
0067     val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000);   /* ns */
0068     rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
0069 }
0070 
0071 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
0072                       struct pci_bus *bus, int dev)
0073 {
0074     /*
0075      * Access only one slot on each root port.
0076      * Do not read more than one device on the bus directly attached
0077      * to RC's downstream side.
0078      */
0079     if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent))
0080         return dev == 0;
0081 
0082     return 1;
0083 }
0084 
0085 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
0086 {
0087     u32 val;
0088     u8 map;
0089 
0090     if (rockchip->legacy_phy)
0091         return GENMASK(MAX_LANE_NUM - 1, 0);
0092 
0093     val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
0094     map = val & PCIE_CORE_LANE_MAP_MASK;
0095 
0096     /* The link may be using a reverse-indexed mapping. */
0097     if (val & PCIE_CORE_LANE_MAP_REVERSE)
0098         map = bitrev8(map) >> 4;
0099 
0100     return map;
0101 }
0102 
0103 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
0104                      int where, int size, u32 *val)
0105 {
0106     void __iomem *addr;
0107 
0108     addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
0109 
0110     if (!IS_ALIGNED((uintptr_t)addr, size)) {
0111         *val = 0;
0112         return PCIBIOS_BAD_REGISTER_NUMBER;
0113     }
0114 
0115     if (size == 4) {
0116         *val = readl(addr);
0117     } else if (size == 2) {
0118         *val = readw(addr);
0119     } else if (size == 1) {
0120         *val = readb(addr);
0121     } else {
0122         *val = 0;
0123         return PCIBIOS_BAD_REGISTER_NUMBER;
0124     }
0125     return PCIBIOS_SUCCESSFUL;
0126 }
0127 
0128 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
0129                      int where, int size, u32 val)
0130 {
0131     u32 mask, tmp, offset;
0132     void __iomem *addr;
0133 
0134     offset = where & ~0x3;
0135     addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
0136 
0137     if (size == 4) {
0138         writel(val, addr);
0139         return PCIBIOS_SUCCESSFUL;
0140     }
0141 
0142     mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
0143 
0144     /*
0145      * N.B. This read/modify/write isn't safe in general because it can
0146      * corrupt RW1C bits in adjacent registers.  But the hardware
0147      * doesn't support smaller writes.
0148      */
0149     tmp = readl(addr) & mask;
0150     tmp |= val << ((where & 0x3) * 8);
0151     writel(tmp, addr);
0152 
0153     return PCIBIOS_SUCCESSFUL;
0154 }
0155 
0156 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
0157                        struct pci_bus *bus, u32 devfn,
0158                        int where, int size, u32 *val)
0159 {
0160     void __iomem *addr;
0161 
0162     addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
0163 
0164     if (!IS_ALIGNED((uintptr_t)addr, size)) {
0165         *val = 0;
0166         return PCIBIOS_BAD_REGISTER_NUMBER;
0167     }
0168 
0169     if (pci_is_root_bus(bus->parent))
0170         rockchip_pcie_cfg_configuration_accesses(rockchip,
0171                         AXI_WRAPPER_TYPE0_CFG);
0172     else
0173         rockchip_pcie_cfg_configuration_accesses(rockchip,
0174                         AXI_WRAPPER_TYPE1_CFG);
0175 
0176     if (size == 4) {
0177         *val = readl(addr);
0178     } else if (size == 2) {
0179         *val = readw(addr);
0180     } else if (size == 1) {
0181         *val = readb(addr);
0182     } else {
0183         *val = 0;
0184         return PCIBIOS_BAD_REGISTER_NUMBER;
0185     }
0186     return PCIBIOS_SUCCESSFUL;
0187 }
0188 
0189 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
0190                        struct pci_bus *bus, u32 devfn,
0191                        int where, int size, u32 val)
0192 {
0193     void __iomem *addr;
0194 
0195     addr = rockchip->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
0196 
0197     if (!IS_ALIGNED((uintptr_t)addr, size))
0198         return PCIBIOS_BAD_REGISTER_NUMBER;
0199 
0200     if (pci_is_root_bus(bus->parent))
0201         rockchip_pcie_cfg_configuration_accesses(rockchip,
0202                         AXI_WRAPPER_TYPE0_CFG);
0203     else
0204         rockchip_pcie_cfg_configuration_accesses(rockchip,
0205                         AXI_WRAPPER_TYPE1_CFG);
0206 
0207     if (size == 4)
0208         writel(val, addr);
0209     else if (size == 2)
0210         writew(val, addr);
0211     else if (size == 1)
0212         writeb(val, addr);
0213     else
0214         return PCIBIOS_BAD_REGISTER_NUMBER;
0215 
0216     return PCIBIOS_SUCCESSFUL;
0217 }
0218 
0219 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
0220                  int size, u32 *val)
0221 {
0222     struct rockchip_pcie *rockchip = bus->sysdata;
0223 
0224     if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
0225         return PCIBIOS_DEVICE_NOT_FOUND;
0226 
0227     if (pci_is_root_bus(bus))
0228         return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
0229 
0230     return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size,
0231                        val);
0232 }
0233 
0234 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
0235                  int where, int size, u32 val)
0236 {
0237     struct rockchip_pcie *rockchip = bus->sysdata;
0238 
0239     if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
0240         return PCIBIOS_DEVICE_NOT_FOUND;
0241 
0242     if (pci_is_root_bus(bus))
0243         return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
0244 
0245     return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size,
0246                        val);
0247 }
0248 
0249 static struct pci_ops rockchip_pcie_ops = {
0250     .read = rockchip_pcie_rd_conf,
0251     .write = rockchip_pcie_wr_conf,
0252 };
0253 
0254 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
0255 {
0256     int curr;
0257     u32 status, scale, power;
0258 
0259     if (IS_ERR(rockchip->vpcie3v3))
0260         return;
0261 
0262     /*
0263      * Set RC's captured slot power limit and scale if
0264      * vpcie3v3 available. The default values are both zero
0265      * which means the software should set these two according
0266      * to the actual power supply.
0267      */
0268     curr = regulator_get_current_limit(rockchip->vpcie3v3);
0269     if (curr <= 0)
0270         return;
0271 
0272     scale = 3; /* 0.001x */
0273     curr = curr / 1000; /* convert to mA */
0274     power = (curr * 3300) / 1000; /* milliwatt */
0275     while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
0276         if (!scale) {
0277             dev_warn(rockchip->dev, "invalid power supply\n");
0278             return;
0279         }
0280         scale--;
0281         power = power / 10;
0282     }
0283 
0284     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
0285     status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
0286           (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
0287     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
0288 }
0289 
0290 /**
0291  * rockchip_pcie_host_init_port - Initialize hardware
0292  * @rockchip: PCIe port information
0293  */
0294 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
0295 {
0296     struct device *dev = rockchip->dev;
0297     int err, i = MAX_LANE_NUM;
0298     u32 status;
0299 
0300     gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
0301 
0302     err = rockchip_pcie_init_port(rockchip);
0303     if (err)
0304         return err;
0305 
0306     /* Fix the transmitted FTS count desired to exit from L0s. */
0307     status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
0308     status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
0309          (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
0310     rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
0311 
0312     rockchip_pcie_set_power_limit(rockchip);
0313 
0314     /* Set RC's clock architecture as common clock */
0315     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
0316     status |= PCI_EXP_LNKSTA_SLC << 16;
0317     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
0318 
0319     /* Set RC's RCB to 128 */
0320     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
0321     status |= PCI_EXP_LNKCTL_RCB;
0322     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
0323 
0324     /* Enable Gen1 training */
0325     rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
0326                 PCIE_CLIENT_CONFIG);
0327 
0328     gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
0329 
0330     /* 500ms timeout value should be enough for Gen1/2 training */
0331     err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
0332                  status, PCIE_LINK_UP(status), 20,
0333                  500 * USEC_PER_MSEC);
0334     if (err) {
0335         dev_err(dev, "PCIe link training gen1 timeout!\n");
0336         goto err_power_off_phy;
0337     }
0338 
0339     if (rockchip->link_gen == 2) {
0340         /*
0341          * Enable retrain for gen2. This should be configured only after
0342          * gen1 finished.
0343          */
0344         status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
0345         status |= PCI_EXP_LNKCTL_RL;
0346         rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
0347 
0348         err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
0349                      status, PCIE_LINK_IS_GEN2(status), 20,
0350                      500 * USEC_PER_MSEC);
0351         if (err)
0352             dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
0353     }
0354 
0355     /* Check the final link width from negotiated lane counter from MGMT */
0356     status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
0357     status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
0358               PCIE_CORE_PL_CONF_LANE_SHIFT);
0359     dev_dbg(dev, "current link width is x%d\n", status);
0360 
0361     /* Power off unused lane(s) */
0362     rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
0363     for (i = 0; i < MAX_LANE_NUM; i++) {
0364         if (!(rockchip->lanes_map & BIT(i))) {
0365             dev_dbg(dev, "idling lane %d\n", i);
0366             phy_power_off(rockchip->phys[i]);
0367         }
0368     }
0369 
0370     rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
0371                 PCIE_CORE_CONFIG_VENDOR);
0372     rockchip_pcie_write(rockchip,
0373                 PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
0374                 PCIE_RC_CONFIG_RID_CCR);
0375 
0376     /* Clear THP cap's next cap pointer to remove L1 substate cap */
0377     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
0378     status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
0379     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
0380 
0381     /* Clear L0s from RC's link cap */
0382     if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
0383         status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
0384         status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
0385         rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
0386     }
0387 
0388     status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR);
0389     status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK;
0390     status |= PCIE_RC_CONFIG_DCSR_MPS_256;
0391     rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
0392 
0393     return 0;
0394 err_power_off_phy:
0395     while (i--)
0396         phy_power_off(rockchip->phys[i]);
0397     i = MAX_LANE_NUM;
0398     while (i--)
0399         phy_exit(rockchip->phys[i]);
0400     return err;
0401 }
0402 
0403 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
0404 {
0405     struct rockchip_pcie *rockchip = arg;
0406     struct device *dev = rockchip->dev;
0407     u32 reg;
0408     u32 sub_reg;
0409 
0410     reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
0411     if (reg & PCIE_CLIENT_INT_LOCAL) {
0412         dev_dbg(dev, "local interrupt received\n");
0413         sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
0414         if (sub_reg & PCIE_CORE_INT_PRFPE)
0415             dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
0416 
0417         if (sub_reg & PCIE_CORE_INT_CRFPE)
0418             dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
0419 
0420         if (sub_reg & PCIE_CORE_INT_RRPE)
0421             dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
0422 
0423         if (sub_reg & PCIE_CORE_INT_PRFO)
0424             dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
0425 
0426         if (sub_reg & PCIE_CORE_INT_CRFO)
0427             dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
0428 
0429         if (sub_reg & PCIE_CORE_INT_RT)
0430             dev_dbg(dev, "replay timer timed out\n");
0431 
0432         if (sub_reg & PCIE_CORE_INT_RTR)
0433             dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
0434 
0435         if (sub_reg & PCIE_CORE_INT_PE)
0436             dev_dbg(dev, "phy error detected on receive side\n");
0437 
0438         if (sub_reg & PCIE_CORE_INT_MTR)
0439             dev_dbg(dev, "malformed TLP received from the link\n");
0440 
0441         if (sub_reg & PCIE_CORE_INT_UCR)
0442             dev_dbg(dev, "malformed TLP received from the link\n");
0443 
0444         if (sub_reg & PCIE_CORE_INT_FCE)
0445             dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
0446 
0447         if (sub_reg & PCIE_CORE_INT_CT)
0448             dev_dbg(dev, "a request timed out waiting for completion\n");
0449 
0450         if (sub_reg & PCIE_CORE_INT_UTC)
0451             dev_dbg(dev, "unmapped TC error\n");
0452 
0453         if (sub_reg & PCIE_CORE_INT_MMVC)
0454             dev_dbg(dev, "MSI mask register changes\n");
0455 
0456         rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
0457     } else if (reg & PCIE_CLIENT_INT_PHY) {
0458         dev_dbg(dev, "phy link changes\n");
0459         rockchip_pcie_update_txcredit_mui(rockchip);
0460         rockchip_pcie_clr_bw_int(rockchip);
0461     }
0462 
0463     rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
0464                 PCIE_CLIENT_INT_STATUS);
0465 
0466     return IRQ_HANDLED;
0467 }
0468 
0469 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
0470 {
0471     struct rockchip_pcie *rockchip = arg;
0472     struct device *dev = rockchip->dev;
0473     u32 reg;
0474 
0475     reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
0476     if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
0477         dev_dbg(dev, "legacy done interrupt received\n");
0478 
0479     if (reg & PCIE_CLIENT_INT_MSG)
0480         dev_dbg(dev, "message done interrupt received\n");
0481 
0482     if (reg & PCIE_CLIENT_INT_HOT_RST)
0483         dev_dbg(dev, "hot reset interrupt received\n");
0484 
0485     if (reg & PCIE_CLIENT_INT_DPA)
0486         dev_dbg(dev, "dpa interrupt received\n");
0487 
0488     if (reg & PCIE_CLIENT_INT_FATAL_ERR)
0489         dev_dbg(dev, "fatal error interrupt received\n");
0490 
0491     if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
0492         dev_dbg(dev, "no fatal error interrupt received\n");
0493 
0494     if (reg & PCIE_CLIENT_INT_CORR_ERR)
0495         dev_dbg(dev, "correctable error interrupt received\n");
0496 
0497     if (reg & PCIE_CLIENT_INT_PHY)
0498         dev_dbg(dev, "phy interrupt received\n");
0499 
0500     rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
0501                   PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
0502                   PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
0503                   PCIE_CLIENT_INT_NFATAL_ERR |
0504                   PCIE_CLIENT_INT_CORR_ERR |
0505                   PCIE_CLIENT_INT_PHY),
0506            PCIE_CLIENT_INT_STATUS);
0507 
0508     return IRQ_HANDLED;
0509 }
0510 
0511 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
0512 {
0513     struct irq_chip *chip = irq_desc_get_chip(desc);
0514     struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
0515     struct device *dev = rockchip->dev;
0516     u32 reg;
0517     u32 hwirq;
0518     int ret;
0519 
0520     chained_irq_enter(chip, desc);
0521 
0522     reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
0523     reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
0524 
0525     while (reg) {
0526         hwirq = ffs(reg) - 1;
0527         reg &= ~BIT(hwirq);
0528 
0529         ret = generic_handle_domain_irq(rockchip->irq_domain, hwirq);
0530         if (ret)
0531             dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
0532     }
0533 
0534     chained_irq_exit(chip, desc);
0535 }
0536 
0537 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
0538 {
0539     int irq, err;
0540     struct device *dev = rockchip->dev;
0541     struct platform_device *pdev = to_platform_device(dev);
0542 
0543     irq = platform_get_irq_byname(pdev, "sys");
0544     if (irq < 0)
0545         return irq;
0546 
0547     err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
0548                    IRQF_SHARED, "pcie-sys", rockchip);
0549     if (err) {
0550         dev_err(dev, "failed to request PCIe subsystem IRQ\n");
0551         return err;
0552     }
0553 
0554     irq = platform_get_irq_byname(pdev, "legacy");
0555     if (irq < 0)
0556         return irq;
0557 
0558     irq_set_chained_handler_and_data(irq,
0559                      rockchip_pcie_legacy_int_handler,
0560                      rockchip);
0561 
0562     irq = platform_get_irq_byname(pdev, "client");
0563     if (irq < 0)
0564         return irq;
0565 
0566     err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
0567                    IRQF_SHARED, "pcie-client", rockchip);
0568     if (err) {
0569         dev_err(dev, "failed to request PCIe client IRQ\n");
0570         return err;
0571     }
0572 
0573     return 0;
0574 }
0575 
0576 /**
0577  * rockchip_pcie_parse_host_dt - Parse Device Tree
0578  * @rockchip: PCIe port information
0579  *
0580  * Return: '0' on success and error value on failure
0581  */
0582 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
0583 {
0584     struct device *dev = rockchip->dev;
0585     int err;
0586 
0587     err = rockchip_pcie_parse_dt(rockchip);
0588     if (err)
0589         return err;
0590 
0591     rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
0592     if (IS_ERR(rockchip->vpcie12v)) {
0593         if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
0594             return PTR_ERR(rockchip->vpcie12v);
0595         dev_info(dev, "no vpcie12v regulator found\n");
0596     }
0597 
0598     rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
0599     if (IS_ERR(rockchip->vpcie3v3)) {
0600         if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
0601             return PTR_ERR(rockchip->vpcie3v3);
0602         dev_info(dev, "no vpcie3v3 regulator found\n");
0603     }
0604 
0605     rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
0606     if (IS_ERR(rockchip->vpcie1v8))
0607         return PTR_ERR(rockchip->vpcie1v8);
0608 
0609     rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
0610     if (IS_ERR(rockchip->vpcie0v9))
0611         return PTR_ERR(rockchip->vpcie0v9);
0612 
0613     return 0;
0614 }
0615 
0616 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
0617 {
0618     struct device *dev = rockchip->dev;
0619     int err;
0620 
0621     if (!IS_ERR(rockchip->vpcie12v)) {
0622         err = regulator_enable(rockchip->vpcie12v);
0623         if (err) {
0624             dev_err(dev, "fail to enable vpcie12v regulator\n");
0625             goto err_out;
0626         }
0627     }
0628 
0629     if (!IS_ERR(rockchip->vpcie3v3)) {
0630         err = regulator_enable(rockchip->vpcie3v3);
0631         if (err) {
0632             dev_err(dev, "fail to enable vpcie3v3 regulator\n");
0633             goto err_disable_12v;
0634         }
0635     }
0636 
0637     err = regulator_enable(rockchip->vpcie1v8);
0638     if (err) {
0639         dev_err(dev, "fail to enable vpcie1v8 regulator\n");
0640         goto err_disable_3v3;
0641     }
0642 
0643     err = regulator_enable(rockchip->vpcie0v9);
0644     if (err) {
0645         dev_err(dev, "fail to enable vpcie0v9 regulator\n");
0646         goto err_disable_1v8;
0647     }
0648 
0649     return 0;
0650 
0651 err_disable_1v8:
0652     regulator_disable(rockchip->vpcie1v8);
0653 err_disable_3v3:
0654     if (!IS_ERR(rockchip->vpcie3v3))
0655         regulator_disable(rockchip->vpcie3v3);
0656 err_disable_12v:
0657     if (!IS_ERR(rockchip->vpcie12v))
0658         regulator_disable(rockchip->vpcie12v);
0659 err_out:
0660     return err;
0661 }
0662 
0663 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
0664 {
0665     rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
0666                 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
0667     rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
0668                 PCIE_CORE_INT_MASK);
0669 
0670     rockchip_pcie_enable_bw_int(rockchip);
0671 }
0672 
0673 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
0674                   irq_hw_number_t hwirq)
0675 {
0676     irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
0677     irq_set_chip_data(irq, domain->host_data);
0678 
0679     return 0;
0680 }
0681 
0682 static const struct irq_domain_ops intx_domain_ops = {
0683     .map = rockchip_pcie_intx_map,
0684 };
0685 
0686 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
0687 {
0688     struct device *dev = rockchip->dev;
0689     struct device_node *intc = of_get_next_child(dev->of_node, NULL);
0690 
0691     if (!intc) {
0692         dev_err(dev, "missing child interrupt-controller node\n");
0693         return -EINVAL;
0694     }
0695 
0696     rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
0697                             &intx_domain_ops, rockchip);
0698     of_node_put(intc);
0699     if (!rockchip->irq_domain) {
0700         dev_err(dev, "failed to get a INTx IRQ domain\n");
0701         return -EINVAL;
0702     }
0703 
0704     return 0;
0705 }
0706 
0707 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
0708                      int region_no, int type, u8 num_pass_bits,
0709                      u32 lower_addr, u32 upper_addr)
0710 {
0711     u32 ob_addr_0;
0712     u32 ob_addr_1;
0713     u32 ob_desc_0;
0714     u32 aw_offset;
0715 
0716     if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
0717         return -EINVAL;
0718     if (num_pass_bits + 1 < 8)
0719         return -EINVAL;
0720     if (num_pass_bits > 63)
0721         return -EINVAL;
0722     if (region_no == 0) {
0723         if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
0724             return -EINVAL;
0725     }
0726     if (region_no != 0) {
0727         if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
0728             return -EINVAL;
0729     }
0730 
0731     aw_offset = (region_no << OB_REG_SIZE_SHIFT);
0732 
0733     ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
0734     ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
0735     ob_addr_1 = upper_addr;
0736     ob_desc_0 = (1 << 23 | type);
0737 
0738     rockchip_pcie_write(rockchip, ob_addr_0,
0739                 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
0740     rockchip_pcie_write(rockchip, ob_addr_1,
0741                 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
0742     rockchip_pcie_write(rockchip, ob_desc_0,
0743                 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
0744     rockchip_pcie_write(rockchip, 0,
0745                 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
0746 
0747     return 0;
0748 }
0749 
0750 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
0751                      int region_no, u8 num_pass_bits,
0752                      u32 lower_addr, u32 upper_addr)
0753 {
0754     u32 ib_addr_0;
0755     u32 ib_addr_1;
0756     u32 aw_offset;
0757 
0758     if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
0759         return -EINVAL;
0760     if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
0761         return -EINVAL;
0762     if (num_pass_bits > 63)
0763         return -EINVAL;
0764 
0765     aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
0766 
0767     ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
0768     ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
0769     ib_addr_1 = upper_addr;
0770 
0771     rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
0772     rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
0773 
0774     return 0;
0775 }
0776 
0777 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
0778 {
0779     struct device *dev = rockchip->dev;
0780     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
0781     struct resource_entry *entry;
0782     u64 pci_addr, size;
0783     int offset;
0784     int err;
0785     int reg_no;
0786 
0787     rockchip_pcie_cfg_configuration_accesses(rockchip,
0788                          AXI_WRAPPER_TYPE0_CFG);
0789     entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
0790     if (!entry)
0791         return -ENODEV;
0792 
0793     size = resource_size(entry->res);
0794     pci_addr = entry->res->start - entry->offset;
0795     rockchip->msg_bus_addr = pci_addr;
0796 
0797     for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
0798         err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
0799                         AXI_WRAPPER_MEM_WRITE,
0800                         20 - 1,
0801                         pci_addr + (reg_no << 20),
0802                         0);
0803         if (err) {
0804             dev_err(dev, "program RC mem outbound ATU failed\n");
0805             return err;
0806         }
0807     }
0808 
0809     err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
0810     if (err) {
0811         dev_err(dev, "program RC mem inbound ATU failed\n");
0812         return err;
0813     }
0814 
0815     entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
0816     if (!entry)
0817         return -ENODEV;
0818 
0819     /* store the register number offset to program RC io outbound ATU */
0820     offset = size >> 20;
0821 
0822     size = resource_size(entry->res);
0823     pci_addr = entry->res->start - entry->offset;
0824 
0825     for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
0826         err = rockchip_pcie_prog_ob_atu(rockchip,
0827                         reg_no + 1 + offset,
0828                         AXI_WRAPPER_IO_WRITE,
0829                         20 - 1,
0830                         pci_addr + (reg_no << 20),
0831                         0);
0832         if (err) {
0833             dev_err(dev, "program RC io outbound ATU failed\n");
0834             return err;
0835         }
0836     }
0837 
0838     /* assign message regions */
0839     rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
0840                   AXI_WRAPPER_NOR_MSG,
0841                   20 - 1, 0, 0);
0842 
0843     rockchip->msg_bus_addr += ((reg_no + offset) << 20);
0844     return err;
0845 }
0846 
0847 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
0848 {
0849     u32 value;
0850     int err;
0851 
0852     /* send PME_TURN_OFF message */
0853     writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
0854 
0855     /* read LTSSM and wait for falling into L2 link state */
0856     err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
0857                  value, PCIE_LINK_IS_L2(value), 20,
0858                  jiffies_to_usecs(5 * HZ));
0859     if (err) {
0860         dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
0861         return err;
0862     }
0863 
0864     return 0;
0865 }
0866 
0867 static int rockchip_pcie_suspend_noirq(struct device *dev)
0868 {
0869     struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
0870     int ret;
0871 
0872     /* disable core and cli int since we don't need to ack PME_ACK */
0873     rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
0874                 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK);
0875     rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
0876 
0877     ret = rockchip_pcie_wait_l2(rockchip);
0878     if (ret) {
0879         rockchip_pcie_enable_interrupts(rockchip);
0880         return ret;
0881     }
0882 
0883     rockchip_pcie_deinit_phys(rockchip);
0884 
0885     rockchip_pcie_disable_clocks(rockchip);
0886 
0887     regulator_disable(rockchip->vpcie0v9);
0888 
0889     return ret;
0890 }
0891 
0892 static int rockchip_pcie_resume_noirq(struct device *dev)
0893 {
0894     struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
0895     int err;
0896 
0897     err = regulator_enable(rockchip->vpcie0v9);
0898     if (err) {
0899         dev_err(dev, "fail to enable vpcie0v9 regulator\n");
0900         return err;
0901     }
0902 
0903     err = rockchip_pcie_enable_clocks(rockchip);
0904     if (err)
0905         goto err_disable_0v9;
0906 
0907     err = rockchip_pcie_host_init_port(rockchip);
0908     if (err)
0909         goto err_pcie_resume;
0910 
0911     err = rockchip_pcie_cfg_atu(rockchip);
0912     if (err)
0913         goto err_err_deinit_port;
0914 
0915     /* Need this to enter L1 again */
0916     rockchip_pcie_update_txcredit_mui(rockchip);
0917     rockchip_pcie_enable_interrupts(rockchip);
0918 
0919     return 0;
0920 
0921 err_err_deinit_port:
0922     rockchip_pcie_deinit_phys(rockchip);
0923 err_pcie_resume:
0924     rockchip_pcie_disable_clocks(rockchip);
0925 err_disable_0v9:
0926     regulator_disable(rockchip->vpcie0v9);
0927     return err;
0928 }
0929 
0930 static int rockchip_pcie_probe(struct platform_device *pdev)
0931 {
0932     struct rockchip_pcie *rockchip;
0933     struct device *dev = &pdev->dev;
0934     struct pci_host_bridge *bridge;
0935     int err;
0936 
0937     if (!dev->of_node)
0938         return -ENODEV;
0939 
0940     bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
0941     if (!bridge)
0942         return -ENOMEM;
0943 
0944     rockchip = pci_host_bridge_priv(bridge);
0945 
0946     platform_set_drvdata(pdev, rockchip);
0947     rockchip->dev = dev;
0948     rockchip->is_rc = true;
0949 
0950     err = rockchip_pcie_parse_host_dt(rockchip);
0951     if (err)
0952         return err;
0953 
0954     err = rockchip_pcie_enable_clocks(rockchip);
0955     if (err)
0956         return err;
0957 
0958     err = rockchip_pcie_set_vpcie(rockchip);
0959     if (err) {
0960         dev_err(dev, "failed to set vpcie regulator\n");
0961         goto err_set_vpcie;
0962     }
0963 
0964     err = rockchip_pcie_host_init_port(rockchip);
0965     if (err)
0966         goto err_vpcie;
0967 
0968     err = rockchip_pcie_init_irq_domain(rockchip);
0969     if (err < 0)
0970         goto err_deinit_port;
0971 
0972     err = rockchip_pcie_cfg_atu(rockchip);
0973     if (err)
0974         goto err_remove_irq_domain;
0975 
0976     rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
0977     if (!rockchip->msg_region) {
0978         err = -ENOMEM;
0979         goto err_remove_irq_domain;
0980     }
0981 
0982     bridge->sysdata = rockchip;
0983     bridge->ops = &rockchip_pcie_ops;
0984 
0985     err = rockchip_pcie_setup_irq(rockchip);
0986     if (err)
0987         goto err_remove_irq_domain;
0988 
0989     rockchip_pcie_enable_interrupts(rockchip);
0990 
0991     err = pci_host_probe(bridge);
0992     if (err < 0)
0993         goto err_remove_irq_domain;
0994 
0995     return 0;
0996 
0997 err_remove_irq_domain:
0998     irq_domain_remove(rockchip->irq_domain);
0999 err_deinit_port:
1000     rockchip_pcie_deinit_phys(rockchip);
1001 err_vpcie:
1002     if (!IS_ERR(rockchip->vpcie12v))
1003         regulator_disable(rockchip->vpcie12v);
1004     if (!IS_ERR(rockchip->vpcie3v3))
1005         regulator_disable(rockchip->vpcie3v3);
1006     regulator_disable(rockchip->vpcie1v8);
1007     regulator_disable(rockchip->vpcie0v9);
1008 err_set_vpcie:
1009     rockchip_pcie_disable_clocks(rockchip);
1010     return err;
1011 }
1012 
1013 static int rockchip_pcie_remove(struct platform_device *pdev)
1014 {
1015     struct device *dev = &pdev->dev;
1016     struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1017     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
1018 
1019     pci_stop_root_bus(bridge->bus);
1020     pci_remove_root_bus(bridge->bus);
1021     irq_domain_remove(rockchip->irq_domain);
1022 
1023     rockchip_pcie_deinit_phys(rockchip);
1024 
1025     rockchip_pcie_disable_clocks(rockchip);
1026 
1027     if (!IS_ERR(rockchip->vpcie12v))
1028         regulator_disable(rockchip->vpcie12v);
1029     if (!IS_ERR(rockchip->vpcie3v3))
1030         regulator_disable(rockchip->vpcie3v3);
1031     regulator_disable(rockchip->vpcie1v8);
1032     regulator_disable(rockchip->vpcie0v9);
1033 
1034     return 0;
1035 }
1036 
1037 static const struct dev_pm_ops rockchip_pcie_pm_ops = {
1038     NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq,
1039                   rockchip_pcie_resume_noirq)
1040 };
1041 
1042 static const struct of_device_id rockchip_pcie_of_match[] = {
1043     { .compatible = "rockchip,rk3399-pcie", },
1044     {}
1045 };
1046 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match);
1047 
1048 static struct platform_driver rockchip_pcie_driver = {
1049     .driver = {
1050         .name = "rockchip-pcie",
1051         .of_match_table = rockchip_pcie_of_match,
1052         .pm = &rockchip_pcie_pm_ops,
1053     },
1054     .probe = rockchip_pcie_probe,
1055     .remove = rockchip_pcie_remove,
1056 };
1057 module_platform_driver(rockchip_pcie_driver);
1058 
1059 MODULE_AUTHOR("Rockchip Inc");
1060 MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
1061 MODULE_LICENSE("GPL v2");
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