pci/controller/pcie-rcar.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * PCIe driver for Renesas R-Car SoCs
0004  *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
0005  *
0006  * Author: Phil Edworthy <phil.edworthy@renesas.com>
0007  */
0008
0009 #ifndef _PCIE_RCAR_H
0010 #define _PCIE_RCAR_H
0011
0012 #define PCIECAR         0x000010
0013 #define PCIECCTLR       0x000018
0014 #define  CONFIG_SEND_ENABLE BIT(31)
0015 #define  TYPE0          (0 << 8)
0016 #define  TYPE1          BIT(8)
0017 #define PCIECDR         0x000020
0018 #define PCIEMSR         0x000028
0019 #define PCIEINTXR       0x000400
0020 #define  ASTINTX        BIT(16)
0021 #define PCIEPHYSR       0x0007f0
0022 #define  PHYRDY         BIT(0)
0023 #define PCIEMSITXR      0x000840
0024
0025 /* Transfer control */
0026 #define PCIETCTLR       0x02000
0027 #define  DL_DOWN        BIT(3)
0028 #define  CFINIT         BIT(0)
0029 #define PCIETSTR        0x02004
0030 #define  DATA_LINK_ACTIVE   BIT(0)
0031 #define PCIEERRFR       0x02020
0032 #define  UNSUPPORTED_REQUEST    BIT(4)
0033 #define PCIEMSIFR       0x02044
0034 #define PCIEMSIALR      0x02048
0035 #define  MSIFE          BIT(0)
0036 #define PCIEMSIAUR      0x0204c
0037 #define PCIEMSIIER      0x02050
0038
0039 /* root port address */
0040 #define PCIEPRAR(x)     (0x02080 + ((x) * 0x4))
0041
0042 /* local address reg & mask */
0043 #define PCIELAR(x)      (0x02200 + ((x) * 0x20))
0044 #define PCIELAMR(x)     (0x02208 + ((x) * 0x20))
0045 #define  LAM_PREFETCH       BIT(3)
0046 #define  LAM_64BIT      BIT(2)
0047 #define  LAR_ENABLE     BIT(1)
0048
0049 /* PCIe address reg & mask */
0050 #define PCIEPALR(x)     (0x03400 + ((x) * 0x20))
0051 #define PCIEPAUR(x)     (0x03404 + ((x) * 0x20))
0052 #define PCIEPAMR(x)     (0x03408 + ((x) * 0x20))
0053 #define PCIEPTCTLR(x)       (0x0340c + ((x) * 0x20))
0054 #define  PAR_ENABLE     BIT(31)
0055 #define  IO_SPACE       BIT(8)
0056
0057 /* Configuration */
0058 #define PCICONF(x)      (0x010000 + ((x) * 0x4))
0059 #define  INTDIS         BIT(10)
0060 #define PMCAP(x)        (0x010040 + ((x) * 0x4))
0061 #define MSICAP(x)       (0x010050 + ((x) * 0x4))
0062 #define  MSICAP0_MSIE       BIT(16)
0063 #define  MSICAP0_MMESCAP_OFFSET 17
0064 #define  MSICAP0_MMESE_OFFSET   20
0065 #define  MSICAP0_MMESE_MASK GENMASK(22, 20)
0066 #define EXPCAP(x)       (0x010070 + ((x) * 0x4))
0067 #define VCCAP(x)        (0x010100 + ((x) * 0x4))
0068
0069 /* link layer */
0070 #define IDSETR0         0x011000
0071 #define IDSETR1         0x011004
0072 #define SUBIDSETR       0x011024
0073 #define TLCTLR          0x011048
0074 #define MACSR           0x011054
0075 #define  SPCHGFIN       BIT(4)
0076 #define  SPCHGFAIL      BIT(6)
0077 #define  SPCHGSUC       BIT(7)
0078 #define  LINK_SPEED     (0xf << 16)
0079 #define  LINK_SPEED_2_5GTS  (1 << 16)
0080 #define  LINK_SPEED_5_0GTS  (2 << 16)
0081 #define MACCTLR         0x011058
0082 #define  MACCTLR_NFTS_MASK  GENMASK(23, 16) /* The name is from SH7786 */
0083 #define  SPEED_CHANGE       BIT(24)
0084 #define  SCRAMBLE_DISABLE   BIT(27)
0085 #define  LTSMDIS        BIT(31)
0086 #define  MACCTLR_INIT_VAL   (LTSMDIS | MACCTLR_NFTS_MASK)
0087 #define PMSR            0x01105c
0088 #define  L1FAEG         BIT(31)
0089 #define  PMEL1RX        BIT(23)
0090 #define  PMSTATE        GENMASK(18, 16)
0091 #define  PMSTATE_L1     (3 << 16)
0092 #define PMCTLR          0x011060
0093 #define  L1IATN         BIT(31)
0094
0095 #define MACS2R          0x011078
0096 #define MACCGSPSETR     0x011084
0097 #define  SPCNGRSN       BIT(31)
0098
0099 /* R-Car H1 PHY */
0100 #define H1_PCIEPHYADRR      0x04000c
0101 #define  WRITE_CMD      BIT(16)
0102 #define  PHY_ACK        BIT(24)
0103 #define  RATE_POS       12
0104 #define  LANE_POS       8
0105 #define  ADR_POS        0
0106 #define H1_PCIEPHYDOUTR     0x040014
0107
0108 /* R-Car Gen2 PHY */
0109 #define GEN2_PCIEPHYADDR    0x780
0110 #define GEN2_PCIEPHYDATA    0x784
0111 #define GEN2_PCIEPHYCTRL    0x78c
0112
0113 #define INT_PCI_MSI_NR      32
0114
0115 #define RCONF(x)        (PCICONF(0) + (x))
0116 #define RPMCAP(x)       (PMCAP(0) + (x))
0117 #define REXPCAP(x)      (EXPCAP(0) + (x))
0118 #define RVCCAP(x)       (VCCAP(0) + (x))
0119
0120 #define PCIE_CONF_BUS(b)    (((b) & 0xff) << 24)
0121 #define PCIE_CONF_DEV(d)    (((d) & 0x1f) << 19)
0122 #define PCIE_CONF_FUNC(f)   (((f) & 0x7) << 16)
0123
0124 #define RCAR_PCI_MAX_RESOURCES  4
0125 #define MAX_NR_INBOUND_MAPS 6
0126
0127 struct rcar_pcie {
0128     struct device       *dev;
0129     void __iomem        *base;
0130 };
0131
0132 enum {
0133     RCAR_PCI_ACCESS_READ,
0134     RCAR_PCI_ACCESS_WRITE,
0135 };
0136
0137 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
0138 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
0139 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
0140 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
0141 int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
0142 void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
0143                 struct resource_entry *window);
0144 void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
0145                u64 pci_addr, u64 flags, int idx, bool host);
0146
0147 #endif