pci/controller/pcie-rcar.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe driver for Renesas R-Car SoCs
0004  *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
0005  *
0006  * Author: Phil Edworthy <phil.edworthy@renesas.com>
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/pci.h>
0011
0012 #include "pcie-rcar.h"
0013
0014 void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg)
0015 {
0016     writel(val, pcie->base + reg);
0017 }
0018
0019 u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
0020 {
0021     return readl(pcie->base + reg);
0022 }
0023
0024 void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
0025 {
0026     unsigned int shift = BITS_PER_BYTE * (where & 3);
0027     u32 val = rcar_pci_read_reg(pcie, where & ~3);
0028
0029     val &= ~(mask << shift);
0030     val |= data << shift;
0031     rcar_pci_write_reg(pcie, val, where & ~3);
0032 }
0033
0034 int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
0035 {
0036     unsigned int timeout = 10;
0037
0038     while (timeout--) {
0039         if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
0040             return 0;
0041
0042         msleep(5);
0043     }
0044
0045     return -ETIMEDOUT;
0046 }
0047
0048 int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
0049 {
0050     unsigned int timeout = 10000;
0051
0052     while (timeout--) {
0053         if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
0054             return 0;
0055
0056         udelay(5);
0057         cpu_relax();
0058     }
0059
0060     return -ETIMEDOUT;
0061 }
0062
0063 void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
0064                 struct resource_entry *window)
0065 {
0066     /* Setup PCIe address space mappings for each resource */
0067     struct resource *res = window->res;
0068     resource_size_t res_start;
0069     resource_size_t size;
0070     u32 mask;
0071
0072     rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
0073
0074     /*
0075      * The PAMR mask is calculated in units of 128Bytes, which
0076      * keeps things pretty simple.
0077      */
0078     size = resource_size(res);
0079     if (size > 128)
0080         mask = (roundup_pow_of_two(size) / SZ_128) - 1;
0081     else
0082         mask = 0x0;
0083     rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
0084
0085     if (res->flags & IORESOURCE_IO)
0086         res_start = pci_pio_to_address(res->start) - window->offset;
0087     else
0088         res_start = res->start - window->offset;
0089
0090     rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
0091     rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
0092                PCIEPALR(win));
0093
0094     /* First resource is for IO */
0095     mask = PAR_ENABLE;
0096     if (res->flags & IORESOURCE_IO)
0097         mask |= IO_SPACE;
0098
0099     rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
0100 }
0101
0102 void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
0103                u64 pci_addr, u64 flags, int idx, bool host)
0104 {
0105     /*
0106      * Set up 64-bit inbound regions as the range parser doesn't
0107      * distinguish between 32 and 64-bit types.
0108      */
0109     if (host)
0110         rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
0111                    PCIEPRAR(idx));
0112     rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
0113     rcar_pci_write_reg(pcie, flags, PCIELAMR(idx));
0114
0115     if (host)
0116         rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
0117                    PCIEPRAR(idx + 1));
0118     rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx + 1));
0119     rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
0120 }