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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe driver for Renesas R-Car SoCs
0004  *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
0005  *
0006  * Based on:
0007  *  arch/sh/drivers/pci/pcie-sh7786.c
0008  *  arch/sh/drivers/pci/ops-sh7786.c
0009  *  Copyright (C) 2009 - 2011  Paul Mundt
0010  *
0011  * Author: Phil Edworthy <phil.edworthy@renesas.com>
0012  */
0013 
0014 #include <linux/bitops.h>
0015 #include <linux/clk.h>
0016 #include <linux/clk-provider.h>
0017 #include <linux/delay.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/irq.h>
0020 #include <linux/irqdomain.h>
0021 #include <linux/kernel.h>
0022 #include <linux/init.h>
0023 #include <linux/iopoll.h>
0024 #include <linux/msi.h>
0025 #include <linux/of_address.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/of_platform.h>
0028 #include <linux/pci.h>
0029 #include <linux/phy/phy.h>
0030 #include <linux/platform_device.h>
0031 #include <linux/pm_runtime.h>
0032 
0033 #include "pcie-rcar.h"
0034 
0035 struct rcar_msi {
0036     DECLARE_BITMAP(used, INT_PCI_MSI_NR);
0037     struct irq_domain *domain;
0038     struct mutex map_lock;
0039     spinlock_t mask_lock;
0040     int irq1;
0041     int irq2;
0042 };
0043 
0044 #ifdef CONFIG_ARM
0045 /*
0046  * Here we keep a static copy of the remapped PCIe controller address.
0047  * This is only used on aarch32 systems, all of which have one single
0048  * PCIe controller, to provide quick access to the PCIe controller in
0049  * the L1 link state fixup function, called from the ARM fault handler.
0050  */
0051 static void __iomem *pcie_base;
0052 /*
0053  * Static copy of PCIe device pointer, so we can check whether the
0054  * device is runtime suspended or not.
0055  */
0056 static struct device *pcie_dev;
0057 #endif
0058 
0059 /* Structure representing the PCIe interface */
0060 struct rcar_pcie_host {
0061     struct rcar_pcie    pcie;
0062     struct phy      *phy;
0063     struct clk      *bus_clk;
0064     struct          rcar_msi msi;
0065     int         (*phy_init_fn)(struct rcar_pcie_host *host);
0066 };
0067 
0068 static DEFINE_SPINLOCK(pmsr_lock);
0069 
0070 static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base)
0071 {
0072     unsigned long flags;
0073     u32 pmsr, val;
0074     int ret = 0;
0075 
0076     spin_lock_irqsave(&pmsr_lock, flags);
0077 
0078     if (!pcie_base || pm_runtime_suspended(pcie_dev)) {
0079         ret = -EINVAL;
0080         goto unlock_exit;
0081     }
0082 
0083     pmsr = readl(pcie_base + PMSR);
0084 
0085     /*
0086      * Test if the PCIe controller received PM_ENTER_L1 DLLP and
0087      * the PCIe controller is not in L1 link state. If true, apply
0088      * fix, which will put the controller into L1 link state, from
0089      * which it can return to L0s/L0 on its own.
0090      */
0091     if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) {
0092         writel(L1IATN, pcie_base + PMCTLR);
0093         ret = readl_poll_timeout_atomic(pcie_base + PMSR, val,
0094                         val & L1FAEG, 10, 1000);
0095         WARN(ret, "Timeout waiting for L1 link state, ret=%d\n", ret);
0096         writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
0097     }
0098 
0099 unlock_exit:
0100     spin_unlock_irqrestore(&pmsr_lock, flags);
0101     return ret;
0102 }
0103 
0104 static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
0105 {
0106     return container_of(msi, struct rcar_pcie_host, msi);
0107 }
0108 
0109 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
0110 {
0111     unsigned int shift = BITS_PER_BYTE * (where & 3);
0112     u32 val = rcar_pci_read_reg(pcie, where & ~3);
0113 
0114     return val >> shift;
0115 }
0116 
0117 #ifdef CONFIG_ARM
0118 #define __rcar_pci_rw_reg_workaround(instr)             \
0119         "   .arch armv7-a\n"                \
0120         "1: " instr " %1, [%2]\n"               \
0121         "2: isb\n"                      \
0122         "3: .pushsection .text.fixup,\"ax\"\n"      \
0123         "   .align  2\n"                    \
0124         "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \
0125         "   b   3b\n"                   \
0126         "   .popsection\n"                  \
0127         "   .pushsection __ex_table,\"a\"\n"        \
0128         "   .align  3\n"                    \
0129         "   .long   1b, 4b\n"               \
0130         "   .long   2b, 4b\n"               \
0131         "   .popsection\n"
0132 #endif
0133 
0134 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val,
0135                      unsigned int reg)
0136 {
0137     int error = PCIBIOS_SUCCESSFUL;
0138 #ifdef CONFIG_ARM
0139     asm volatile(
0140         __rcar_pci_rw_reg_workaround("str")
0141     : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory");
0142 #else
0143     rcar_pci_write_reg(pcie, val, reg);
0144 #endif
0145     return error;
0146 }
0147 
0148 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val,
0149                     unsigned int reg)
0150 {
0151     int error = PCIBIOS_SUCCESSFUL;
0152 #ifdef CONFIG_ARM
0153     asm volatile(
0154         __rcar_pci_rw_reg_workaround("ldr")
0155     : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory");
0156 
0157     if (error != PCIBIOS_SUCCESSFUL)
0158         PCI_SET_ERROR_RESPONSE(val);
0159 #else
0160     *val = rcar_pci_read_reg(pcie, reg);
0161 #endif
0162     return error;
0163 }
0164 
0165 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
0166 static int rcar_pcie_config_access(struct rcar_pcie_host *host,
0167         unsigned char access_type, struct pci_bus *bus,
0168         unsigned int devfn, int where, u32 *data)
0169 {
0170     struct rcar_pcie *pcie = &host->pcie;
0171     unsigned int dev, func, reg, index;
0172     int ret;
0173 
0174     /* Wake the bus up in case it is in L1 state. */
0175     ret = rcar_pcie_wakeup(pcie->dev, pcie->base);
0176     if (ret) {
0177         PCI_SET_ERROR_RESPONSE(data);
0178         return PCIBIOS_SET_FAILED;
0179     }
0180 
0181     dev = PCI_SLOT(devfn);
0182     func = PCI_FUNC(devfn);
0183     reg = where & ~3;
0184     index = reg / 4;
0185 
0186     /*
0187      * While each channel has its own memory-mapped extended config
0188      * space, it's generally only accessible when in endpoint mode.
0189      * When in root complex mode, the controller is unable to target
0190      * itself with either type 0 or type 1 accesses, and indeed, any
0191      * controller initiated target transfer to its own config space
0192      * result in a completer abort.
0193      *
0194      * Each channel effectively only supports a single device, but as
0195      * the same channel <-> device access works for any PCI_SLOT()
0196      * value, we cheat a bit here and bind the controller's config
0197      * space to devfn 0 in order to enable self-enumeration. In this
0198      * case the regular ECAR/ECDR path is sidelined and the mangled
0199      * config access itself is initiated as an internal bus transaction.
0200      */
0201     if (pci_is_root_bus(bus)) {
0202         if (dev != 0)
0203             return PCIBIOS_DEVICE_NOT_FOUND;
0204 
0205         if (access_type == RCAR_PCI_ACCESS_READ)
0206             *data = rcar_pci_read_reg(pcie, PCICONF(index));
0207         else
0208             rcar_pci_write_reg(pcie, *data, PCICONF(index));
0209 
0210         return PCIBIOS_SUCCESSFUL;
0211     }
0212 
0213     /* Clear errors */
0214     rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
0215 
0216     /* Set the PIO address */
0217     rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
0218         PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
0219 
0220     /* Enable the configuration access */
0221     if (pci_is_root_bus(bus->parent))
0222         rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
0223     else
0224         rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
0225 
0226     /* Check for errors */
0227     if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
0228         return PCIBIOS_DEVICE_NOT_FOUND;
0229 
0230     /* Check for master and target aborts */
0231     if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
0232         (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
0233         return PCIBIOS_DEVICE_NOT_FOUND;
0234 
0235     if (access_type == RCAR_PCI_ACCESS_READ)
0236         ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR);
0237     else
0238         ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR);
0239 
0240     /* Disable the configuration access */
0241     rcar_pci_write_reg(pcie, 0, PCIECCTLR);
0242 
0243     return ret;
0244 }
0245 
0246 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
0247                    int where, int size, u32 *val)
0248 {
0249     struct rcar_pcie_host *host = bus->sysdata;
0250     int ret;
0251 
0252     ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
0253                       bus, devfn, where, val);
0254     if (ret != PCIBIOS_SUCCESSFUL)
0255         return ret;
0256 
0257     if (size == 1)
0258         *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
0259     else if (size == 2)
0260         *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
0261 
0262     dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
0263         bus->number, devfn, where, size, *val);
0264 
0265     return ret;
0266 }
0267 
0268 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
0269 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
0270                 int where, int size, u32 val)
0271 {
0272     struct rcar_pcie_host *host = bus->sysdata;
0273     unsigned int shift;
0274     u32 data;
0275     int ret;
0276 
0277     ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ,
0278                       bus, devfn, where, &data);
0279     if (ret != PCIBIOS_SUCCESSFUL)
0280         return ret;
0281 
0282     dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
0283         bus->number, devfn, where, size, val);
0284 
0285     if (size == 1) {
0286         shift = BITS_PER_BYTE * (where & 3);
0287         data &= ~(0xff << shift);
0288         data |= ((val & 0xff) << shift);
0289     } else if (size == 2) {
0290         shift = BITS_PER_BYTE * (where & 2);
0291         data &= ~(0xffff << shift);
0292         data |= ((val & 0xffff) << shift);
0293     } else
0294         data = val;
0295 
0296     ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE,
0297                       bus, devfn, where, &data);
0298 
0299     return ret;
0300 }
0301 
0302 static struct pci_ops rcar_pcie_ops = {
0303     .read   = rcar_pcie_read_conf,
0304     .write  = rcar_pcie_write_conf,
0305 };
0306 
0307 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
0308 {
0309     struct device *dev = pcie->dev;
0310     unsigned int timeout = 1000;
0311     u32 macsr;
0312 
0313     if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
0314         return;
0315 
0316     if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
0317         dev_err(dev, "Speed change already in progress\n");
0318         return;
0319     }
0320 
0321     macsr = rcar_pci_read_reg(pcie, MACSR);
0322     if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
0323         goto done;
0324 
0325     /* Set target link speed to 5.0 GT/s */
0326     rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
0327            PCI_EXP_LNKSTA_CLS_5_0GB);
0328 
0329     /* Set speed change reason as intentional factor */
0330     rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
0331 
0332     /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
0333     if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
0334         rcar_pci_write_reg(pcie, macsr, MACSR);
0335 
0336     /* Start link speed change */
0337     rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
0338 
0339     while (timeout--) {
0340         macsr = rcar_pci_read_reg(pcie, MACSR);
0341         if (macsr & SPCHGFIN) {
0342             /* Clear the interrupt bits */
0343             rcar_pci_write_reg(pcie, macsr, MACSR);
0344 
0345             if (macsr & SPCHGFAIL)
0346                 dev_err(dev, "Speed change failed\n");
0347 
0348             goto done;
0349         }
0350 
0351         msleep(1);
0352     }
0353 
0354     dev_err(dev, "Speed change timed out\n");
0355 
0356 done:
0357     dev_info(dev, "Current link speed is %s GT/s\n",
0358          (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
0359 }
0360 
0361 static void rcar_pcie_hw_enable(struct rcar_pcie_host *host)
0362 {
0363     struct rcar_pcie *pcie = &host->pcie;
0364     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
0365     struct resource_entry *win;
0366     LIST_HEAD(res);
0367     int i = 0;
0368 
0369     /* Try setting 5 GT/s link speed */
0370     rcar_pcie_force_speedup(pcie);
0371 
0372     /* Setup PCI resources */
0373     resource_list_for_each_entry(win, &bridge->windows) {
0374         struct resource *res = win->res;
0375 
0376         if (!res->flags)
0377             continue;
0378 
0379         switch (resource_type(res)) {
0380         case IORESOURCE_IO:
0381         case IORESOURCE_MEM:
0382             rcar_pcie_set_outbound(pcie, i, win);
0383             i++;
0384             break;
0385         }
0386     }
0387 }
0388 
0389 static int rcar_pcie_enable(struct rcar_pcie_host *host)
0390 {
0391     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
0392 
0393     rcar_pcie_hw_enable(host);
0394 
0395     pci_add_flags(PCI_REASSIGN_ALL_BUS);
0396 
0397     bridge->sysdata = host;
0398     bridge->ops = &rcar_pcie_ops;
0399 
0400     return pci_host_probe(bridge);
0401 }
0402 
0403 static int phy_wait_for_ack(struct rcar_pcie *pcie)
0404 {
0405     struct device *dev = pcie->dev;
0406     unsigned int timeout = 100;
0407 
0408     while (timeout--) {
0409         if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
0410             return 0;
0411 
0412         udelay(100);
0413     }
0414 
0415     dev_err(dev, "Access to PCIe phy timed out\n");
0416 
0417     return -ETIMEDOUT;
0418 }
0419 
0420 static void phy_write_reg(struct rcar_pcie *pcie,
0421               unsigned int rate, u32 addr,
0422               unsigned int lane, u32 data)
0423 {
0424     u32 phyaddr;
0425 
0426     phyaddr = WRITE_CMD |
0427         ((rate & 1) << RATE_POS) |
0428         ((lane & 0xf) << LANE_POS) |
0429         ((addr & 0xff) << ADR_POS);
0430 
0431     /* Set write data */
0432     rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
0433     rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
0434 
0435     /* Ignore errors as they will be dealt with if the data link is down */
0436     phy_wait_for_ack(pcie);
0437 
0438     /* Clear command */
0439     rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
0440     rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
0441 
0442     /* Ignore errors as they will be dealt with if the data link is down */
0443     phy_wait_for_ack(pcie);
0444 }
0445 
0446 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
0447 {
0448     int err;
0449 
0450     /* Begin initialization */
0451     rcar_pci_write_reg(pcie, 0, PCIETCTLR);
0452 
0453     /* Set mode */
0454     rcar_pci_write_reg(pcie, 1, PCIEMSR);
0455 
0456     err = rcar_pcie_wait_for_phyrdy(pcie);
0457     if (err)
0458         return err;
0459 
0460     /*
0461      * Initial header for port config space is type 1, set the device
0462      * class to match. Hardware takes care of propagating the IDSETR
0463      * settings, so there is no need to bother with a quirk.
0464      */
0465     rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1);
0466 
0467     /*
0468      * Setup Secondary Bus Number & Subordinate Bus Number, even though
0469      * they aren't used, to avoid bridge being detected as broken.
0470      */
0471     rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
0472     rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
0473 
0474     /* Initialize default capabilities. */
0475     rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
0476     rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
0477         PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
0478     rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
0479         PCI_HEADER_TYPE_BRIDGE);
0480 
0481     /* Enable data link layer active state reporting */
0482     rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
0483         PCI_EXP_LNKCAP_DLLLARC);
0484 
0485     /* Write out the physical slot number = 0 */
0486     rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
0487 
0488     /* Set the completion timer timeout to the maximum 50ms. */
0489     rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
0490 
0491     /* Terminate list of capabilities (Next Capability Offset=0) */
0492     rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
0493 
0494     /* Enable MSI */
0495     if (IS_ENABLED(CONFIG_PCI_MSI))
0496         rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
0497 
0498     rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
0499 
0500     /* Finish initialization - establish a PCI Express link */
0501     rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
0502 
0503     /* This will timeout if we don't have a link. */
0504     err = rcar_pcie_wait_for_dl(pcie);
0505     if (err)
0506         return err;
0507 
0508     /* Enable INTx interrupts */
0509     rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
0510 
0511     wmb();
0512 
0513     return 0;
0514 }
0515 
0516 static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host)
0517 {
0518     struct rcar_pcie *pcie = &host->pcie;
0519 
0520     /* Initialize the phy */
0521     phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
0522     phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
0523     phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
0524     phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
0525     phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
0526     phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
0527     phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
0528     phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
0529     phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
0530     phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
0531     phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
0532     phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
0533 
0534     phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
0535     phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
0536     phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
0537 
0538     return 0;
0539 }
0540 
0541 static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host)
0542 {
0543     struct rcar_pcie *pcie = &host->pcie;
0544 
0545     /*
0546      * These settings come from the R-Car Series, 2nd Generation User's
0547      * Manual, section 50.3.1 (2) Initialization of the physical layer.
0548      */
0549     rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
0550     rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
0551     rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
0552     rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
0553 
0554     rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
0555     /* The following value is for DC connection, no termination resistor */
0556     rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
0557     rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
0558     rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
0559 
0560     return 0;
0561 }
0562 
0563 static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
0564 {
0565     int err;
0566 
0567     err = phy_init(host->phy);
0568     if (err)
0569         return err;
0570 
0571     err = phy_power_on(host->phy);
0572     if (err)
0573         phy_exit(host->phy);
0574 
0575     return err;
0576 }
0577 
0578 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
0579 {
0580     struct rcar_pcie_host *host = data;
0581     struct rcar_pcie *pcie = &host->pcie;
0582     struct rcar_msi *msi = &host->msi;
0583     struct device *dev = pcie->dev;
0584     unsigned long reg;
0585 
0586     reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
0587 
0588     /* MSI & INTx share an interrupt - we only handle MSI here */
0589     if (!reg)
0590         return IRQ_NONE;
0591 
0592     while (reg) {
0593         unsigned int index = find_first_bit(&reg, 32);
0594         int ret;
0595 
0596         ret = generic_handle_domain_irq(msi->domain->parent, index);
0597         if (ret) {
0598             /* Unknown MSI, just clear it */
0599             dev_dbg(dev, "unexpected MSI\n");
0600             rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
0601         }
0602 
0603         /* see if there's any more pending in this vector */
0604         reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
0605     }
0606 
0607     return IRQ_HANDLED;
0608 }
0609 
0610 static void rcar_msi_top_irq_ack(struct irq_data *d)
0611 {
0612     irq_chip_ack_parent(d);
0613 }
0614 
0615 static void rcar_msi_top_irq_mask(struct irq_data *d)
0616 {
0617     pci_msi_mask_irq(d);
0618     irq_chip_mask_parent(d);
0619 }
0620 
0621 static void rcar_msi_top_irq_unmask(struct irq_data *d)
0622 {
0623     pci_msi_unmask_irq(d);
0624     irq_chip_unmask_parent(d);
0625 }
0626 
0627 static struct irq_chip rcar_msi_top_chip = {
0628     .name       = "PCIe MSI",
0629     .irq_ack    = rcar_msi_top_irq_ack,
0630     .irq_mask   = rcar_msi_top_irq_mask,
0631     .irq_unmask = rcar_msi_top_irq_unmask,
0632 };
0633 
0634 static void rcar_msi_irq_ack(struct irq_data *d)
0635 {
0636     struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
0637     struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
0638 
0639     /* clear the interrupt */
0640     rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
0641 }
0642 
0643 static void rcar_msi_irq_mask(struct irq_data *d)
0644 {
0645     struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
0646     struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
0647     unsigned long flags;
0648     u32 value;
0649 
0650     spin_lock_irqsave(&msi->mask_lock, flags);
0651     value = rcar_pci_read_reg(pcie, PCIEMSIIER);
0652     value &= ~BIT(d->hwirq);
0653     rcar_pci_write_reg(pcie, value, PCIEMSIIER);
0654     spin_unlock_irqrestore(&msi->mask_lock, flags);
0655 }
0656 
0657 static void rcar_msi_irq_unmask(struct irq_data *d)
0658 {
0659     struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
0660     struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
0661     unsigned long flags;
0662     u32 value;
0663 
0664     spin_lock_irqsave(&msi->mask_lock, flags);
0665     value = rcar_pci_read_reg(pcie, PCIEMSIIER);
0666     value |= BIT(d->hwirq);
0667     rcar_pci_write_reg(pcie, value, PCIEMSIIER);
0668     spin_unlock_irqrestore(&msi->mask_lock, flags);
0669 }
0670 
0671 static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
0672 {
0673     return -EINVAL;
0674 }
0675 
0676 static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
0677 {
0678     struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
0679     struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
0680 
0681     msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
0682     msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
0683     msg->data = data->hwirq;
0684 }
0685 
0686 static struct irq_chip rcar_msi_bottom_chip = {
0687     .name           = "Rcar MSI",
0688     .irq_ack        = rcar_msi_irq_ack,
0689     .irq_mask       = rcar_msi_irq_mask,
0690     .irq_unmask     = rcar_msi_irq_unmask,
0691     .irq_set_affinity   = rcar_msi_set_affinity,
0692     .irq_compose_msi_msg    = rcar_compose_msi_msg,
0693 };
0694 
0695 static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
0696                   unsigned int nr_irqs, void *args)
0697 {
0698     struct rcar_msi *msi = domain->host_data;
0699     unsigned int i;
0700     int hwirq;
0701 
0702     mutex_lock(&msi->map_lock);
0703 
0704     hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
0705 
0706     mutex_unlock(&msi->map_lock);
0707 
0708     if (hwirq < 0)
0709         return -ENOSPC;
0710 
0711     for (i = 0; i < nr_irqs; i++)
0712         irq_domain_set_info(domain, virq + i, hwirq + i,
0713                     &rcar_msi_bottom_chip, domain->host_data,
0714                     handle_edge_irq, NULL, NULL);
0715 
0716     return 0;
0717 }
0718 
0719 static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
0720                   unsigned int nr_irqs)
0721 {
0722     struct irq_data *d = irq_domain_get_irq_data(domain, virq);
0723     struct rcar_msi *msi = domain->host_data;
0724 
0725     mutex_lock(&msi->map_lock);
0726 
0727     bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
0728 
0729     mutex_unlock(&msi->map_lock);
0730 }
0731 
0732 static const struct irq_domain_ops rcar_msi_domain_ops = {
0733     .alloc  = rcar_msi_domain_alloc,
0734     .free   = rcar_msi_domain_free,
0735 };
0736 
0737 static struct msi_domain_info rcar_msi_info = {
0738     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
0739            MSI_FLAG_MULTI_PCI_MSI),
0740     .chip   = &rcar_msi_top_chip,
0741 };
0742 
0743 static int rcar_allocate_domains(struct rcar_msi *msi)
0744 {
0745     struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
0746     struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
0747     struct irq_domain *parent;
0748 
0749     parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
0750                       &rcar_msi_domain_ops, msi);
0751     if (!parent) {
0752         dev_err(pcie->dev, "failed to create IRQ domain\n");
0753         return -ENOMEM;
0754     }
0755     irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
0756 
0757     msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
0758     if (!msi->domain) {
0759         dev_err(pcie->dev, "failed to create MSI domain\n");
0760         irq_domain_remove(parent);
0761         return -ENOMEM;
0762     }
0763 
0764     return 0;
0765 }
0766 
0767 static void rcar_free_domains(struct rcar_msi *msi)
0768 {
0769     struct irq_domain *parent = msi->domain->parent;
0770 
0771     irq_domain_remove(msi->domain);
0772     irq_domain_remove(parent);
0773 }
0774 
0775 static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
0776 {
0777     struct rcar_pcie *pcie = &host->pcie;
0778     struct device *dev = pcie->dev;
0779     struct rcar_msi *msi = &host->msi;
0780     struct resource res;
0781     int err;
0782 
0783     mutex_init(&msi->map_lock);
0784     spin_lock_init(&msi->mask_lock);
0785 
0786     err = of_address_to_resource(dev->of_node, 0, &res);
0787     if (err)
0788         return err;
0789 
0790     err = rcar_allocate_domains(msi);
0791     if (err)
0792         return err;
0793 
0794     /* Two irqs are for MSI, but they are also used for non-MSI irqs */
0795     err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
0796                    IRQF_SHARED | IRQF_NO_THREAD,
0797                    rcar_msi_bottom_chip.name, host);
0798     if (err < 0) {
0799         dev_err(dev, "failed to request IRQ: %d\n", err);
0800         goto err;
0801     }
0802 
0803     err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
0804                    IRQF_SHARED | IRQF_NO_THREAD,
0805                    rcar_msi_bottom_chip.name, host);
0806     if (err < 0) {
0807         dev_err(dev, "failed to request IRQ: %d\n", err);
0808         goto err;
0809     }
0810 
0811     /* disable all MSIs */
0812     rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
0813 
0814     /*
0815      * Setup MSI data target using RC base address address, which
0816      * is guaranteed to be in the low 32bit range on any RCar HW.
0817      */
0818     rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
0819     rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
0820 
0821     return 0;
0822 
0823 err:
0824     rcar_free_domains(msi);
0825     return err;
0826 }
0827 
0828 static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
0829 {
0830     struct rcar_pcie *pcie = &host->pcie;
0831 
0832     /* Disable all MSI interrupts */
0833     rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
0834 
0835     /* Disable address decoding of the MSI interrupt, MSIFE */
0836     rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
0837 
0838     rcar_free_domains(&host->msi);
0839 }
0840 
0841 static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
0842 {
0843     struct rcar_pcie *pcie = &host->pcie;
0844     struct device *dev = pcie->dev;
0845     struct resource res;
0846     int err, i;
0847 
0848     host->phy = devm_phy_optional_get(dev, "pcie");
0849     if (IS_ERR(host->phy))
0850         return PTR_ERR(host->phy);
0851 
0852     err = of_address_to_resource(dev->of_node, 0, &res);
0853     if (err)
0854         return err;
0855 
0856     pcie->base = devm_ioremap_resource(dev, &res);
0857     if (IS_ERR(pcie->base))
0858         return PTR_ERR(pcie->base);
0859 
0860     host->bus_clk = devm_clk_get(dev, "pcie_bus");
0861     if (IS_ERR(host->bus_clk)) {
0862         dev_err(dev, "cannot get pcie bus clock\n");
0863         return PTR_ERR(host->bus_clk);
0864     }
0865 
0866     i = irq_of_parse_and_map(dev->of_node, 0);
0867     if (!i) {
0868         dev_err(dev, "cannot get platform resources for msi interrupt\n");
0869         err = -ENOENT;
0870         goto err_irq1;
0871     }
0872     host->msi.irq1 = i;
0873 
0874     i = irq_of_parse_and_map(dev->of_node, 1);
0875     if (!i) {
0876         dev_err(dev, "cannot get platform resources for msi interrupt\n");
0877         err = -ENOENT;
0878         goto err_irq2;
0879     }
0880     host->msi.irq2 = i;
0881 
0882 #ifdef CONFIG_ARM
0883     /* Cache static copy for L1 link state fixup hook on aarch32 */
0884     pcie_base = pcie->base;
0885     pcie_dev = pcie->dev;
0886 #endif
0887 
0888     return 0;
0889 
0890 err_irq2:
0891     irq_dispose_mapping(host->msi.irq1);
0892 err_irq1:
0893     return err;
0894 }
0895 
0896 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
0897                     struct resource_entry *entry,
0898                     int *index)
0899 {
0900     u64 restype = entry->res->flags;
0901     u64 cpu_addr = entry->res->start;
0902     u64 cpu_end = entry->res->end;
0903     u64 pci_addr = entry->res->start - entry->offset;
0904     u32 flags = LAM_64BIT | LAR_ENABLE;
0905     u64 mask;
0906     u64 size = resource_size(entry->res);
0907     int idx = *index;
0908 
0909     if (restype & IORESOURCE_PREFETCH)
0910         flags |= LAM_PREFETCH;
0911 
0912     while (cpu_addr < cpu_end) {
0913         if (idx >= MAX_NR_INBOUND_MAPS - 1) {
0914             dev_err(pcie->dev, "Failed to map inbound regions!\n");
0915             return -EINVAL;
0916         }
0917         /*
0918          * If the size of the range is larger than the alignment of
0919          * the start address, we have to use multiple entries to
0920          * perform the mapping.
0921          */
0922         if (cpu_addr > 0) {
0923             unsigned long nr_zeros = __ffs64(cpu_addr);
0924             u64 alignment = 1ULL << nr_zeros;
0925 
0926             size = min(size, alignment);
0927         }
0928         /* Hardware supports max 4GiB inbound region */
0929         size = min(size, 1ULL << 32);
0930 
0931         mask = roundup_pow_of_two(size) - 1;
0932         mask &= ~0xf;
0933 
0934         rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr,
0935                       lower_32_bits(mask) | flags, idx, true);
0936 
0937         pci_addr += size;
0938         cpu_addr += size;
0939         idx += 2;
0940     }
0941     *index = idx;
0942 
0943     return 0;
0944 }
0945 
0946 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host)
0947 {
0948     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);
0949     struct resource_entry *entry;
0950     int index = 0, err = 0;
0951 
0952     resource_list_for_each_entry(entry, &bridge->dma_ranges) {
0953         err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index);
0954         if (err)
0955             break;
0956     }
0957 
0958     return err;
0959 }
0960 
0961 static const struct of_device_id rcar_pcie_of_match[] = {
0962     { .compatible = "renesas,pcie-r8a7779",
0963       .data = rcar_pcie_phy_init_h1 },
0964     { .compatible = "renesas,pcie-r8a7790",
0965       .data = rcar_pcie_phy_init_gen2 },
0966     { .compatible = "renesas,pcie-r8a7791",
0967       .data = rcar_pcie_phy_init_gen2 },
0968     { .compatible = "renesas,pcie-rcar-gen2",
0969       .data = rcar_pcie_phy_init_gen2 },
0970     { .compatible = "renesas,pcie-r8a7795",
0971       .data = rcar_pcie_phy_init_gen3 },
0972     { .compatible = "renesas,pcie-rcar-gen3",
0973       .data = rcar_pcie_phy_init_gen3 },
0974     {},
0975 };
0976 
0977 static int rcar_pcie_probe(struct platform_device *pdev)
0978 {
0979     struct device *dev = &pdev->dev;
0980     struct rcar_pcie_host *host;
0981     struct rcar_pcie *pcie;
0982     u32 data;
0983     int err;
0984     struct pci_host_bridge *bridge;
0985 
0986     bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));
0987     if (!bridge)
0988         return -ENOMEM;
0989 
0990     host = pci_host_bridge_priv(bridge);
0991     pcie = &host->pcie;
0992     pcie->dev = dev;
0993     platform_set_drvdata(pdev, host);
0994 
0995     pm_runtime_enable(pcie->dev);
0996     err = pm_runtime_get_sync(pcie->dev);
0997     if (err < 0) {
0998         dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
0999         goto err_pm_put;
1000     }
1001 
1002     err = rcar_pcie_get_resources(host);
1003     if (err < 0) {
1004         dev_err(dev, "failed to request resources: %d\n", err);
1005         goto err_pm_put;
1006     }
1007 
1008     err = clk_prepare_enable(host->bus_clk);
1009     if (err) {
1010         dev_err(dev, "failed to enable bus clock: %d\n", err);
1011         goto err_unmap_msi_irqs;
1012     }
1013 
1014     err = rcar_pcie_parse_map_dma_ranges(host);
1015     if (err)
1016         goto err_clk_disable;
1017 
1018     host->phy_init_fn = of_device_get_match_data(dev);
1019     err = host->phy_init_fn(host);
1020     if (err) {
1021         dev_err(dev, "failed to init PCIe PHY\n");
1022         goto err_clk_disable;
1023     }
1024 
1025     /* Failure to get a link might just be that no cards are inserted */
1026     if (rcar_pcie_hw_init(pcie)) {
1027         dev_info(dev, "PCIe link down\n");
1028         err = -ENODEV;
1029         goto err_phy_shutdown;
1030     }
1031 
1032     data = rcar_pci_read_reg(pcie, MACSR);
1033     dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1034 
1035     if (IS_ENABLED(CONFIG_PCI_MSI)) {
1036         err = rcar_pcie_enable_msi(host);
1037         if (err < 0) {
1038             dev_err(dev,
1039                 "failed to enable MSI support: %d\n",
1040                 err);
1041             goto err_phy_shutdown;
1042         }
1043     }
1044 
1045     err = rcar_pcie_enable(host);
1046     if (err)
1047         goto err_msi_teardown;
1048 
1049     return 0;
1050 
1051 err_msi_teardown:
1052     if (IS_ENABLED(CONFIG_PCI_MSI))
1053         rcar_pcie_teardown_msi(host);
1054 
1055 err_phy_shutdown:
1056     if (host->phy) {
1057         phy_power_off(host->phy);
1058         phy_exit(host->phy);
1059     }
1060 
1061 err_clk_disable:
1062     clk_disable_unprepare(host->bus_clk);
1063 
1064 err_unmap_msi_irqs:
1065     irq_dispose_mapping(host->msi.irq2);
1066     irq_dispose_mapping(host->msi.irq1);
1067 
1068 err_pm_put:
1069     pm_runtime_put(dev);
1070     pm_runtime_disable(dev);
1071 
1072     return err;
1073 }
1074 
1075 static int rcar_pcie_resume(struct device *dev)
1076 {
1077     struct rcar_pcie_host *host = dev_get_drvdata(dev);
1078     struct rcar_pcie *pcie = &host->pcie;
1079     unsigned int data;
1080     int err;
1081 
1082     err = rcar_pcie_parse_map_dma_ranges(host);
1083     if (err)
1084         return 0;
1085 
1086     /* Failure to get a link might just be that no cards are inserted */
1087     err = host->phy_init_fn(host);
1088     if (err) {
1089         dev_info(dev, "PCIe link down\n");
1090         return 0;
1091     }
1092 
1093     data = rcar_pci_read_reg(pcie, MACSR);
1094     dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1095 
1096     /* Enable MSI */
1097     if (IS_ENABLED(CONFIG_PCI_MSI)) {
1098         struct resource res;
1099         u32 val;
1100 
1101         of_address_to_resource(dev->of_node, 0, &res);
1102         rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
1103         rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
1104 
1105         bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
1106         rcar_pci_write_reg(pcie, val, PCIEMSIIER);
1107     }
1108 
1109     rcar_pcie_hw_enable(host);
1110 
1111     return 0;
1112 }
1113 
1114 static int rcar_pcie_resume_noirq(struct device *dev)
1115 {
1116     struct rcar_pcie_host *host = dev_get_drvdata(dev);
1117     struct rcar_pcie *pcie = &host->pcie;
1118 
1119     if (rcar_pci_read_reg(pcie, PMSR) &&
1120         !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1121         return 0;
1122 
1123     /* Re-establish the PCIe link */
1124     rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1125     rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1126     return rcar_pcie_wait_for_dl(pcie);
1127 }
1128 
1129 static const struct dev_pm_ops rcar_pcie_pm_ops = {
1130     SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume)
1131     .resume_noirq = rcar_pcie_resume_noirq,
1132 };
1133 
1134 static struct platform_driver rcar_pcie_driver = {
1135     .driver = {
1136         .name = "rcar-pcie",
1137         .of_match_table = rcar_pcie_of_match,
1138         .pm = &rcar_pcie_pm_ops,
1139         .suppress_bind_attrs = true,
1140     },
1141     .probe = rcar_pcie_probe,
1142 };
1143 
1144 #ifdef CONFIG_ARM
1145 static int rcar_pcie_aarch32_abort_handler(unsigned long addr,
1146         unsigned int fsr, struct pt_regs *regs)
1147 {
1148     return !fixup_exception(regs);
1149 }
1150 
1151 static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = {
1152     { .compatible = "renesas,pcie-r8a7779" },
1153     { .compatible = "renesas,pcie-r8a7790" },
1154     { .compatible = "renesas,pcie-r8a7791" },
1155     { .compatible = "renesas,pcie-rcar-gen2" },
1156     {},
1157 };
1158 
1159 static int __init rcar_pcie_init(void)
1160 {
1161     if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) {
1162 #ifdef CONFIG_ARM_LPAE
1163         hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1164                 "asynchronous external abort");
1165 #else
1166         hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
1167                 "imprecise external abort");
1168 #endif
1169     }
1170 
1171     return platform_driver_register(&rcar_pcie_driver);
1172 }
1173 device_initcall(rcar_pcie_init);
1174 #else
1175 builtin_platform_driver(rcar_pcie_driver);
1176 #endif
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