pci/controller/pcie-rcar-ep.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe endpoint driver for Renesas R-Car SoCs
0004  *  Copyright (c) 2020 Renesas Electronics Europe GmbH
0005  *
0006  * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
0007  */
0008
0009 #include <linux/delay.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_platform.h>
0012 #include <linux/pci.h>
0013 #include <linux/pci-epc.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016
0017 #include "pcie-rcar.h"
0018
0019 #define RCAR_EPC_MAX_FUNCTIONS      1
0020
0021 /* Structure representing the PCIe interface */
0022 struct rcar_pcie_endpoint {
0023     struct rcar_pcie    pcie;
0024     phys_addr_t     *ob_mapped_addr;
0025     struct pci_epc_mem_window *ob_window;
0026     u8          max_functions;
0027     unsigned int        bar_to_atu[MAX_NR_INBOUND_MAPS];
0028     unsigned long       *ib_window_map;
0029     u32         num_ib_windows;
0030     u32         num_ob_windows;
0031 };
0032
0033 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie)
0034 {
0035     u32 val;
0036
0037     rcar_pci_write_reg(pcie, 0, PCIETCTLR);
0038
0039     /* Set endpoint mode */
0040     rcar_pci_write_reg(pcie, 0, PCIEMSR);
0041
0042     /* Initialize default capabilities. */
0043     rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
0044     rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
0045            PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4);
0046     rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
0047            PCI_HEADER_TYPE_NORMAL);
0048
0049     /* Write out the physical slot number = 0 */
0050     rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
0051
0052     val = rcar_pci_read_reg(pcie, EXPCAP(1));
0053     /* device supports fixed 128 bytes MPSS */
0054     val &= ~GENMASK(2, 0);
0055     rcar_pci_write_reg(pcie, val, EXPCAP(1));
0056
0057     val = rcar_pci_read_reg(pcie, EXPCAP(2));
0058     /* read requests size 128 bytes */
0059     val &= ~GENMASK(14, 12);
0060     /* payload size 128 bytes */
0061     val &= ~GENMASK(7, 5);
0062     rcar_pci_write_reg(pcie, val, EXPCAP(2));
0063
0064     /* Set target link speed to 5.0 GT/s */
0065     rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
0066            PCI_EXP_LNKSTA_CLS_5_0GB);
0067
0068     /* Set the completion timer timeout to the maximum 50ms. */
0069     rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
0070
0071     /* Terminate list of capabilities (Next Capability Offset=0) */
0072     rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
0073
0074     /* flush modifications */
0075     wmb();
0076 }
0077
0078 static int rcar_pcie_ep_get_window(struct rcar_pcie_endpoint *ep,
0079                    phys_addr_t addr)
0080 {
0081     int i;
0082
0083     for (i = 0; i < ep->num_ob_windows; i++)
0084         if (ep->ob_window[i].phys_base == addr)
0085             return i;
0086
0087     return -EINVAL;
0088 }
0089
0090 static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie_endpoint *ep,
0091                        struct platform_device *pdev)
0092 {
0093     struct rcar_pcie *pcie = &ep->pcie;
0094     char outbound_name[10];
0095     struct resource *res;
0096     unsigned int i = 0;
0097
0098     ep->num_ob_windows = 0;
0099     for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
0100         sprintf(outbound_name, "memory%u", i);
0101         res = platform_get_resource_byname(pdev,
0102                            IORESOURCE_MEM,
0103                            outbound_name);
0104         if (!res) {
0105             dev_err(pcie->dev, "missing outbound window %u\n", i);
0106             return -EINVAL;
0107         }
0108         if (!devm_request_mem_region(&pdev->dev, res->start,
0109                          resource_size(res),
0110                          outbound_name)) {
0111             dev_err(pcie->dev, "Cannot request memory region %s.\n",
0112                 outbound_name);
0113             return -EIO;
0114         }
0115
0116         ep->ob_window[i].phys_base = res->start;
0117         ep->ob_window[i].size = resource_size(res);
0118         /* controller doesn't support multiple allocation
0119          * from same window, so set page_size to window size
0120          */
0121         ep->ob_window[i].page_size = resource_size(res);
0122     }
0123     ep->num_ob_windows = i;
0124
0125     return 0;
0126 }
0127
0128 static int rcar_pcie_ep_get_pdata(struct rcar_pcie_endpoint *ep,
0129                   struct platform_device *pdev)
0130 {
0131     struct rcar_pcie *pcie = &ep->pcie;
0132     struct pci_epc_mem_window *window;
0133     struct device *dev = pcie->dev;
0134     struct resource res;
0135     int err;
0136
0137     err = of_address_to_resource(dev->of_node, 0, &res);
0138     if (err)
0139         return err;
0140     pcie->base = devm_ioremap_resource(dev, &res);
0141     if (IS_ERR(pcie->base))
0142         return PTR_ERR(pcie->base);
0143
0144     ep->ob_window = devm_kcalloc(dev, RCAR_PCI_MAX_RESOURCES,
0145                      sizeof(*window), GFP_KERNEL);
0146     if (!ep->ob_window)
0147         return -ENOMEM;
0148
0149     rcar_pcie_parse_outbound_ranges(ep, pdev);
0150
0151     err = of_property_read_u8(dev->of_node, "max-functions",
0152                   &ep->max_functions);
0153     if (err < 0 || ep->max_functions > RCAR_EPC_MAX_FUNCTIONS)
0154         ep->max_functions = RCAR_EPC_MAX_FUNCTIONS;
0155
0156     return 0;
0157 }
0158
0159 static int rcar_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
0160                      struct pci_epf_header *hdr)
0161 {
0162     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0163     struct rcar_pcie *pcie = &ep->pcie;
0164     u32 val;
0165
0166     if (!fn)
0167         val = hdr->vendorid;
0168     else
0169         val = rcar_pci_read_reg(pcie, IDSETR0);
0170     val |= hdr->deviceid << 16;
0171     rcar_pci_write_reg(pcie, val, IDSETR0);
0172
0173     val = hdr->revid;
0174     val |= hdr->progif_code << 8;
0175     val |= hdr->subclass_code << 16;
0176     val |= hdr->baseclass_code << 24;
0177     rcar_pci_write_reg(pcie, val, IDSETR1);
0178
0179     if (!fn)
0180         val = hdr->subsys_vendor_id;
0181     else
0182         val = rcar_pci_read_reg(pcie, SUBIDSETR);
0183     val |= hdr->subsys_id << 16;
0184     rcar_pci_write_reg(pcie, val, SUBIDSETR);
0185
0186     if (hdr->interrupt_pin > PCI_INTERRUPT_INTA)
0187         return -EINVAL;
0188     val = rcar_pci_read_reg(pcie, PCICONF(15));
0189     val |= (hdr->interrupt_pin << 8);
0190     rcar_pci_write_reg(pcie, val, PCICONF(15));
0191
0192     return 0;
0193 }
0194
0195 static int rcar_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
0196                 struct pci_epf_bar *epf_bar)
0197 {
0198     int flags = epf_bar->flags | LAR_ENABLE | LAM_64BIT;
0199     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0200     u64 size = 1ULL << fls64(epf_bar->size - 1);
0201     dma_addr_t cpu_addr = epf_bar->phys_addr;
0202     enum pci_barno bar = epf_bar->barno;
0203     struct rcar_pcie *pcie = &ep->pcie;
0204     u32 mask;
0205     int idx;
0206     int err;
0207
0208     idx = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
0209     if (idx >= ep->num_ib_windows) {
0210         dev_err(pcie->dev, "no free inbound window\n");
0211         return -EINVAL;
0212     }
0213
0214     if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
0215         flags |= IO_SPACE;
0216
0217     ep->bar_to_atu[bar] = idx;
0218     /* use 64-bit BARs */
0219     set_bit(idx, ep->ib_window_map);
0220     set_bit(idx + 1, ep->ib_window_map);
0221
0222     if (cpu_addr > 0) {
0223         unsigned long nr_zeros = __ffs64(cpu_addr);
0224         u64 alignment = 1ULL << nr_zeros;
0225
0226         size = min(size, alignment);
0227     }
0228
0229     size = min(size, 1ULL << 32);
0230
0231     mask = roundup_pow_of_two(size) - 1;
0232     mask &= ~0xf;
0233
0234     rcar_pcie_set_inbound(pcie, cpu_addr,
0235                   0x0, mask | flags, idx, false);
0236
0237     err = rcar_pcie_wait_for_phyrdy(pcie);
0238     if (err) {
0239         dev_err(pcie->dev, "phy not ready\n");
0240         return -EINVAL;
0241     }
0242
0243     return 0;
0244 }
0245
0246 static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
0247                    struct pci_epf_bar *epf_bar)
0248 {
0249     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0250     enum pci_barno bar = epf_bar->barno;
0251     u32 atu_index = ep->bar_to_atu[bar];
0252
0253     rcar_pcie_set_inbound(&ep->pcie, 0x0, 0x0, 0x0, bar, false);
0254
0255     clear_bit(atu_index, ep->ib_window_map);
0256     clear_bit(atu_index + 1, ep->ib_window_map);
0257 }
0258
0259 static int rcar_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
0260                 u8 interrupts)
0261 {
0262     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0263     struct rcar_pcie *pcie = &ep->pcie;
0264     u32 flags;
0265
0266     flags = rcar_pci_read_reg(pcie, MSICAP(fn));
0267     flags |= interrupts << MSICAP0_MMESCAP_OFFSET;
0268     rcar_pci_write_reg(pcie, flags, MSICAP(fn));
0269
0270     return 0;
0271 }
0272
0273 static int rcar_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
0274 {
0275     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0276     struct rcar_pcie *pcie = &ep->pcie;
0277     u32 flags;
0278
0279     flags = rcar_pci_read_reg(pcie, MSICAP(fn));
0280     if (!(flags & MSICAP0_MSIE))
0281         return -EINVAL;
0282
0283     return ((flags & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
0284 }
0285
0286 static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
0287                  phys_addr_t addr, u64 pci_addr, size_t size)
0288 {
0289     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0290     struct rcar_pcie *pcie = &ep->pcie;
0291     struct resource_entry win;
0292     struct resource res;
0293     int window;
0294     int err;
0295
0296     /* check if we have a link. */
0297     err = rcar_pcie_wait_for_dl(pcie);
0298     if (err) {
0299         dev_err(pcie->dev, "link not up\n");
0300         return err;
0301     }
0302
0303     window = rcar_pcie_ep_get_window(ep, addr);
0304     if (window < 0) {
0305         dev_err(pcie->dev, "failed to get corresponding window\n");
0306         return -EINVAL;
0307     }
0308
0309     memset(&win, 0x0, sizeof(win));
0310     memset(&res, 0x0, sizeof(res));
0311     res.start = pci_addr;
0312     res.end = pci_addr + size - 1;
0313     res.flags = IORESOURCE_MEM;
0314     win.res = &res;
0315
0316     rcar_pcie_set_outbound(pcie, window, &win);
0317
0318     ep->ob_mapped_addr[window] = addr;
0319
0320     return 0;
0321 }
0322
0323 static void rcar_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
0324                     phys_addr_t addr)
0325 {
0326     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0327     struct resource_entry win;
0328     struct resource res;
0329     int idx;
0330
0331     for (idx = 0; idx < ep->num_ob_windows; idx++)
0332         if (ep->ob_mapped_addr[idx] == addr)
0333             break;
0334
0335     if (idx >= ep->num_ob_windows)
0336         return;
0337
0338     memset(&win, 0x0, sizeof(win));
0339     memset(&res, 0x0, sizeof(res));
0340     win.res = &res;
0341     rcar_pcie_set_outbound(&ep->pcie, idx, &win);
0342
0343     ep->ob_mapped_addr[idx] = 0;
0344 }
0345
0346 static int rcar_pcie_ep_assert_intx(struct rcar_pcie_endpoint *ep,
0347                     u8 fn, u8 intx)
0348 {
0349     struct rcar_pcie *pcie = &ep->pcie;
0350     u32 val;
0351
0352     val = rcar_pci_read_reg(pcie, PCIEMSITXR);
0353     if ((val & PCI_MSI_FLAGS_ENABLE)) {
0354         dev_err(pcie->dev, "MSI is enabled, cannot assert INTx\n");
0355         return -EINVAL;
0356     }
0357
0358     val = rcar_pci_read_reg(pcie, PCICONF(1));
0359     if ((val & INTDIS)) {
0360         dev_err(pcie->dev, "INTx message transmission is disabled\n");
0361         return -EINVAL;
0362     }
0363
0364     val = rcar_pci_read_reg(pcie, PCIEINTXR);
0365     if ((val & ASTINTX)) {
0366         dev_err(pcie->dev, "INTx is already asserted\n");
0367         return -EINVAL;
0368     }
0369
0370     val |= ASTINTX;
0371     rcar_pci_write_reg(pcie, val, PCIEINTXR);
0372     usleep_range(1000, 1001);
0373     val = rcar_pci_read_reg(pcie, PCIEINTXR);
0374     val &= ~ASTINTX;
0375     rcar_pci_write_reg(pcie, val, PCIEINTXR);
0376
0377     return 0;
0378 }
0379
0380 static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
0381                    u8 fn, u8 interrupt_num)
0382 {
0383     u16 msi_count;
0384     u32 val;
0385
0386     /* Check MSI enable bit */
0387     val = rcar_pci_read_reg(pcie, MSICAP(fn));
0388     if (!(val & MSICAP0_MSIE))
0389         return -EINVAL;
0390
0391     /* Get MSI numbers from MME */
0392     msi_count = ((val & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
0393     msi_count = 1 << msi_count;
0394
0395     if (!interrupt_num || interrupt_num > msi_count)
0396         return -EINVAL;
0397
0398     val = rcar_pci_read_reg(pcie, PCIEMSITXR);
0399     rcar_pci_write_reg(pcie, val | (interrupt_num - 1), PCIEMSITXR);
0400
0401     return 0;
0402 }
0403
0404 static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
0405                   enum pci_epc_irq_type type,
0406                   u16 interrupt_num)
0407 {
0408     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0409
0410     switch (type) {
0411     case PCI_EPC_IRQ_LEGACY:
0412         return rcar_pcie_ep_assert_intx(ep, fn, 0);
0413
0414     case PCI_EPC_IRQ_MSI:
0415         return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
0416
0417     default:
0418         return -EINVAL;
0419     }
0420 }
0421
0422 static int rcar_pcie_ep_start(struct pci_epc *epc)
0423 {
0424     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0425
0426     rcar_pci_write_reg(&ep->pcie, MACCTLR_INIT_VAL, MACCTLR);
0427     rcar_pci_write_reg(&ep->pcie, CFINIT, PCIETCTLR);
0428
0429     return 0;
0430 }
0431
0432 static void rcar_pcie_ep_stop(struct pci_epc *epc)
0433 {
0434     struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
0435
0436     rcar_pci_write_reg(&ep->pcie, 0, PCIETCTLR);
0437 }
0438
0439 static const struct pci_epc_features rcar_pcie_epc_features = {
0440     .linkup_notifier = false,
0441     .msi_capable = true,
0442     .msix_capable = false,
0443     /* use 64-bit BARs so mark BAR[1,3,5] as reserved */
0444     .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
0445     .bar_fixed_64bit = 1 << BAR_0 | 1 << BAR_2 | 1 << BAR_4,
0446     .bar_fixed_size[0] = 128,
0447     .bar_fixed_size[2] = 256,
0448     .bar_fixed_size[4] = 256,
0449 };
0450
0451 static const struct pci_epc_features*
0452 rcar_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
0453 {
0454     return &rcar_pcie_epc_features;
0455 }
0456
0457 static const struct pci_epc_ops rcar_pcie_epc_ops = {
0458     .write_header   = rcar_pcie_ep_write_header,
0459     .set_bar    = rcar_pcie_ep_set_bar,
0460     .clear_bar  = rcar_pcie_ep_clear_bar,
0461     .set_msi    = rcar_pcie_ep_set_msi,
0462     .get_msi    = rcar_pcie_ep_get_msi,
0463     .map_addr   = rcar_pcie_ep_map_addr,
0464     .unmap_addr = rcar_pcie_ep_unmap_addr,
0465     .raise_irq  = rcar_pcie_ep_raise_irq,
0466     .start      = rcar_pcie_ep_start,
0467     .stop       = rcar_pcie_ep_stop,
0468     .get_features   = rcar_pcie_ep_get_features,
0469 };
0470
0471 static const struct of_device_id rcar_pcie_ep_of_match[] = {
0472     { .compatible = "renesas,r8a774c0-pcie-ep", },
0473     { .compatible = "renesas,rcar-gen3-pcie-ep" },
0474     { },
0475 };
0476
0477 static int rcar_pcie_ep_probe(struct platform_device *pdev)
0478 {
0479     struct device *dev = &pdev->dev;
0480     struct rcar_pcie_endpoint *ep;
0481     struct rcar_pcie *pcie;
0482     struct pci_epc *epc;
0483     int err;
0484
0485     ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
0486     if (!ep)
0487         return -ENOMEM;
0488
0489     pcie = &ep->pcie;
0490     pcie->dev = dev;
0491
0492     pm_runtime_enable(dev);
0493     err = pm_runtime_resume_and_get(dev);
0494     if (err < 0) {
0495         dev_err(dev, "pm_runtime_resume_and_get failed\n");
0496         goto err_pm_disable;
0497     }
0498
0499     err = rcar_pcie_ep_get_pdata(ep, pdev);
0500     if (err < 0) {
0501         dev_err(dev, "failed to request resources: %d\n", err);
0502         goto err_pm_put;
0503     }
0504
0505     ep->num_ib_windows = MAX_NR_INBOUND_MAPS;
0506     ep->ib_window_map =
0507             devm_kcalloc(dev, BITS_TO_LONGS(ep->num_ib_windows),
0508                      sizeof(long), GFP_KERNEL);
0509     if (!ep->ib_window_map) {
0510         err = -ENOMEM;
0511         dev_err(dev, "failed to allocate memory for inbound map\n");
0512         goto err_pm_put;
0513     }
0514
0515     ep->ob_mapped_addr = devm_kcalloc(dev, ep->num_ob_windows,
0516                       sizeof(*ep->ob_mapped_addr),
0517                       GFP_KERNEL);
0518     if (!ep->ob_mapped_addr) {
0519         err = -ENOMEM;
0520         dev_err(dev, "failed to allocate memory for outbound memory pointers\n");
0521         goto err_pm_put;
0522     }
0523
0524     epc = devm_pci_epc_create(dev, &rcar_pcie_epc_ops);
0525     if (IS_ERR(epc)) {
0526         dev_err(dev, "failed to create epc device\n");
0527         err = PTR_ERR(epc);
0528         goto err_pm_put;
0529     }
0530
0531     epc->max_functions = ep->max_functions;
0532     epc_set_drvdata(epc, ep);
0533
0534     rcar_pcie_ep_hw_init(pcie);
0535
0536     err = pci_epc_multi_mem_init(epc, ep->ob_window, ep->num_ob_windows);
0537     if (err < 0) {
0538         dev_err(dev, "failed to initialize the epc memory space\n");
0539         goto err_pm_put;
0540     }
0541
0542     return 0;
0543
0544 err_pm_put:
0545     pm_runtime_put(dev);
0546
0547 err_pm_disable:
0548     pm_runtime_disable(dev);
0549
0550     return err;
0551 }
0552
0553 static struct platform_driver rcar_pcie_ep_driver = {
0554     .driver = {
0555         .name = "rcar-pcie-ep",
0556         .of_match_table = rcar_pcie_ep_of_match,
0557         .suppress_bind_attrs = true,
0558     },
0559     .probe = rcar_pcie_ep_probe,
0560 };
0561 builtin_platform_driver(rcar_pcie_ep_driver);