pci/controller/pcie-mt7621.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * BRIEF MODULE DESCRIPTION
0004  *     PCI init for Ralink RT2880 solution
0005  *
0006  * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
0007  *
0008  * May 2007 Bruce Chang
0009  * Initial Release
0010  *
0011  * May 2009 Bruce Chang
0012  * support RT2880/RT3883 PCIe
0013  *
0014  * May 2011 Bruce Chang
0015  * support RT6855/MT7620 PCIe
0016  */
0017
0018 #include <linux/bitops.h>
0019 #include <linux/clk.h>
0020 #include <linux/delay.h>
0021 #include <linux/gpio/consumer.h>
0022 #include <linux/module.h>
0023 #include <linux/of.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of_pci.h>
0026 #include <linux/of_platform.h>
0027 #include <linux/pci.h>
0028 #include <linux/phy/phy.h>
0029 #include <linux/platform_device.h>
0030 #include <linux/reset.h>
0031 #include <linux/sys_soc.h>
0032
0033 /* MediaTek-specific configuration registers */
0034 #define PCIE_FTS_NUM            0x70c
0035 #define PCIE_FTS_NUM_MASK       GENMASK(15, 8)
0036 #define PCIE_FTS_NUM_L0(x)      (((x) & 0xff) << 8)
0037
0038 /* Host-PCI bridge registers */
0039 #define RALINK_PCI_PCICFG_ADDR      0x0000
0040 #define RALINK_PCI_PCIMSK_ADDR      0x000c
0041 #define RALINK_PCI_CONFIG_ADDR      0x0020
0042 #define RALINK_PCI_CONFIG_DATA      0x0024
0043 #define RALINK_PCI_MEMBASE      0x0028
0044 #define RALINK_PCI_IOBASE       0x002c
0045
0046 /* PCIe RC control registers */
0047 #define RALINK_PCI_ID           0x0030
0048 #define RALINK_PCI_CLASS        0x0034
0049 #define RALINK_PCI_SUBID        0x0038
0050 #define RALINK_PCI_STATUS       0x0050
0051
0052 /* Some definition values */
0053 #define PCIE_REVISION_ID        BIT(0)
0054 #define PCIE_CLASS_CODE         (0x60400 << 8)
0055 #define PCIE_BAR_MAP_MAX        GENMASK(30, 16)
0056 #define PCIE_BAR_ENABLE         BIT(0)
0057 #define PCIE_PORT_INT_EN(x)     BIT(20 + (x))
0058 #define PCIE_PORT_LINKUP        BIT(0)
0059 #define PCIE_PORT_CNT           3
0060
0061 #define PERST_DELAY_MS          100
0062
0063 /**
0064  * struct mt7621_pcie_port - PCIe port information
0065  * @base: I/O mapped register base
0066  * @list: port list
0067  * @pcie: pointer to PCIe host info
0068  * @clk: pointer to the port clock gate
0069  * @phy: pointer to PHY control block
0070  * @pcie_rst: pointer to port reset control
0071  * @gpio_rst: gpio reset
0072  * @slot: port slot
0073  * @enabled: indicates if port is enabled
0074  */
0075 struct mt7621_pcie_port {
0076     void __iomem *base;
0077     struct list_head list;
0078     struct mt7621_pcie *pcie;
0079     struct clk *clk;
0080     struct phy *phy;
0081     struct reset_control *pcie_rst;
0082     struct gpio_desc *gpio_rst;
0083     u32 slot;
0084     bool enabled;
0085 };
0086
0087 /**
0088  * struct mt7621_pcie - PCIe host information
0089  * @base: IO Mapped Register Base
0090  * @dev: Pointer to PCIe device
0091  * @ports: pointer to PCIe port information
0092  * @resets_inverted: depends on chip revision
0093  * reset lines are inverted.
0094  */
0095 struct mt7621_pcie {
0096     struct device *dev;
0097     void __iomem *base;
0098     struct list_head ports;
0099     bool resets_inverted;
0100 };
0101
0102 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
0103 {
0104     return readl_relaxed(pcie->base + reg);
0105 }
0106
0107 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
0108 {
0109     writel_relaxed(val, pcie->base + reg);
0110 }
0111
0112 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
0113 {
0114     return readl_relaxed(port->base + reg);
0115 }
0116
0117 static inline void pcie_port_write(struct mt7621_pcie_port *port,
0118                    u32 val, u32 reg)
0119 {
0120     writel_relaxed(val, port->base + reg);
0121 }
0122
0123 static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
0124                      unsigned int func, unsigned int where)
0125 {
0126     return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
0127         (func << 8) | (where & 0xfc) | 0x80000000;
0128 }
0129
0130 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
0131                      unsigned int devfn, int where)
0132 {
0133     struct mt7621_pcie *pcie = bus->sysdata;
0134     u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
0135                          PCI_FUNC(devfn), where);
0136
0137     writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
0138
0139     return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
0140 }
0141
0142 static struct pci_ops mt7621_pcie_ops = {
0143     .map_bus    = mt7621_pcie_map_bus,
0144     .read       = pci_generic_config_read,
0145     .write      = pci_generic_config_write,
0146 };
0147
0148 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
0149 {
0150     u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
0151
0152     pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
0153     return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
0154 }
0155
0156 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
0157              u32 reg, u32 val)
0158 {
0159     u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
0160
0161     pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
0162     pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
0163 }
0164
0165 static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
0166 {
0167     if (port->gpio_rst)
0168         gpiod_set_value(port->gpio_rst, 1);
0169 }
0170
0171 static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
0172 {
0173     if (port->gpio_rst)
0174         gpiod_set_value(port->gpio_rst, 0);
0175 }
0176
0177 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
0178 {
0179     return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
0180 }
0181
0182 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
0183 {
0184     struct mt7621_pcie *pcie = port->pcie;
0185
0186     if (pcie->resets_inverted)
0187         reset_control_assert(port->pcie_rst);
0188     else
0189         reset_control_deassert(port->pcie_rst);
0190 }
0191
0192 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
0193 {
0194     struct mt7621_pcie *pcie = port->pcie;
0195
0196     if (pcie->resets_inverted)
0197         reset_control_deassert(port->pcie_rst);
0198     else
0199         reset_control_assert(port->pcie_rst);
0200 }
0201
0202 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
0203                   struct device_node *node,
0204                   int slot)
0205 {
0206     struct mt7621_pcie_port *port;
0207     struct device *dev = pcie->dev;
0208     struct platform_device *pdev = to_platform_device(dev);
0209     char name[10];
0210     int err;
0211
0212     port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
0213     if (!port)
0214         return -ENOMEM;
0215
0216     port->base = devm_platform_ioremap_resource(pdev, slot + 1);
0217     if (IS_ERR(port->base))
0218         return PTR_ERR(port->base);
0219
0220     port->clk = devm_get_clk_from_child(dev, node, NULL);
0221     if (IS_ERR(port->clk)) {
0222         dev_err(dev, "failed to get pcie%d clock\n", slot);
0223         return PTR_ERR(port->clk);
0224     }
0225
0226     port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
0227     if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
0228         dev_err(dev, "failed to get pcie%d reset control\n", slot);
0229         return PTR_ERR(port->pcie_rst);
0230     }
0231
0232     snprintf(name, sizeof(name), "pcie-phy%d", slot);
0233     port->phy = devm_of_phy_get(dev, node, name);
0234     if (IS_ERR(port->phy)) {
0235         dev_err(dev, "failed to get pcie-phy%d\n", slot);
0236         err = PTR_ERR(port->phy);
0237         goto remove_reset;
0238     }
0239
0240     port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
0241                                GPIOD_OUT_LOW);
0242     if (IS_ERR(port->gpio_rst)) {
0243         dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
0244         err = PTR_ERR(port->gpio_rst);
0245         goto remove_reset;
0246     }
0247
0248     port->slot = slot;
0249     port->pcie = pcie;
0250
0251     INIT_LIST_HEAD(&port->list);
0252     list_add_tail(&port->list, &pcie->ports);
0253
0254     return 0;
0255
0256 remove_reset:
0257     reset_control_put(port->pcie_rst);
0258     return err;
0259 }
0260
0261 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
0262 {
0263     struct device *dev = pcie->dev;
0264     struct platform_device *pdev = to_platform_device(dev);
0265     struct device_node *node = dev->of_node, *child;
0266     int err;
0267
0268     pcie->base = devm_platform_ioremap_resource(pdev, 0);
0269     if (IS_ERR(pcie->base))
0270         return PTR_ERR(pcie->base);
0271
0272     for_each_available_child_of_node(node, child) {
0273         int slot;
0274
0275         err = of_pci_get_devfn(child);
0276         if (err < 0) {
0277             of_node_put(child);
0278             dev_err(dev, "failed to parse devfn: %d\n", err);
0279             return err;
0280         }
0281
0282         slot = PCI_SLOT(err);
0283
0284         err = mt7621_pcie_parse_port(pcie, child, slot);
0285         if (err) {
0286             of_node_put(child);
0287             return err;
0288         }
0289     }
0290
0291     return 0;
0292 }
0293
0294 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
0295 {
0296     struct mt7621_pcie *pcie = port->pcie;
0297     struct device *dev = pcie->dev;
0298     u32 slot = port->slot;
0299     int err;
0300
0301     err = phy_init(port->phy);
0302     if (err) {
0303         dev_err(dev, "failed to initialize port%d phy\n", slot);
0304         return err;
0305     }
0306
0307     err = phy_power_on(port->phy);
0308     if (err) {
0309         dev_err(dev, "failed to power on port%d phy\n", slot);
0310         phy_exit(port->phy);
0311         return err;
0312     }
0313
0314     port->enabled = true;
0315
0316     return 0;
0317 }
0318
0319 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
0320 {
0321     struct mt7621_pcie_port *port;
0322
0323     list_for_each_entry(port, &pcie->ports, list) {
0324         /* PCIe RC reset assert */
0325         mt7621_control_assert(port);
0326
0327         /* PCIe EP reset assert */
0328         mt7621_rst_gpio_pcie_assert(port);
0329     }
0330
0331     msleep(PERST_DELAY_MS);
0332 }
0333
0334 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
0335 {
0336     struct mt7621_pcie_port *port;
0337
0338     list_for_each_entry(port, &pcie->ports, list)
0339         mt7621_control_deassert(port);
0340 }
0341
0342 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
0343 {
0344     struct mt7621_pcie_port *port;
0345
0346     list_for_each_entry(port, &pcie->ports, list)
0347         mt7621_rst_gpio_pcie_deassert(port);
0348
0349     msleep(PERST_DELAY_MS);
0350 }
0351
0352 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
0353 {
0354     struct device *dev = pcie->dev;
0355     struct mt7621_pcie_port *port, *tmp;
0356     u8 num_disabled = 0;
0357     int err;
0358
0359     mt7621_pcie_reset_assert(pcie);
0360     mt7621_pcie_reset_rc_deassert(pcie);
0361
0362     list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
0363         u32 slot = port->slot;
0364
0365         if (slot == 1) {
0366             port->enabled = true;
0367             continue;
0368         }
0369
0370         err = mt7621_pcie_init_port(port);
0371         if (err) {
0372             dev_err(dev, "initializing port %d failed\n", slot);
0373             list_del(&port->list);
0374         }
0375     }
0376
0377     mt7621_pcie_reset_ep_deassert(pcie);
0378
0379     tmp = NULL;
0380     list_for_each_entry(port, &pcie->ports, list) {
0381         u32 slot = port->slot;
0382
0383         if (!mt7621_pcie_port_is_linkup(port)) {
0384             dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
0385                 slot);
0386             mt7621_control_assert(port);
0387             port->enabled = false;
0388             num_disabled++;
0389
0390             if (slot == 0) {
0391                 tmp = port;
0392                 continue;
0393             }
0394
0395             if (slot == 1 && tmp && !tmp->enabled)
0396                 phy_power_off(tmp->phy);
0397         }
0398     }
0399
0400     return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
0401 }
0402
0403 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
0404 {
0405     struct mt7621_pcie *pcie = port->pcie;
0406     u32 slot = port->slot;
0407     u32 val;
0408
0409     /* enable pcie interrupt */
0410     val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
0411     val |= PCIE_PORT_INT_EN(slot);
0412     pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
0413
0414     /* map 2G DDR region */
0415     pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
0416             PCI_BASE_ADDRESS_0);
0417
0418     /* configure class code and revision ID */
0419     pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
0420             RALINK_PCI_CLASS);
0421
0422     /* configure RC FTS number to 250 when it leaves L0s */
0423     val = read_config(pcie, slot, PCIE_FTS_NUM);
0424     val &= ~PCIE_FTS_NUM_MASK;
0425     val |= PCIE_FTS_NUM_L0(0x50);
0426     write_config(pcie, slot, PCIE_FTS_NUM, val);
0427 }
0428
0429 static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
0430 {
0431     struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
0432     struct device *dev = pcie->dev;
0433     struct mt7621_pcie_port *port;
0434     struct resource_entry *entry;
0435     int err;
0436
0437     entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
0438     if (!entry) {
0439         dev_err(dev, "cannot get io resource\n");
0440         return -EINVAL;
0441     }
0442
0443     /* Setup MEMWIN and IOWIN */
0444     pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
0445     pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
0446
0447     list_for_each_entry(port, &pcie->ports, list) {
0448         if (port->enabled) {
0449             err = clk_prepare_enable(port->clk);
0450             if (err) {
0451                 dev_err(dev, "enabling clk pcie%d\n",
0452                     port->slot);
0453                 return err;
0454             }
0455
0456             mt7621_pcie_enable_port(port);
0457             dev_info(dev, "PCIE%d enabled\n", port->slot);
0458         }
0459     }
0460
0461     return 0;
0462 }
0463
0464 static int mt7621_pcie_register_host(struct pci_host_bridge *host)
0465 {
0466     struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
0467
0468     host->ops = &mt7621_pcie_ops;
0469     host->sysdata = pcie;
0470     return pci_host_probe(host);
0471 }
0472
0473 static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
0474     { .soc_id = "mt7621", .revision = "E2" }
0475 };
0476
0477 static int mt7621_pcie_probe(struct platform_device *pdev)
0478 {
0479     struct device *dev = &pdev->dev;
0480     const struct soc_device_attribute *attr;
0481     struct mt7621_pcie_port *port;
0482     struct mt7621_pcie *pcie;
0483     struct pci_host_bridge *bridge;
0484     int err;
0485
0486     if (!dev->of_node)
0487         return -ENODEV;
0488
0489     bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
0490     if (!bridge)
0491         return -ENOMEM;
0492
0493     pcie = pci_host_bridge_priv(bridge);
0494     pcie->dev = dev;
0495     platform_set_drvdata(pdev, pcie);
0496     INIT_LIST_HEAD(&pcie->ports);
0497
0498     attr = soc_device_match(mt7621_pcie_quirks_match);
0499     if (attr)
0500         pcie->resets_inverted = true;
0501
0502     err = mt7621_pcie_parse_dt(pcie);
0503     if (err) {
0504         dev_err(dev, "parsing DT failed\n");
0505         return err;
0506     }
0507
0508     err = mt7621_pcie_init_ports(pcie);
0509     if (err) {
0510         dev_err(dev, "nothing connected in virtual bridges\n");
0511         return 0;
0512     }
0513
0514     err = mt7621_pcie_enable_ports(bridge);
0515     if (err) {
0516         dev_err(dev, "error enabling pcie ports\n");
0517         goto remove_resets;
0518     }
0519
0520     return mt7621_pcie_register_host(bridge);
0521
0522 remove_resets:
0523     list_for_each_entry(port, &pcie->ports, list)
0524         reset_control_put(port->pcie_rst);
0525
0526     return err;
0527 }
0528
0529 static int mt7621_pcie_remove(struct platform_device *pdev)
0530 {
0531     struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
0532     struct mt7621_pcie_port *port;
0533
0534     list_for_each_entry(port, &pcie->ports, list)
0535         reset_control_put(port->pcie_rst);
0536
0537     return 0;
0538 }
0539
0540 static const struct of_device_id mt7621_pcie_ids[] = {
0541     { .compatible = "mediatek,mt7621-pci" },
0542     {},
0543 };
0544 MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
0545
0546 static struct platform_driver mt7621_pcie_driver = {
0547     .probe = mt7621_pcie_probe,
0548     .remove = mt7621_pcie_remove,
0549     .driver = {
0550         .name = "mt7621-pci",
0551         .of_match_table = mt7621_pcie_ids,
0552     },
0553 };
0554 builtin_platform_driver(mt7621_pcie_driver);
0555
0556 MODULE_LICENSE("GPL v2");