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0010 #include <linux/clk.h>
0011 #include <linux/irqchip/chained_irq.h>
0012 #include <linux/module.h>
0013 #include <linux/msi.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/of_pci.h>
0017 #include <linux/pci-ecam.h>
0018 #include <linux/platform_device.h>
0019
0020 #include "../pci.h"
0021
0022
0023 #define MC_NUM_MSI_IRQS 32
0024 #define MC_NUM_MSI_IRQS_CODED 5
0025
0026
0027 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u
0028 #define MC_PCIE1_CTRL_ADDR 0x0000a000u
0029
0030 #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
0031 #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
0032
0033
0034 #define SEC_ERROR_CNT 0x20
0035 #define DED_ERROR_CNT 0x24
0036 #define SEC_ERROR_INT 0x28
0037 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0)
0038 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4)
0039 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8)
0040 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12)
0041 #define NUM_SEC_ERROR_INTS (4)
0042 #define SEC_ERROR_INT_MASK 0x2c
0043 #define DED_ERROR_INT 0x30
0044 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0)
0045 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4)
0046 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8)
0047 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12)
0048 #define NUM_DED_ERROR_INTS (4)
0049 #define DED_ERROR_INT_MASK 0x34
0050 #define ECC_CONTROL 0x38
0051 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0)
0052 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1)
0053 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
0054 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3)
0055 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4)
0056 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5)
0057 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6)
0058 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7)
0059 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8)
0060 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9)
0061 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10)
0062 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11)
0063 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12)
0064 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13)
0065 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14)
0066 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15)
0067 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24)
0068 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25)
0069 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26)
0070 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27)
0071 #define LTSSM_STATE 0x5c
0072 #define LTSSM_L0_STATE 0x10
0073 #define PCIE_EVENT_INT 0x14c
0074 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0)
0075 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1)
0076 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
0077 #define PCIE_EVENT_INT_MASK GENMASK(2, 0)
0078 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16)
0079 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17)
0080 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18)
0081 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16)
0082 #define PCIE_EVENT_INT_ENB_SHIFT 16
0083 #define NUM_PCIE_EVENTS (3)
0084
0085
0086 #define PCIE_PCI_IDS_DW1 0x9c
0087
0088
0089 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u
0090 #define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1)
0091 #define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4)
0092
0093 #define IMASK_LOCAL 0x180
0094 #define DMA_END_ENGINE_0_MASK 0x00000000u
0095 #define DMA_END_ENGINE_0_SHIFT 0
0096 #define DMA_END_ENGINE_1_MASK 0x00000000u
0097 #define DMA_END_ENGINE_1_SHIFT 1
0098 #define DMA_ERROR_ENGINE_0_MASK 0x00000100u
0099 #define DMA_ERROR_ENGINE_0_SHIFT 8
0100 #define DMA_ERROR_ENGINE_1_MASK 0x00000200u
0101 #define DMA_ERROR_ENGINE_1_SHIFT 9
0102 #define A_ATR_EVT_POST_ERR_MASK 0x00010000u
0103 #define A_ATR_EVT_POST_ERR_SHIFT 16
0104 #define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u
0105 #define A_ATR_EVT_FETCH_ERR_SHIFT 17
0106 #define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u
0107 #define A_ATR_EVT_DISCARD_ERR_SHIFT 18
0108 #define A_ATR_EVT_DOORBELL_MASK 0x00000000u
0109 #define A_ATR_EVT_DOORBELL_SHIFT 19
0110 #define P_ATR_EVT_POST_ERR_MASK 0x00100000u
0111 #define P_ATR_EVT_POST_ERR_SHIFT 20
0112 #define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u
0113 #define P_ATR_EVT_FETCH_ERR_SHIFT 21
0114 #define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u
0115 #define P_ATR_EVT_DISCARD_ERR_SHIFT 22
0116 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u
0117 #define P_ATR_EVT_DOORBELL_SHIFT 23
0118 #define PM_MSI_INT_INTA_MASK 0x01000000u
0119 #define PM_MSI_INT_INTA_SHIFT 24
0120 #define PM_MSI_INT_INTB_MASK 0x02000000u
0121 #define PM_MSI_INT_INTB_SHIFT 25
0122 #define PM_MSI_INT_INTC_MASK 0x04000000u
0123 #define PM_MSI_INT_INTC_SHIFT 26
0124 #define PM_MSI_INT_INTD_MASK 0x08000000u
0125 #define PM_MSI_INT_INTD_SHIFT 27
0126 #define PM_MSI_INT_INTX_MASK 0x0f000000u
0127 #define PM_MSI_INT_INTX_SHIFT 24
0128 #define PM_MSI_INT_MSI_MASK 0x10000000u
0129 #define PM_MSI_INT_MSI_SHIFT 28
0130 #define PM_MSI_INT_AER_EVT_MASK 0x20000000u
0131 #define PM_MSI_INT_AER_EVT_SHIFT 29
0132 #define PM_MSI_INT_EVENTS_MASK 0x40000000u
0133 #define PM_MSI_INT_EVENTS_SHIFT 30
0134 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u
0135 #define PM_MSI_INT_SYS_ERR_SHIFT 31
0136 #define NUM_LOCAL_EVENTS 15
0137 #define ISTATUS_LOCAL 0x184
0138 #define IMASK_HOST 0x188
0139 #define ISTATUS_HOST 0x18c
0140 #define MSI_ADDR 0x190
0141 #define ISTATUS_MSI 0x194
0142
0143
0144 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u
0145 #define ATR0_PCIE_ATR_SIZE 0x25
0146 #define ATR0_PCIE_ATR_SIZE_SHIFT 1
0147 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604u
0148 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u
0149 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu
0150 #define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u
0151
0152
0153 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u
0154 #define ATR_SIZE_SHIFT 1
0155 #define ATR_IMPL_ENABLE 1
0156 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u
0157 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u
0158 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu
0159 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u
0160 #define PCIE_TX_RX_INTERFACE 0x00000000u
0161 #define PCIE_CONFIG_INTERFACE 0x00000001u
0162
0163 #define ATR_ENTRY_SIZE 32
0164
0165 #define EVENT_PCIE_L2_EXIT 0
0166 #define EVENT_PCIE_HOTRST_EXIT 1
0167 #define EVENT_PCIE_DLUP_EXIT 2
0168 #define EVENT_SEC_TX_RAM_SEC_ERR 3
0169 #define EVENT_SEC_RX_RAM_SEC_ERR 4
0170 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5
0171 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6
0172 #define EVENT_DED_TX_RAM_DED_ERR 7
0173 #define EVENT_DED_RX_RAM_DED_ERR 8
0174 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9
0175 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10
0176 #define EVENT_LOCAL_DMA_END_ENGINE_0 11
0177 #define EVENT_LOCAL_DMA_END_ENGINE_1 12
0178 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
0179 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14
0180 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15
0181 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16
0182 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17
0183 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18
0184 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19
0185 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20
0186 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21
0187 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22
0188 #define EVENT_LOCAL_PM_MSI_INT_INTX 23
0189 #define EVENT_LOCAL_PM_MSI_INT_MSI 24
0190 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25
0191 #define EVENT_LOCAL_PM_MSI_INT_EVENTS 26
0192 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27
0193 #define NUM_EVENTS 28
0194
0195 #define PCIE_EVENT_CAUSE(x, s) \
0196 [EVENT_PCIE_ ## x] = { __stringify(x), s }
0197
0198 #define SEC_ERROR_CAUSE(x, s) \
0199 [EVENT_SEC_ ## x] = { __stringify(x), s }
0200
0201 #define DED_ERROR_CAUSE(x, s) \
0202 [EVENT_DED_ ## x] = { __stringify(x), s }
0203
0204 #define LOCAL_EVENT_CAUSE(x, s) \
0205 [EVENT_LOCAL_ ## x] = { __stringify(x), s }
0206
0207 #define PCIE_EVENT(x) \
0208 .base = MC_PCIE_CTRL_ADDR, \
0209 .offset = PCIE_EVENT_INT, \
0210 .mask_offset = PCIE_EVENT_INT, \
0211 .mask_high = 1, \
0212 .mask = PCIE_EVENT_INT_ ## x ## _INT, \
0213 .enb_mask = PCIE_EVENT_INT_ENB_MASK
0214
0215 #define SEC_EVENT(x) \
0216 .base = MC_PCIE_CTRL_ADDR, \
0217 .offset = SEC_ERROR_INT, \
0218 .mask_offset = SEC_ERROR_INT_MASK, \
0219 .mask = SEC_ERROR_INT_ ## x ## _INT, \
0220 .mask_high = 1, \
0221 .enb_mask = 0
0222
0223 #define DED_EVENT(x) \
0224 .base = MC_PCIE_CTRL_ADDR, \
0225 .offset = DED_ERROR_INT, \
0226 .mask_offset = DED_ERROR_INT_MASK, \
0227 .mask_high = 1, \
0228 .mask = DED_ERROR_INT_ ## x ## _INT, \
0229 .enb_mask = 0
0230
0231 #define LOCAL_EVENT(x) \
0232 .base = MC_PCIE_BRIDGE_ADDR, \
0233 .offset = ISTATUS_LOCAL, \
0234 .mask_offset = IMASK_LOCAL, \
0235 .mask_high = 0, \
0236 .mask = x ## _MASK, \
0237 .enb_mask = 0
0238
0239 #define PCIE_EVENT_TO_EVENT_MAP(x) \
0240 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x }
0241
0242 #define SEC_ERROR_TO_EVENT_MAP(x) \
0243 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x }
0244
0245 #define DED_ERROR_TO_EVENT_MAP(x) \
0246 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x }
0247
0248 #define LOCAL_STATUS_TO_EVENT_MAP(x) \
0249 { x ## _MASK, EVENT_LOCAL_ ## x }
0250
0251 struct event_map {
0252 u32 reg_mask;
0253 u32 event_bit;
0254 };
0255
0256 struct mc_msi {
0257 struct mutex lock;
0258 struct irq_domain *msi_domain;
0259 struct irq_domain *dev_domain;
0260 u32 num_vectors;
0261 u64 vector_phy;
0262 DECLARE_BITMAP(used, MC_NUM_MSI_IRQS);
0263 };
0264
0265 struct mc_pcie {
0266 void __iomem *axi_base_addr;
0267 struct device *dev;
0268 struct irq_domain *intx_domain;
0269 struct irq_domain *event_domain;
0270 raw_spinlock_t lock;
0271 struct mc_msi msi;
0272 };
0273
0274 struct cause {
0275 const char *sym;
0276 const char *str;
0277 };
0278
0279 static const struct cause event_cause[NUM_EVENTS] = {
0280 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"),
0281 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"),
0282 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"),
0283 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"),
0284 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"),
0285 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"),
0286 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"),
0287 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"),
0288 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"),
0289 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"),
0290 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"),
0291 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
0292 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
0293 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"),
0294 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"),
0295 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"),
0296 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"),
0297 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"),
0298 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"),
0299 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"),
0300 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"),
0301 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"),
0302 };
0303
0304 static struct event_map pcie_event_to_event[] = {
0305 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT),
0306 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT),
0307 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT),
0308 };
0309
0310 static struct event_map sec_error_to_event[] = {
0311 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR),
0312 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR),
0313 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR),
0314 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR),
0315 };
0316
0317 static struct event_map ded_error_to_event[] = {
0318 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR),
0319 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR),
0320 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR),
0321 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR),
0322 };
0323
0324 static struct event_map local_status_to_event[] = {
0325 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0),
0326 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1),
0327 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0),
0328 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1),
0329 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR),
0330 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR),
0331 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR),
0332 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL),
0333 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR),
0334 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR),
0335 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR),
0336 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL),
0337 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX),
0338 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI),
0339 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT),
0340 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS),
0341 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR),
0342 };
0343
0344 static struct {
0345 u32 base;
0346 u32 offset;
0347 u32 mask;
0348 u32 shift;
0349 u32 enb_mask;
0350 u32 mask_high;
0351 u32 mask_offset;
0352 } event_descs[] = {
0353 { PCIE_EVENT(L2_EXIT) },
0354 { PCIE_EVENT(HOTRST_EXIT) },
0355 { PCIE_EVENT(DLUP_EXIT) },
0356 { SEC_EVENT(TX_RAM_SEC_ERR) },
0357 { SEC_EVENT(RX_RAM_SEC_ERR) },
0358 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) },
0359 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) },
0360 { DED_EVENT(TX_RAM_DED_ERR) },
0361 { DED_EVENT(RX_RAM_DED_ERR) },
0362 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) },
0363 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) },
0364 { LOCAL_EVENT(DMA_END_ENGINE_0) },
0365 { LOCAL_EVENT(DMA_END_ENGINE_1) },
0366 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) },
0367 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) },
0368 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) },
0369 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) },
0370 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) },
0371 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) },
0372 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) },
0373 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) },
0374 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) },
0375 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) },
0376 { LOCAL_EVENT(PM_MSI_INT_INTX) },
0377 { LOCAL_EVENT(PM_MSI_INT_MSI) },
0378 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) },
0379 { LOCAL_EVENT(PM_MSI_INT_EVENTS) },
0380 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) },
0381 };
0382
0383 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" };
0384
0385 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base)
0386 {
0387 struct mc_msi *msi = &port->msi;
0388 u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET;
0389 u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS);
0390
0391 msg_ctrl |= PCI_MSI_FLAGS_ENABLE;
0392 msg_ctrl &= ~PCI_MSI_FLAGS_QMASK;
0393 msg_ctrl |= MC_MSI_MAX_Q_AVAIL;
0394 msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE;
0395 msg_ctrl |= MC_MSI_Q_SIZE;
0396 msg_ctrl |= PCI_MSI_FLAGS_64BIT;
0397
0398 writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS);
0399
0400 writel_relaxed(lower_32_bits(msi->vector_phy),
0401 base + cap_offset + PCI_MSI_ADDRESS_LO);
0402 writel_relaxed(upper_32_bits(msi->vector_phy),
0403 base + cap_offset + PCI_MSI_ADDRESS_HI);
0404 }
0405
0406 static void mc_handle_msi(struct irq_desc *desc)
0407 {
0408 struct mc_pcie *port = irq_desc_get_handler_data(desc);
0409 struct irq_chip *chip = irq_desc_get_chip(desc);
0410 struct device *dev = port->dev;
0411 struct mc_msi *msi = &port->msi;
0412 void __iomem *bridge_base_addr =
0413 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0414 unsigned long status;
0415 u32 bit;
0416 int ret;
0417
0418 chained_irq_enter(chip, desc);
0419
0420 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
0421 if (status & PM_MSI_INT_MSI_MASK) {
0422 writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL);
0423 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI);
0424 for_each_set_bit(bit, &status, msi->num_vectors) {
0425 ret = generic_handle_domain_irq(msi->dev_domain, bit);
0426 if (ret)
0427 dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
0428 bit);
0429 }
0430 }
0431
0432 chained_irq_exit(chip, desc);
0433 }
0434
0435 static void mc_msi_bottom_irq_ack(struct irq_data *data)
0436 {
0437 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0438 void __iomem *bridge_base_addr =
0439 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0440 u32 bitpos = data->hwirq;
0441
0442 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
0443 }
0444
0445 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
0446 {
0447 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0448 phys_addr_t addr = port->msi.vector_phy;
0449
0450 msg->address_lo = lower_32_bits(addr);
0451 msg->address_hi = upper_32_bits(addr);
0452 msg->data = data->hwirq;
0453
0454 dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n",
0455 (int)data->hwirq, msg->address_hi, msg->address_lo);
0456 }
0457
0458 static int mc_msi_set_affinity(struct irq_data *irq_data,
0459 const struct cpumask *mask, bool force)
0460 {
0461 return -EINVAL;
0462 }
0463
0464 static struct irq_chip mc_msi_bottom_irq_chip = {
0465 .name = "Microchip MSI",
0466 .irq_ack = mc_msi_bottom_irq_ack,
0467 .irq_compose_msi_msg = mc_compose_msi_msg,
0468 .irq_set_affinity = mc_msi_set_affinity,
0469 };
0470
0471 static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
0472 unsigned int nr_irqs, void *args)
0473 {
0474 struct mc_pcie *port = domain->host_data;
0475 struct mc_msi *msi = &port->msi;
0476 void __iomem *bridge_base_addr =
0477 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0478 unsigned long bit;
0479 u32 val;
0480
0481 mutex_lock(&msi->lock);
0482 bit = find_first_zero_bit(msi->used, msi->num_vectors);
0483 if (bit >= msi->num_vectors) {
0484 mutex_unlock(&msi->lock);
0485 return -ENOSPC;
0486 }
0487
0488 set_bit(bit, msi->used);
0489
0490 irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip,
0491 domain->host_data, handle_edge_irq, NULL, NULL);
0492
0493
0494 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
0495 val |= PM_MSI_INT_MSI_MASK;
0496 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
0497
0498 mutex_unlock(&msi->lock);
0499
0500 return 0;
0501 }
0502
0503 static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq,
0504 unsigned int nr_irqs)
0505 {
0506 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
0507 struct mc_pcie *port = irq_data_get_irq_chip_data(d);
0508 struct mc_msi *msi = &port->msi;
0509
0510 mutex_lock(&msi->lock);
0511
0512 if (test_bit(d->hwirq, msi->used))
0513 __clear_bit(d->hwirq, msi->used);
0514 else
0515 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq);
0516
0517 mutex_unlock(&msi->lock);
0518 }
0519
0520 static const struct irq_domain_ops msi_domain_ops = {
0521 .alloc = mc_irq_msi_domain_alloc,
0522 .free = mc_irq_msi_domain_free,
0523 };
0524
0525 static struct irq_chip mc_msi_irq_chip = {
0526 .name = "Microchip PCIe MSI",
0527 .irq_ack = irq_chip_ack_parent,
0528 .irq_mask = pci_msi_mask_irq,
0529 .irq_unmask = pci_msi_unmask_irq,
0530 };
0531
0532 static struct msi_domain_info mc_msi_domain_info = {
0533 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
0534 MSI_FLAG_PCI_MSIX),
0535 .chip = &mc_msi_irq_chip,
0536 };
0537
0538 static int mc_allocate_msi_domains(struct mc_pcie *port)
0539 {
0540 struct device *dev = port->dev;
0541 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
0542 struct mc_msi *msi = &port->msi;
0543
0544 mutex_init(&port->msi.lock);
0545
0546 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors,
0547 &msi_domain_ops, port);
0548 if (!msi->dev_domain) {
0549 dev_err(dev, "failed to create IRQ domain\n");
0550 return -ENOMEM;
0551 }
0552
0553 msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info,
0554 msi->dev_domain);
0555 if (!msi->msi_domain) {
0556 dev_err(dev, "failed to create MSI domain\n");
0557 irq_domain_remove(msi->dev_domain);
0558 return -ENOMEM;
0559 }
0560
0561 return 0;
0562 }
0563
0564 static void mc_handle_intx(struct irq_desc *desc)
0565 {
0566 struct mc_pcie *port = irq_desc_get_handler_data(desc);
0567 struct irq_chip *chip = irq_desc_get_chip(desc);
0568 struct device *dev = port->dev;
0569 void __iomem *bridge_base_addr =
0570 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0571 unsigned long status;
0572 u32 bit;
0573 int ret;
0574
0575 chained_irq_enter(chip, desc);
0576
0577 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL);
0578 if (status & PM_MSI_INT_INTX_MASK) {
0579 status &= PM_MSI_INT_INTX_MASK;
0580 status >>= PM_MSI_INT_INTX_SHIFT;
0581 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
0582 ret = generic_handle_domain_irq(port->intx_domain, bit);
0583 if (ret)
0584 dev_err_ratelimited(dev, "bad INTx IRQ %d\n",
0585 bit);
0586 }
0587 }
0588
0589 chained_irq_exit(chip, desc);
0590 }
0591
0592 static void mc_ack_intx_irq(struct irq_data *data)
0593 {
0594 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0595 void __iomem *bridge_base_addr =
0596 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0597 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
0598
0599 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL);
0600 }
0601
0602 static void mc_mask_intx_irq(struct irq_data *data)
0603 {
0604 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0605 void __iomem *bridge_base_addr =
0606 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0607 unsigned long flags;
0608 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
0609 u32 val;
0610
0611 raw_spin_lock_irqsave(&port->lock, flags);
0612 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
0613 val &= ~mask;
0614 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
0615 raw_spin_unlock_irqrestore(&port->lock, flags);
0616 }
0617
0618 static void mc_unmask_intx_irq(struct irq_data *data)
0619 {
0620 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0621 void __iomem *bridge_base_addr =
0622 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0623 unsigned long flags;
0624 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
0625 u32 val;
0626
0627 raw_spin_lock_irqsave(&port->lock, flags);
0628 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
0629 val |= mask;
0630 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
0631 raw_spin_unlock_irqrestore(&port->lock, flags);
0632 }
0633
0634 static struct irq_chip mc_intx_irq_chip = {
0635 .name = "Microchip PCIe INTx",
0636 .irq_ack = mc_ack_intx_irq,
0637 .irq_mask = mc_mask_intx_irq,
0638 .irq_unmask = mc_unmask_intx_irq,
0639 };
0640
0641 static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
0642 irq_hw_number_t hwirq)
0643 {
0644 irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq);
0645 irq_set_chip_data(irq, domain->host_data);
0646
0647 return 0;
0648 }
0649
0650 static const struct irq_domain_ops intx_domain_ops = {
0651 .map = mc_pcie_intx_map,
0652 };
0653
0654 static inline u32 reg_to_event(u32 reg, struct event_map field)
0655 {
0656 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0;
0657 }
0658
0659 static u32 pcie_events(void __iomem *addr)
0660 {
0661 u32 reg = readl_relaxed(addr);
0662 u32 val = 0;
0663 int i;
0664
0665 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++)
0666 val |= reg_to_event(reg, pcie_event_to_event[i]);
0667
0668 return val;
0669 }
0670
0671 static u32 sec_errors(void __iomem *addr)
0672 {
0673 u32 reg = readl_relaxed(addr);
0674 u32 val = 0;
0675 int i;
0676
0677 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++)
0678 val |= reg_to_event(reg, sec_error_to_event[i]);
0679
0680 return val;
0681 }
0682
0683 static u32 ded_errors(void __iomem *addr)
0684 {
0685 u32 reg = readl_relaxed(addr);
0686 u32 val = 0;
0687 int i;
0688
0689 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++)
0690 val |= reg_to_event(reg, ded_error_to_event[i]);
0691
0692 return val;
0693 }
0694
0695 static u32 local_events(void __iomem *addr)
0696 {
0697 u32 reg = readl_relaxed(addr);
0698 u32 val = 0;
0699 int i;
0700
0701 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++)
0702 val |= reg_to_event(reg, local_status_to_event[i]);
0703
0704 return val;
0705 }
0706
0707 static u32 get_events(struct mc_pcie *port)
0708 {
0709 void __iomem *bridge_base_addr =
0710 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0711 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
0712 u32 events = 0;
0713
0714 events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT);
0715 events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT);
0716 events |= ded_errors(ctrl_base_addr + DED_ERROR_INT);
0717 events |= local_events(bridge_base_addr + ISTATUS_LOCAL);
0718
0719 return events;
0720 }
0721
0722 static irqreturn_t mc_event_handler(int irq, void *dev_id)
0723 {
0724 struct mc_pcie *port = dev_id;
0725 struct device *dev = port->dev;
0726 struct irq_data *data;
0727
0728 data = irq_domain_get_irq_data(port->event_domain, irq);
0729
0730 if (event_cause[data->hwirq].str)
0731 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str);
0732 else
0733 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq);
0734
0735 return IRQ_HANDLED;
0736 }
0737
0738 static void mc_handle_event(struct irq_desc *desc)
0739 {
0740 struct mc_pcie *port = irq_desc_get_handler_data(desc);
0741 unsigned long events;
0742 u32 bit;
0743 struct irq_chip *chip = irq_desc_get_chip(desc);
0744
0745 chained_irq_enter(chip, desc);
0746
0747 events = get_events(port);
0748
0749 for_each_set_bit(bit, &events, NUM_EVENTS)
0750 generic_handle_domain_irq(port->event_domain, bit);
0751
0752 chained_irq_exit(chip, desc);
0753 }
0754
0755 static void mc_ack_event_irq(struct irq_data *data)
0756 {
0757 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0758 u32 event = data->hwirq;
0759 void __iomem *addr;
0760 u32 mask;
0761
0762 addr = port->axi_base_addr + event_descs[event].base +
0763 event_descs[event].offset;
0764 mask = event_descs[event].mask;
0765 mask |= event_descs[event].enb_mask;
0766
0767 writel_relaxed(mask, addr);
0768 }
0769
0770 static void mc_mask_event_irq(struct irq_data *data)
0771 {
0772 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0773 u32 event = data->hwirq;
0774 void __iomem *addr;
0775 u32 mask;
0776 u32 val;
0777
0778 addr = port->axi_base_addr + event_descs[event].base +
0779 event_descs[event].mask_offset;
0780 mask = event_descs[event].mask;
0781 if (event_descs[event].enb_mask) {
0782 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
0783 mask &= PCIE_EVENT_INT_ENB_MASK;
0784 }
0785
0786 if (!event_descs[event].mask_high)
0787 mask = ~mask;
0788
0789 raw_spin_lock(&port->lock);
0790 val = readl_relaxed(addr);
0791 if (event_descs[event].mask_high)
0792 val |= mask;
0793 else
0794 val &= mask;
0795
0796 writel_relaxed(val, addr);
0797 raw_spin_unlock(&port->lock);
0798 }
0799
0800 static void mc_unmask_event_irq(struct irq_data *data)
0801 {
0802 struct mc_pcie *port = irq_data_get_irq_chip_data(data);
0803 u32 event = data->hwirq;
0804 void __iomem *addr;
0805 u32 mask;
0806 u32 val;
0807
0808 addr = port->axi_base_addr + event_descs[event].base +
0809 event_descs[event].mask_offset;
0810 mask = event_descs[event].mask;
0811
0812 if (event_descs[event].enb_mask)
0813 mask <<= PCIE_EVENT_INT_ENB_SHIFT;
0814
0815 if (event_descs[event].mask_high)
0816 mask = ~mask;
0817
0818 if (event_descs[event].enb_mask)
0819 mask &= PCIE_EVENT_INT_ENB_MASK;
0820
0821 raw_spin_lock(&port->lock);
0822 val = readl_relaxed(addr);
0823 if (event_descs[event].mask_high)
0824 val &= mask;
0825 else
0826 val |= mask;
0827 writel_relaxed(val, addr);
0828 raw_spin_unlock(&port->lock);
0829 }
0830
0831 static struct irq_chip mc_event_irq_chip = {
0832 .name = "Microchip PCIe EVENT",
0833 .irq_ack = mc_ack_event_irq,
0834 .irq_mask = mc_mask_event_irq,
0835 .irq_unmask = mc_unmask_event_irq,
0836 };
0837
0838 static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq,
0839 irq_hw_number_t hwirq)
0840 {
0841 irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
0842 irq_set_chip_data(irq, domain->host_data);
0843
0844 return 0;
0845 }
0846
0847 static const struct irq_domain_ops event_domain_ops = {
0848 .map = mc_pcie_event_map,
0849 };
0850
0851 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id)
0852 {
0853 struct clk *clk;
0854 int ret;
0855
0856 clk = devm_clk_get_optional(dev, id);
0857 if (IS_ERR(clk))
0858 return clk;
0859 if (!clk)
0860 return clk;
0861
0862 ret = clk_prepare_enable(clk);
0863 if (ret)
0864 return ERR_PTR(ret);
0865
0866 devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare,
0867 clk);
0868
0869 return clk;
0870 }
0871
0872 static int mc_pcie_init_clks(struct device *dev)
0873 {
0874 int i;
0875 struct clk *fic;
0876
0877
0878
0879
0880
0881 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) {
0882 fic = mc_pcie_init_clk(dev, poss_clks[i]);
0883 if (IS_ERR(fic))
0884 return PTR_ERR(fic);
0885 }
0886
0887 return 0;
0888 }
0889
0890 static int mc_pcie_init_irq_domains(struct mc_pcie *port)
0891 {
0892 struct device *dev = port->dev;
0893 struct device_node *node = dev->of_node;
0894 struct device_node *pcie_intc_node;
0895
0896
0897 pcie_intc_node = of_get_next_child(node, NULL);
0898 if (!pcie_intc_node) {
0899 dev_err(dev, "failed to find PCIe Intc node\n");
0900 return -EINVAL;
0901 }
0902
0903 port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS,
0904 &event_domain_ops, port);
0905 if (!port->event_domain) {
0906 dev_err(dev, "failed to get event domain\n");
0907 of_node_put(pcie_intc_node);
0908 return -ENOMEM;
0909 }
0910
0911 irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS);
0912
0913 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
0914 &intx_domain_ops, port);
0915 if (!port->intx_domain) {
0916 dev_err(dev, "failed to get an INTx IRQ domain\n");
0917 of_node_put(pcie_intc_node);
0918 return -ENOMEM;
0919 }
0920
0921 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED);
0922
0923 of_node_put(pcie_intc_node);
0924 raw_spin_lock_init(&port->lock);
0925
0926 return mc_allocate_msi_domains(port);
0927 }
0928
0929 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
0930 phys_addr_t axi_addr, phys_addr_t pci_addr,
0931 size_t size)
0932 {
0933 u32 atr_sz = ilog2(size) - 1;
0934 u32 val;
0935
0936 if (index == 0)
0937 val = PCIE_CONFIG_INTERFACE;
0938 else
0939 val = PCIE_TX_RX_INTERFACE;
0940
0941 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
0942 ATR0_AXI4_SLV0_TRSL_PARAM);
0943
0944 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) |
0945 ATR_IMPL_ENABLE;
0946 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
0947 ATR0_AXI4_SLV0_SRCADDR_PARAM);
0948
0949 val = upper_32_bits(axi_addr);
0950 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
0951 ATR0_AXI4_SLV0_SRC_ADDR);
0952
0953 val = lower_32_bits(pci_addr);
0954 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
0955 ATR0_AXI4_SLV0_TRSL_ADDR_LSB);
0956
0957 val = upper_32_bits(pci_addr);
0958 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
0959 ATR0_AXI4_SLV0_TRSL_ADDR_UDW);
0960
0961 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
0962 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
0963 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
0964 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
0965 }
0966
0967 static int mc_pcie_setup_windows(struct platform_device *pdev,
0968 struct mc_pcie *port)
0969 {
0970 void __iomem *bridge_base_addr =
0971 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
0972 struct pci_host_bridge *bridge = platform_get_drvdata(pdev);
0973 struct resource_entry *entry;
0974 u64 pci_addr;
0975 u32 index = 1;
0976
0977 resource_list_for_each_entry(entry, &bridge->windows) {
0978 if (resource_type(entry->res) == IORESOURCE_MEM) {
0979 pci_addr = entry->res->start - entry->offset;
0980 mc_pcie_setup_window(bridge_base_addr, index,
0981 entry->res->start, pci_addr,
0982 resource_size(entry->res));
0983 index++;
0984 }
0985 }
0986
0987 return 0;
0988 }
0989
0990 static int mc_platform_init(struct pci_config_window *cfg)
0991 {
0992 struct device *dev = cfg->parent;
0993 struct platform_device *pdev = to_platform_device(dev);
0994 struct mc_pcie *port;
0995 void __iomem *bridge_base_addr;
0996 void __iomem *ctrl_base_addr;
0997 int ret;
0998 int irq;
0999 int i, intx_irq, msi_irq, event_irq;
1000 u32 val;
1001 int err;
1002
1003 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1004 if (!port)
1005 return -ENOMEM;
1006 port->dev = dev;
1007
1008 ret = mc_pcie_init_clks(dev);
1009 if (ret) {
1010 dev_err(dev, "failed to get clock resources, error %d\n", ret);
1011 return -ENODEV;
1012 }
1013
1014 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1);
1015 if (IS_ERR(port->axi_base_addr))
1016 return PTR_ERR(port->axi_base_addr);
1017
1018 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
1019 ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR;
1020
1021 port->msi.vector_phy = MSI_ADDR;
1022 port->msi.num_vectors = MC_NUM_MSI_IRQS;
1023 ret = mc_pcie_init_irq_domains(port);
1024 if (ret) {
1025 dev_err(dev, "failed creating IRQ domains\n");
1026 return ret;
1027 }
1028
1029 irq = platform_get_irq(pdev, 0);
1030 if (irq < 0)
1031 return -ENODEV;
1032
1033 for (i = 0; i < NUM_EVENTS; i++) {
1034 event_irq = irq_create_mapping(port->event_domain, i);
1035 if (!event_irq) {
1036 dev_err(dev, "failed to map hwirq %d\n", i);
1037 return -ENXIO;
1038 }
1039
1040 err = devm_request_irq(dev, event_irq, mc_event_handler,
1041 0, event_cause[i].sym, port);
1042 if (err) {
1043 dev_err(dev, "failed to request IRQ %d\n", event_irq);
1044 return err;
1045 }
1046 }
1047
1048 intx_irq = irq_create_mapping(port->event_domain,
1049 EVENT_LOCAL_PM_MSI_INT_INTX);
1050 if (!intx_irq) {
1051 dev_err(dev, "failed to map INTx interrupt\n");
1052 return -ENXIO;
1053 }
1054
1055
1056 irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port);
1057
1058 msi_irq = irq_create_mapping(port->event_domain,
1059 EVENT_LOCAL_PM_MSI_INT_MSI);
1060 if (!msi_irq)
1061 return -ENXIO;
1062
1063
1064 irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port);
1065
1066
1067 irq_set_chained_handler_and_data(irq, mc_handle_event, port);
1068
1069
1070 mc_pcie_enable_msi(port, cfg->win);
1071
1072 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL);
1073 val |= PM_MSI_INT_INTX_MASK;
1074 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL);
1075
1076 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL);
1077
1078 val = PCIE_EVENT_INT_L2_EXIT_INT |
1079 PCIE_EVENT_INT_HOTRST_EXIT_INT |
1080 PCIE_EVENT_INT_DLUP_EXIT_INT;
1081 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT);
1082
1083 val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT |
1084 SEC_ERROR_INT_RX_RAM_SEC_ERR_INT |
1085 SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT |
1086 SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT;
1087 writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT);
1088 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK);
1089 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT);
1090
1091 val = DED_ERROR_INT_TX_RAM_DED_ERR_INT |
1092 DED_ERROR_INT_RX_RAM_DED_ERR_INT |
1093 DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT |
1094 DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT;
1095 writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT);
1096 writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK);
1097 writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT);
1098
1099 writel_relaxed(0, bridge_base_addr + IMASK_HOST);
1100 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);
1101
1102
1103 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff,
1104 cfg->res.start, resource_size(&cfg->res));
1105
1106 return mc_pcie_setup_windows(pdev, port);
1107 }
1108
1109 static const struct pci_ecam_ops mc_ecam_ops = {
1110 .init = mc_platform_init,
1111 .pci_ops = {
1112 .map_bus = pci_ecam_map_bus,
1113 .read = pci_generic_config_read,
1114 .write = pci_generic_config_write,
1115 }
1116 };
1117
1118 static const struct of_device_id mc_pcie_of_match[] = {
1119 {
1120 .compatible = "microchip,pcie-host-1.0",
1121 .data = &mc_ecam_ops,
1122 },
1123 {},
1124 };
1125
1126 MODULE_DEVICE_TABLE(of, mc_pcie_of_match);
1127
1128 static struct platform_driver mc_pcie_driver = {
1129 .probe = pci_host_common_probe,
1130 .driver = {
1131 .name = "microchip-pcie",
1132 .of_match_table = mc_pcie_of_match,
1133 .suppress_bind_attrs = true,
1134 },
1135 };
1136
1137 builtin_platform_driver(mc_pcie_driver);
1138 MODULE_LICENSE("GPL");
1139 MODULE_DESCRIPTION("Microchip PCIe host controller driver");
1140 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
