pci/controller/pcie-hisi-error.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for handling the PCIe controller errors on
0004  * HiSilicon HIP SoCs.
0005  *
0006  * Copyright (c) 2020 HiSilicon Limited.
0007  */
0008
0009 #include <linux/acpi.h>
0010 #include <acpi/ghes.h>
0011 #include <linux/bitops.h>
0012 #include <linux/delay.h>
0013 #include <linux/pci.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/kfifo.h>
0016 #include <linux/spinlock.h>
0017
0018 /* HISI PCIe controller error definitions */
0019 #define HISI_PCIE_ERR_MISC_REGS 33
0020
0021 #define HISI_PCIE_LOCAL_VALID_VERSION       BIT(0)
0022 #define HISI_PCIE_LOCAL_VALID_SOC_ID        BIT(1)
0023 #define HISI_PCIE_LOCAL_VALID_SOCKET_ID     BIT(2)
0024 #define HISI_PCIE_LOCAL_VALID_NIMBUS_ID     BIT(3)
0025 #define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4)
0026 #define HISI_PCIE_LOCAL_VALID_CORE_ID       BIT(5)
0027 #define HISI_PCIE_LOCAL_VALID_PORT_ID       BIT(6)
0028 #define HISI_PCIE_LOCAL_VALID_ERR_TYPE      BIT(7)
0029 #define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY  BIT(8)
0030 #define HISI_PCIE_LOCAL_VALID_ERR_MISC      9
0031
0032 static guid_t hisi_pcie_sec_guid =
0033     GUID_INIT(0xB2889FC9, 0xE7D7, 0x4F9D,
0034           0xA8, 0x67, 0xAF, 0x42, 0xE9, 0x8B, 0xE7, 0x72);
0035
0036 /*
0037  * Firmware reports the socket port ID where the error occurred.  These
0038  * macros convert that to the core ID and core port ID required by the
0039  * ACPI reset method.
0040  */
0041 #define HISI_PCIE_PORT_ID(core, v)       (((v) >> 1) + ((core) << 3))
0042 #define HISI_PCIE_CORE_ID(v)             ((v) >> 3)
0043 #define HISI_PCIE_CORE_PORT_ID(v)        (((v) & 7) << 1)
0044
0045 struct hisi_pcie_error_data {
0046     u64 val_bits;
0047     u8  version;
0048     u8  soc_id;
0049     u8  socket_id;
0050     u8  nimbus_id;
0051     u8  sub_module_id;
0052     u8  core_id;
0053     u8  port_id;
0054     u8  err_severity;
0055     u16 err_type;
0056     u8  reserv[2];
0057     u32 err_misc[HISI_PCIE_ERR_MISC_REGS];
0058 };
0059
0060 struct hisi_pcie_error_private {
0061     struct notifier_block   nb;
0062     struct device *dev;
0063 };
0064
0065 enum hisi_pcie_submodule_id {
0066     HISI_PCIE_SUB_MODULE_ID_AP,
0067     HISI_PCIE_SUB_MODULE_ID_TL,
0068     HISI_PCIE_SUB_MODULE_ID_MAC,
0069     HISI_PCIE_SUB_MODULE_ID_DL,
0070     HISI_PCIE_SUB_MODULE_ID_SDI,
0071 };
0072
0073 static const char * const hisi_pcie_sub_module[] = {
0074     [HISI_PCIE_SUB_MODULE_ID_AP]    = "AP Layer",
0075     [HISI_PCIE_SUB_MODULE_ID_TL]    = "TL Layer",
0076     [HISI_PCIE_SUB_MODULE_ID_MAC]   = "MAC Layer",
0077     [HISI_PCIE_SUB_MODULE_ID_DL]    = "DL Layer",
0078     [HISI_PCIE_SUB_MODULE_ID_SDI]   = "SDI Layer",
0079 };
0080
0081 enum hisi_pcie_err_severity {
0082     HISI_PCIE_ERR_SEV_RECOVERABLE,
0083     HISI_PCIE_ERR_SEV_FATAL,
0084     HISI_PCIE_ERR_SEV_CORRECTED,
0085     HISI_PCIE_ERR_SEV_NONE,
0086 };
0087
0088 static const char * const hisi_pcie_error_sev[] = {
0089     [HISI_PCIE_ERR_SEV_RECOVERABLE] = "recoverable",
0090     [HISI_PCIE_ERR_SEV_FATAL]   = "fatal",
0091     [HISI_PCIE_ERR_SEV_CORRECTED]   = "corrected",
0092     [HISI_PCIE_ERR_SEV_NONE]    = "none",
0093 };
0094
0095 static const char *hisi_pcie_get_string(const char * const *array,
0096                     size_t n, u32 id)
0097 {
0098     u32 index;
0099
0100     for (index = 0; index < n; index++) {
0101         if (index == id && array[index])
0102             return array[index];
0103     }
0104
0105     return "unknown";
0106 }
0107
0108 static int hisi_pcie_port_reset(struct platform_device *pdev,
0109                 u32 chip_id, u32 port_id)
0110 {
0111     struct device *dev = &pdev->dev;
0112     acpi_handle handle = ACPI_HANDLE(dev);
0113     union acpi_object arg[3];
0114     struct acpi_object_list arg_list;
0115     acpi_status s;
0116     unsigned long long data = 0;
0117
0118     arg[0].type = ACPI_TYPE_INTEGER;
0119     arg[0].integer.value = chip_id;
0120     arg[1].type = ACPI_TYPE_INTEGER;
0121     arg[1].integer.value = HISI_PCIE_CORE_ID(port_id);
0122     arg[2].type = ACPI_TYPE_INTEGER;
0123     arg[2].integer.value = HISI_PCIE_CORE_PORT_ID(port_id);
0124
0125     arg_list.count = 3;
0126     arg_list.pointer = arg;
0127
0128     s = acpi_evaluate_integer(handle, "RST", &arg_list, &data);
0129     if (ACPI_FAILURE(s)) {
0130         dev_err(dev, "No RST method\n");
0131         return -EIO;
0132     }
0133
0134     if (data) {
0135         dev_err(dev, "Failed to Reset\n");
0136         return -EIO;
0137     }
0138
0139     return 0;
0140 }
0141
0142 static int hisi_pcie_port_do_recovery(struct platform_device *dev,
0143                       u32 chip_id, u32 port_id)
0144 {
0145     acpi_status s;
0146     struct device *device = &dev->dev;
0147     acpi_handle root_handle = ACPI_HANDLE(device);
0148     struct acpi_pci_root *pci_root;
0149     struct pci_bus *root_bus;
0150     struct pci_dev *pdev;
0151     u32 domain, busnr, devfn;
0152
0153     s = acpi_get_parent(root_handle, &root_handle);
0154     if (ACPI_FAILURE(s))
0155         return -ENODEV;
0156     pci_root = acpi_pci_find_root(root_handle);
0157     if (!pci_root)
0158         return -ENODEV;
0159     root_bus = pci_root->bus;
0160     domain = pci_root->segment;
0161
0162     busnr = root_bus->number;
0163     devfn = PCI_DEVFN(port_id, 0);
0164     pdev = pci_get_domain_bus_and_slot(domain, busnr, devfn);
0165     if (!pdev) {
0166         dev_info(device, "Fail to get root port %04x:%02x:%02x.%d device\n",
0167              domain, busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
0168         return -ENODEV;
0169     }
0170
0171     pci_stop_and_remove_bus_device_locked(pdev);
0172     pci_dev_put(pdev);
0173
0174     if (hisi_pcie_port_reset(dev, chip_id, port_id))
0175         return -EIO;
0176
0177     /*
0178      * The initialization time of subordinate devices after
0179      * hot reset is no more than 1s, which is required by
0180      * the PCI spec v5.0 sec 6.6.1. The time will shorten
0181      * if Readiness Notifications mechanisms are used. But
0182      * wait 1s here to adapt any conditions.
0183      */
0184     ssleep(1UL);
0185
0186     /* add root port and downstream devices */
0187     pci_lock_rescan_remove();
0188     pci_rescan_bus(root_bus);
0189     pci_unlock_rescan_remove();
0190
0191     return 0;
0192 }
0193
0194 static void hisi_pcie_handle_error(struct platform_device *pdev,
0195                    const struct hisi_pcie_error_data *edata)
0196 {
0197     struct device *dev = &pdev->dev;
0198     int idx, rc;
0199     const unsigned long valid_bits[] = {BITMAP_FROM_U64(edata->val_bits)};
0200
0201     if (edata->val_bits == 0) {
0202         dev_warn(dev, "%s: no valid error information\n", __func__);
0203         return;
0204     }
0205
0206     dev_info(dev, "\nHISI : HIP : PCIe controller error\n");
0207     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID)
0208         dev_info(dev, "Table version = %d\n", edata->version);
0209     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID)
0210         dev_info(dev, "Socket ID = %d\n", edata->socket_id);
0211     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID)
0212         dev_info(dev, "Nimbus ID = %d\n", edata->nimbus_id);
0213     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID)
0214         dev_info(dev, "Sub Module = %s\n",
0215              hisi_pcie_get_string(hisi_pcie_sub_module,
0216                           ARRAY_SIZE(hisi_pcie_sub_module),
0217                           edata->sub_module_id));
0218     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID)
0219         dev_info(dev, "Core ID = core%d\n", edata->core_id);
0220     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID)
0221         dev_info(dev, "Port ID = port%d\n", edata->port_id);
0222     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY)
0223         dev_info(dev, "Error severity = %s\n",
0224              hisi_pcie_get_string(hisi_pcie_error_sev,
0225                           ARRAY_SIZE(hisi_pcie_error_sev),
0226                           edata->err_severity));
0227     if (edata->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE)
0228         dev_info(dev, "Error type = 0x%x\n", edata->err_type);
0229
0230     dev_info(dev, "Reg Dump:\n");
0231     idx = HISI_PCIE_LOCAL_VALID_ERR_MISC;
0232     for_each_set_bit_from(idx, valid_bits,
0233                   HISI_PCIE_LOCAL_VALID_ERR_MISC + HISI_PCIE_ERR_MISC_REGS)
0234         dev_info(dev, "ERR_MISC_%d = 0x%x\n", idx - HISI_PCIE_LOCAL_VALID_ERR_MISC,
0235              edata->err_misc[idx - HISI_PCIE_LOCAL_VALID_ERR_MISC]);
0236
0237     if (edata->err_severity != HISI_PCIE_ERR_SEV_RECOVERABLE)
0238         return;
0239
0240     /* Recovery for the PCIe controller errors, try reset
0241      * PCI port for the error recovery
0242      */
0243     rc = hisi_pcie_port_do_recovery(pdev, edata->socket_id,
0244             HISI_PCIE_PORT_ID(edata->core_id, edata->port_id));
0245     if (rc)
0246         dev_info(dev, "fail to do hisi pcie port reset\n");
0247 }
0248
0249 static int hisi_pcie_notify_error(struct notifier_block *nb,
0250                   unsigned long event, void *data)
0251 {
0252     struct acpi_hest_generic_data *gdata = data;
0253     const struct hisi_pcie_error_data *error_data = acpi_hest_get_payload(gdata);
0254     struct hisi_pcie_error_private *priv;
0255     struct device *dev;
0256     struct platform_device *pdev;
0257     guid_t err_sec_guid;
0258     u8 socket;
0259
0260     import_guid(&err_sec_guid, gdata->section_type);
0261     if (!guid_equal(&err_sec_guid, &hisi_pcie_sec_guid))
0262         return NOTIFY_DONE;
0263
0264     priv = container_of(nb, struct hisi_pcie_error_private, nb);
0265     dev = priv->dev;
0266
0267     if (device_property_read_u8(dev, "socket", &socket))
0268         return NOTIFY_DONE;
0269
0270     if (error_data->socket_id != socket)
0271         return NOTIFY_DONE;
0272
0273     pdev = container_of(dev, struct platform_device, dev);
0274     hisi_pcie_handle_error(pdev, error_data);
0275
0276     return NOTIFY_OK;
0277 }
0278
0279 static int hisi_pcie_error_handler_probe(struct platform_device *pdev)
0280 {
0281     struct hisi_pcie_error_private *priv;
0282     int ret;
0283
0284     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0285     if (!priv)
0286         return -ENOMEM;
0287
0288     priv->nb.notifier_call = hisi_pcie_notify_error;
0289     priv->dev = &pdev->dev;
0290     ret = ghes_register_vendor_record_notifier(&priv->nb);
0291     if (ret) {
0292         dev_err(&pdev->dev,
0293             "Failed to register hisi pcie controller error handler with apei\n");
0294         return ret;
0295     }
0296
0297     platform_set_drvdata(pdev, priv);
0298
0299     return 0;
0300 }
0301
0302 static int hisi_pcie_error_handler_remove(struct platform_device *pdev)
0303 {
0304     struct hisi_pcie_error_private *priv = platform_get_drvdata(pdev);
0305
0306     ghes_unregister_vendor_record_notifier(&priv->nb);
0307
0308     return 0;
0309 }
0310
0311 static const struct acpi_device_id hisi_pcie_acpi_match[] = {
0312     { "HISI0361", 0 },
0313     { }
0314 };
0315
0316 static struct platform_driver hisi_pcie_error_handler_driver = {
0317     .driver = {
0318         .name   = "hisi-pcie-error-handler",
0319         .acpi_match_table = hisi_pcie_acpi_match,
0320     },
0321     .probe      = hisi_pcie_error_handler_probe,
0322     .remove     = hisi_pcie_error_handler_remove,
0323 };
0324 module_platform_driver(hisi_pcie_error_handler_driver);
0325
0326 MODULE_DESCRIPTION("HiSilicon HIP PCIe controller error handling driver");
0327 MODULE_LICENSE("GPL v2");