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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
0004  *
0005  * Author: Ley Foon Tan <lftan@altera.com>
0006  * Description: Altera PCIe host controller driver
0007  */
0008 
0009 #include <linux/delay.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/irqchip/chained_irq.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_device.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/of_pci.h>
0018 #include <linux/pci.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 
0022 #include "../pci.h"
0023 
0024 #define RP_TX_REG0          0x2000
0025 #define RP_TX_REG1          0x2004
0026 #define RP_TX_CNTRL         0x2008
0027 #define RP_TX_EOP           0x2
0028 #define RP_TX_SOP           0x1
0029 #define RP_RXCPL_STATUS         0x2010
0030 #define RP_RXCPL_EOP            0x2
0031 #define RP_RXCPL_SOP            0x1
0032 #define RP_RXCPL_REG0           0x2014
0033 #define RP_RXCPL_REG1           0x2018
0034 #define P2A_INT_STATUS          0x3060
0035 #define P2A_INT_STS_ALL         0xf
0036 #define P2A_INT_ENABLE          0x3070
0037 #define P2A_INT_ENA_ALL         0xf
0038 #define RP_LTSSM            0x3c64
0039 #define RP_LTSSM_MASK           0x1f
0040 #define LTSSM_L0            0xf
0041 
0042 #define S10_RP_TX_CNTRL         0x2004
0043 #define S10_RP_RXCPL_REG        0x2008
0044 #define S10_RP_RXCPL_STATUS     0x200C
0045 #define S10_RP_CFG_ADDR(pcie, reg)  \
0046     (((pcie)->hip_base) + (reg) + (1 << 20))
0047 #define S10_RP_SECONDARY(pcie)      \
0048     readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
0049 
0050 /* TLP configuration type 0 and 1 */
0051 #define TLP_FMTTYPE_CFGRD0      0x04    /* Configuration Read Type 0 */
0052 #define TLP_FMTTYPE_CFGWR0      0x44    /* Configuration Write Type 0 */
0053 #define TLP_FMTTYPE_CFGRD1      0x05    /* Configuration Read Type 1 */
0054 #define TLP_FMTTYPE_CFGWR1      0x45    /* Configuration Write Type 1 */
0055 #define TLP_PAYLOAD_SIZE        0x01
0056 #define TLP_READ_TAG            0x1d
0057 #define TLP_WRITE_TAG           0x10
0058 #define RP_DEVFN            0
0059 #define TLP_REQ_ID(bus, devfn)      (((bus) << 8) | (devfn))
0060 #define TLP_CFG_DW0(pcie, cfg)      \
0061         (((cfg) << 24) |    \
0062           TLP_PAYLOAD_SIZE)
0063 #define TLP_CFG_DW1(pcie, tag, be)  \
0064     (((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
0065 #define TLP_CFG_DW2(bus, devfn, offset) \
0066                 (((bus) << 24) | ((devfn) << 16) | (offset))
0067 #define TLP_COMP_STATUS(s)      (((s) >> 13) & 7)
0068 #define TLP_BYTE_COUNT(s)       (((s) >> 0) & 0xfff)
0069 #define TLP_HDR_SIZE            3
0070 #define TLP_LOOP            500
0071 
0072 #define LINK_UP_TIMEOUT         HZ
0073 #define LINK_RETRAIN_TIMEOUT        HZ
0074 
0075 #define DWORD_MASK          3
0076 
0077 #define S10_TLP_FMTTYPE_CFGRD0      0x05
0078 #define S10_TLP_FMTTYPE_CFGRD1      0x04
0079 #define S10_TLP_FMTTYPE_CFGWR0      0x45
0080 #define S10_TLP_FMTTYPE_CFGWR1      0x44
0081 
0082 enum altera_pcie_version {
0083     ALTERA_PCIE_V1 = 0,
0084     ALTERA_PCIE_V2,
0085 };
0086 
0087 struct altera_pcie {
0088     struct platform_device  *pdev;
0089     void __iomem        *cra_base;
0090     void __iomem        *hip_base;
0091     int         irq;
0092     u8          root_bus_nr;
0093     struct irq_domain   *irq_domain;
0094     struct resource     bus_range;
0095     const struct altera_pcie_data   *pcie_data;
0096 };
0097 
0098 struct altera_pcie_ops {
0099     int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
0100     void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
0101                   u32 data, bool align);
0102     bool (*get_link_status)(struct altera_pcie *pcie);
0103     int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
0104                int size, u32 *value);
0105     int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
0106                 int where, int size, u32 value);
0107 };
0108 
0109 struct altera_pcie_data {
0110     const struct altera_pcie_ops *ops;
0111     enum altera_pcie_version version;
0112     u32 cap_offset;     /* PCIe capability structure register offset */
0113     u32 cfgrd0;
0114     u32 cfgrd1;
0115     u32 cfgwr0;
0116     u32 cfgwr1;
0117 };
0118 
0119 struct tlp_rp_regpair_t {
0120     u32 ctrl;
0121     u32 reg0;
0122     u32 reg1;
0123 };
0124 
0125 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
0126                   const u32 reg)
0127 {
0128     writel_relaxed(value, pcie->cra_base + reg);
0129 }
0130 
0131 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
0132 {
0133     return readl_relaxed(pcie->cra_base + reg);
0134 }
0135 
0136 static bool altera_pcie_link_up(struct altera_pcie *pcie)
0137 {
0138     return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
0139 }
0140 
0141 static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
0142 {
0143     void __iomem *addr = S10_RP_CFG_ADDR(pcie,
0144                    pcie->pcie_data->cap_offset +
0145                    PCI_EXP_LNKSTA);
0146 
0147     return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
0148 }
0149 
0150 /*
0151  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
0152  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
0153  * using these registers, so it can be reached by DMA from EP devices.
0154  * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
0155  * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
0156  * should be hidden during enumeration to avoid the sizing and resource
0157  * allocation by PCIe core.
0158  */
0159 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
0160                     int offset)
0161 {
0162     if (pci_is_root_bus(bus) && (devfn == 0) &&
0163         (offset == PCI_BASE_ADDRESS_0))
0164         return true;
0165 
0166     return false;
0167 }
0168 
0169 static void tlp_write_tx(struct altera_pcie *pcie,
0170              struct tlp_rp_regpair_t *tlp_rp_regdata)
0171 {
0172     cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
0173     cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
0174     cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
0175 }
0176 
0177 static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)
0178 {
0179     cra_writel(pcie, reg0, RP_TX_REG0);
0180     cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);
0181 }
0182 
0183 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
0184                      struct pci_bus *bus, int dev)
0185 {
0186     /* If there is no link, then there is no device */
0187     if (bus->number != pcie->root_bus_nr) {
0188         if (!pcie->pcie_data->ops->get_link_status(pcie))
0189             return false;
0190     }
0191 
0192     /* access only one slot on each root port */
0193     if (bus->number == pcie->root_bus_nr && dev > 0)
0194         return false;
0195 
0196     return true;
0197 }
0198 
0199 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
0200 {
0201     int i;
0202     bool sop = false;
0203     u32 ctrl;
0204     u32 reg0, reg1;
0205     u32 comp_status = 1;
0206 
0207     /*
0208      * Minimum 2 loops to read TLP headers and 1 loop to read data
0209      * payload.
0210      */
0211     for (i = 0; i < TLP_LOOP; i++) {
0212         ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
0213         if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
0214             reg0 = cra_readl(pcie, RP_RXCPL_REG0);
0215             reg1 = cra_readl(pcie, RP_RXCPL_REG1);
0216 
0217             if (ctrl & RP_RXCPL_SOP) {
0218                 sop = true;
0219                 comp_status = TLP_COMP_STATUS(reg1);
0220             }
0221 
0222             if (ctrl & RP_RXCPL_EOP) {
0223                 if (comp_status)
0224                     return PCIBIOS_DEVICE_NOT_FOUND;
0225 
0226                 if (value)
0227                     *value = reg0;
0228 
0229                 return PCIBIOS_SUCCESSFUL;
0230             }
0231         }
0232         udelay(5);
0233     }
0234 
0235     return PCIBIOS_DEVICE_NOT_FOUND;
0236 }
0237 
0238 static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
0239 {
0240     u32 ctrl;
0241     u32 comp_status;
0242     u32 dw[4];
0243     u32 count;
0244     struct device *dev = &pcie->pdev->dev;
0245 
0246     for (count = 0; count < TLP_LOOP; count++) {
0247         ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
0248         if (ctrl & RP_RXCPL_SOP) {
0249             /* Read first DW */
0250             dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
0251             break;
0252         }
0253 
0254         udelay(5);
0255     }
0256 
0257     /* SOP detection failed, return error */
0258     if (count == TLP_LOOP)
0259         return PCIBIOS_DEVICE_NOT_FOUND;
0260 
0261     count = 1;
0262 
0263     /* Poll for EOP */
0264     while (count < ARRAY_SIZE(dw)) {
0265         ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
0266         dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);
0267         if (ctrl & RP_RXCPL_EOP) {
0268             comp_status = TLP_COMP_STATUS(dw[1]);
0269             if (comp_status)
0270                 return PCIBIOS_DEVICE_NOT_FOUND;
0271 
0272             if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
0273                 count == 4)
0274                 *value = dw[3];
0275 
0276             return PCIBIOS_SUCCESSFUL;
0277         }
0278     }
0279 
0280     dev_warn(dev, "Malformed TLP packet\n");
0281 
0282     return PCIBIOS_DEVICE_NOT_FOUND;
0283 }
0284 
0285 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
0286                  u32 data, bool align)
0287 {
0288     struct tlp_rp_regpair_t tlp_rp_regdata;
0289 
0290     tlp_rp_regdata.reg0 = headers[0];
0291     tlp_rp_regdata.reg1 = headers[1];
0292     tlp_rp_regdata.ctrl = RP_TX_SOP;
0293     tlp_write_tx(pcie, &tlp_rp_regdata);
0294 
0295     if (align) {
0296         tlp_rp_regdata.reg0 = headers[2];
0297         tlp_rp_regdata.reg1 = 0;
0298         tlp_rp_regdata.ctrl = 0;
0299         tlp_write_tx(pcie, &tlp_rp_regdata);
0300 
0301         tlp_rp_regdata.reg0 = data;
0302         tlp_rp_regdata.reg1 = 0;
0303     } else {
0304         tlp_rp_regdata.reg0 = headers[2];
0305         tlp_rp_regdata.reg1 = data;
0306     }
0307 
0308     tlp_rp_regdata.ctrl = RP_TX_EOP;
0309     tlp_write_tx(pcie, &tlp_rp_regdata);
0310 }
0311 
0312 static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
0313                  u32 data, bool dummy)
0314 {
0315     s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
0316     s10_tlp_write_tx(pcie, headers[1], 0);
0317     s10_tlp_write_tx(pcie, headers[2], 0);
0318     s10_tlp_write_tx(pcie, data, RP_TX_EOP);
0319 }
0320 
0321 static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
0322                int where, u8 byte_en, bool read, u32 *headers)
0323 {
0324     u8 cfg;
0325     u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
0326     u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
0327     u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
0328 
0329     if (pcie->pcie_data->version == ALTERA_PCIE_V1)
0330         cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
0331     else
0332         cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
0333 
0334     headers[0] = TLP_CFG_DW0(pcie, cfg);
0335     headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
0336     headers[2] = TLP_CFG_DW2(bus, devfn, where);
0337 }
0338 
0339 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
0340                   int where, u8 byte_en, u32 *value)
0341 {
0342     u32 headers[TLP_HDR_SIZE];
0343 
0344     get_tlp_header(pcie, bus, devfn, where, byte_en, true,
0345                headers);
0346 
0347     pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
0348 
0349     return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
0350 }
0351 
0352 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
0353                    int where, u8 byte_en, u32 value)
0354 {
0355     u32 headers[TLP_HDR_SIZE];
0356     int ret;
0357 
0358     get_tlp_header(pcie, bus, devfn, where, byte_en, false,
0359                headers);
0360 
0361     /* check alignment to Qword */
0362     if ((where & 0x7) == 0)
0363         pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
0364                             value, true);
0365     else
0366         pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
0367                             value, false);
0368 
0369     ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
0370     if (ret != PCIBIOS_SUCCESSFUL)
0371         return ret;
0372 
0373     /*
0374      * Monitor changes to PCI_PRIMARY_BUS register on root port
0375      * and update local copy of root bus number accordingly.
0376      */
0377     if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
0378         pcie->root_bus_nr = (u8)(value);
0379 
0380     return PCIBIOS_SUCCESSFUL;
0381 }
0382 
0383 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,
0384                int size, u32 *value)
0385 {
0386     void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
0387 
0388     switch (size) {
0389     case 1:
0390         *value = readb(addr);
0391         break;
0392     case 2:
0393         *value = readw(addr);
0394         break;
0395     default:
0396         *value = readl(addr);
0397         break;
0398     }
0399 
0400     return PCIBIOS_SUCCESSFUL;
0401 }
0402 
0403 static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
0404                 int where, int size, u32 value)
0405 {
0406     void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
0407 
0408     switch (size) {
0409     case 1:
0410         writeb(value, addr);
0411         break;
0412     case 2:
0413         writew(value, addr);
0414         break;
0415     default:
0416         writel(value, addr);
0417         break;
0418     }
0419 
0420     /*
0421      * Monitor changes to PCI_PRIMARY_BUS register on root port
0422      * and update local copy of root bus number accordingly.
0423      */
0424     if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
0425         pcie->root_bus_nr = value & 0xff;
0426 
0427     return PCIBIOS_SUCCESSFUL;
0428 }
0429 
0430 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
0431                  unsigned int devfn, int where, int size,
0432                  u32 *value)
0433 {
0434     int ret;
0435     u32 data;
0436     u8 byte_en;
0437 
0438     if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
0439         return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
0440                              size, value);
0441 
0442     switch (size) {
0443     case 1:
0444         byte_en = 1 << (where & 3);
0445         break;
0446     case 2:
0447         byte_en = 3 << (where & 3);
0448         break;
0449     default:
0450         byte_en = 0xf;
0451         break;
0452     }
0453 
0454     ret = tlp_cfg_dword_read(pcie, busno, devfn,
0455                  (where & ~DWORD_MASK), byte_en, &data);
0456     if (ret != PCIBIOS_SUCCESSFUL)
0457         return ret;
0458 
0459     switch (size) {
0460     case 1:
0461         *value = (data >> (8 * (where & 0x3))) & 0xff;
0462         break;
0463     case 2:
0464         *value = (data >> (8 * (where & 0x2))) & 0xffff;
0465         break;
0466     default:
0467         *value = data;
0468         break;
0469     }
0470 
0471     return PCIBIOS_SUCCESSFUL;
0472 }
0473 
0474 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
0475                   unsigned int devfn, int where, int size,
0476                   u32 value)
0477 {
0478     u32 data32;
0479     u32 shift = 8 * (where & 3);
0480     u8 byte_en;
0481 
0482     if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
0483         return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
0484                              where, size, value);
0485 
0486     switch (size) {
0487     case 1:
0488         data32 = (value & 0xff) << shift;
0489         byte_en = 1 << (where & 3);
0490         break;
0491     case 2:
0492         data32 = (value & 0xffff) << shift;
0493         byte_en = 3 << (where & 3);
0494         break;
0495     default:
0496         data32 = value;
0497         byte_en = 0xf;
0498         break;
0499     }
0500 
0501     return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
0502                    byte_en, data32);
0503 }
0504 
0505 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
0506                 int where, int size, u32 *value)
0507 {
0508     struct altera_pcie *pcie = bus->sysdata;
0509 
0510     if (altera_pcie_hide_rc_bar(bus, devfn, where))
0511         return PCIBIOS_BAD_REGISTER_NUMBER;
0512 
0513     if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
0514         return PCIBIOS_DEVICE_NOT_FOUND;
0515 
0516     return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
0517                      value);
0518 }
0519 
0520 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
0521                  int where, int size, u32 value)
0522 {
0523     struct altera_pcie *pcie = bus->sysdata;
0524 
0525     if (altera_pcie_hide_rc_bar(bus, devfn, where))
0526         return PCIBIOS_BAD_REGISTER_NUMBER;
0527 
0528     if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
0529         return PCIBIOS_DEVICE_NOT_FOUND;
0530 
0531     return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
0532                      value);
0533 }
0534 
0535 static struct pci_ops altera_pcie_ops = {
0536     .read = altera_pcie_cfg_read,
0537     .write = altera_pcie_cfg_write,
0538 };
0539 
0540 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
0541                 unsigned int devfn, int offset, u16 *value)
0542 {
0543     u32 data;
0544     int ret;
0545 
0546     ret = _altera_pcie_cfg_read(pcie, busno, devfn,
0547                     pcie->pcie_data->cap_offset + offset,
0548                     sizeof(*value),
0549                     &data);
0550     *value = data;
0551     return ret;
0552 }
0553 
0554 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
0555                  unsigned int devfn, int offset, u16 value)
0556 {
0557     return _altera_pcie_cfg_write(pcie, busno, devfn,
0558                       pcie->pcie_data->cap_offset + offset,
0559                       sizeof(value),
0560                       value);
0561 }
0562 
0563 static void altera_wait_link_retrain(struct altera_pcie *pcie)
0564 {
0565     struct device *dev = &pcie->pdev->dev;
0566     u16 reg16;
0567     unsigned long start_jiffies;
0568 
0569     /* Wait for link training end. */
0570     start_jiffies = jiffies;
0571     for (;;) {
0572         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
0573                      PCI_EXP_LNKSTA, &reg16);
0574         if (!(reg16 & PCI_EXP_LNKSTA_LT))
0575             break;
0576 
0577         if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
0578             dev_err(dev, "link retrain timeout\n");
0579             break;
0580         }
0581         udelay(100);
0582     }
0583 
0584     /* Wait for link is up */
0585     start_jiffies = jiffies;
0586     for (;;) {
0587         if (pcie->pcie_data->ops->get_link_status(pcie))
0588             break;
0589 
0590         if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
0591             dev_err(dev, "link up timeout\n");
0592             break;
0593         }
0594         udelay(100);
0595     }
0596 }
0597 
0598 static void altera_pcie_retrain(struct altera_pcie *pcie)
0599 {
0600     u16 linkcap, linkstat, linkctl;
0601 
0602     if (!pcie->pcie_data->ops->get_link_status(pcie))
0603         return;
0604 
0605     /*
0606      * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
0607      * current speed is 2.5 GB/s.
0608      */
0609     altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
0610                  &linkcap);
0611     if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
0612         return;
0613 
0614     altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
0615                  &linkstat);
0616     if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
0617         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
0618                      PCI_EXP_LNKCTL, &linkctl);
0619         linkctl |= PCI_EXP_LNKCTL_RL;
0620         altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
0621                       PCI_EXP_LNKCTL, linkctl);
0622 
0623         altera_wait_link_retrain(pcie);
0624     }
0625 }
0626 
0627 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
0628                 irq_hw_number_t hwirq)
0629 {
0630     irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
0631     irq_set_chip_data(irq, domain->host_data);
0632     return 0;
0633 }
0634 
0635 static const struct irq_domain_ops intx_domain_ops = {
0636     .map = altera_pcie_intx_map,
0637     .xlate = pci_irqd_intx_xlate,
0638 };
0639 
0640 static void altera_pcie_isr(struct irq_desc *desc)
0641 {
0642     struct irq_chip *chip = irq_desc_get_chip(desc);
0643     struct altera_pcie *pcie;
0644     struct device *dev;
0645     unsigned long status;
0646     u32 bit;
0647     int ret;
0648 
0649     chained_irq_enter(chip, desc);
0650     pcie = irq_desc_get_handler_data(desc);
0651     dev = &pcie->pdev->dev;
0652 
0653     while ((status = cra_readl(pcie, P2A_INT_STATUS)
0654         & P2A_INT_STS_ALL) != 0) {
0655         for_each_set_bit(bit, &status, PCI_NUM_INTX) {
0656             /* clear interrupts */
0657             cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
0658 
0659             ret = generic_handle_domain_irq(pcie->irq_domain, bit);
0660             if (ret)
0661                 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
0662         }
0663     }
0664 
0665     chained_irq_exit(chip, desc);
0666 }
0667 
0668 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
0669 {
0670     struct device *dev = &pcie->pdev->dev;
0671     struct device_node *node = dev->of_node;
0672 
0673     /* Setup INTx */
0674     pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
0675                     &intx_domain_ops, pcie);
0676     if (!pcie->irq_domain) {
0677         dev_err(dev, "Failed to get a INTx IRQ domain\n");
0678         return -ENOMEM;
0679     }
0680 
0681     return 0;
0682 }
0683 
0684 static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
0685 {
0686     irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
0687     irq_domain_remove(pcie->irq_domain);
0688     irq_dispose_mapping(pcie->irq);
0689 }
0690 
0691 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
0692 {
0693     struct platform_device *pdev = pcie->pdev;
0694 
0695     pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
0696     if (IS_ERR(pcie->cra_base))
0697         return PTR_ERR(pcie->cra_base);
0698 
0699     if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
0700         pcie->hip_base =
0701             devm_platform_ioremap_resource_byname(pdev, "Hip");
0702         if (IS_ERR(pcie->hip_base))
0703             return PTR_ERR(pcie->hip_base);
0704     }
0705 
0706     /* setup IRQ */
0707     pcie->irq = platform_get_irq(pdev, 0);
0708     if (pcie->irq < 0)
0709         return pcie->irq;
0710 
0711     irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
0712     return 0;
0713 }
0714 
0715 static void altera_pcie_host_init(struct altera_pcie *pcie)
0716 {
0717     altera_pcie_retrain(pcie);
0718 }
0719 
0720 static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
0721     .tlp_read_pkt = tlp_read_packet,
0722     .tlp_write_pkt = tlp_write_packet,
0723     .get_link_status = altera_pcie_link_up,
0724 };
0725 
0726 static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
0727     .tlp_read_pkt = s10_tlp_read_packet,
0728     .tlp_write_pkt = s10_tlp_write_packet,
0729     .get_link_status = s10_altera_pcie_link_up,
0730     .rp_read_cfg = s10_rp_read_cfg,
0731     .rp_write_cfg = s10_rp_write_cfg,
0732 };
0733 
0734 static const struct altera_pcie_data altera_pcie_1_0_data = {
0735     .ops = &altera_pcie_ops_1_0,
0736     .cap_offset = 0x80,
0737     .version = ALTERA_PCIE_V1,
0738     .cfgrd0 = TLP_FMTTYPE_CFGRD0,
0739     .cfgrd1 = TLP_FMTTYPE_CFGRD1,
0740     .cfgwr0 = TLP_FMTTYPE_CFGWR0,
0741     .cfgwr1 = TLP_FMTTYPE_CFGWR1,
0742 };
0743 
0744 static const struct altera_pcie_data altera_pcie_2_0_data = {
0745     .ops = &altera_pcie_ops_2_0,
0746     .version = ALTERA_PCIE_V2,
0747     .cap_offset = 0x70,
0748     .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
0749     .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
0750     .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
0751     .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
0752 };
0753 
0754 static const struct of_device_id altera_pcie_of_match[] = {
0755     {.compatible = "altr,pcie-root-port-1.0",
0756      .data = &altera_pcie_1_0_data },
0757     {.compatible = "altr,pcie-root-port-2.0",
0758      .data = &altera_pcie_2_0_data },
0759     {},
0760 };
0761 
0762 static int altera_pcie_probe(struct platform_device *pdev)
0763 {
0764     struct device *dev = &pdev->dev;
0765     struct altera_pcie *pcie;
0766     struct pci_host_bridge *bridge;
0767     int ret;
0768     const struct altera_pcie_data *data;
0769 
0770     bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
0771     if (!bridge)
0772         return -ENOMEM;
0773 
0774     pcie = pci_host_bridge_priv(bridge);
0775     pcie->pdev = pdev;
0776     platform_set_drvdata(pdev, pcie);
0777 
0778     data = of_device_get_match_data(&pdev->dev);
0779     if (!data)
0780         return -ENODEV;
0781 
0782     pcie->pcie_data = data;
0783 
0784     ret = altera_pcie_parse_dt(pcie);
0785     if (ret) {
0786         dev_err(dev, "Parsing DT failed\n");
0787         return ret;
0788     }
0789 
0790     ret = altera_pcie_init_irq_domain(pcie);
0791     if (ret) {
0792         dev_err(dev, "Failed creating IRQ Domain\n");
0793         return ret;
0794     }
0795 
0796     /* clear all interrupts */
0797     cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
0798     /* enable all interrupts */
0799     cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
0800     altera_pcie_host_init(pcie);
0801 
0802     bridge->sysdata = pcie;
0803     bridge->busnr = pcie->root_bus_nr;
0804     bridge->ops = &altera_pcie_ops;
0805 
0806     return pci_host_probe(bridge);
0807 }
0808 
0809 static int altera_pcie_remove(struct platform_device *pdev)
0810 {
0811     struct altera_pcie *pcie = platform_get_drvdata(pdev);
0812     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
0813 
0814     pci_stop_root_bus(bridge->bus);
0815     pci_remove_root_bus(bridge->bus);
0816     altera_pcie_irq_teardown(pcie);
0817 
0818     return 0;
0819 }
0820 
0821 static struct platform_driver altera_pcie_driver = {
0822     .probe      = altera_pcie_probe,
0823     .remove     = altera_pcie_remove,
0824     .driver = {
0825         .name   = "altera-pcie",
0826         .of_match_table = altera_pcie_of_match,
0827     },
0828 };
0829 
0830 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
0831 module_platform_driver(altera_pcie_driver);
0832 MODULE_LICENSE("GPL v2");
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