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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * APM X-Gene PCIe Driver
0004  *
0005  * Copyright (c) 2014 Applied Micro Circuits Corporation.
0006  *
0007  * Author: Tanmay Inamdar <tinamdar@apm.com>.
0008  */
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/jiffies.h>
0013 #include <linux/memblock.h>
0014 #include <linux/init.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_pci.h>
0019 #include <linux/pci.h>
0020 #include <linux/pci-acpi.h>
0021 #include <linux/pci-ecam.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/slab.h>
0024 
0025 #include "../pci.h"
0026 
0027 #define PCIECORE_CTLANDSTATUS       0x50
0028 #define PIM1_1L             0x80
0029 #define IBAR2               0x98
0030 #define IR2MSK              0x9c
0031 #define PIM2_1L             0xa0
0032 #define IBAR3L              0xb4
0033 #define IR3MSKL             0xbc
0034 #define PIM3_1L             0xc4
0035 #define OMR1BARL            0x100
0036 #define OMR2BARL            0x118
0037 #define OMR3BARL            0x130
0038 #define CFGBARL             0x154
0039 #define CFGBARH             0x158
0040 #define CFGCTL              0x15c
0041 #define RTDID               0x160
0042 #define BRIDGE_CFG_0            0x2000
0043 #define BRIDGE_CFG_4            0x2010
0044 #define BRIDGE_STATUS_0         0x2600
0045 
0046 #define LINK_UP_MASK            0x00000100
0047 #define AXI_EP_CFG_ACCESS       0x10000
0048 #define EN_COHERENCY            0xF0000000
0049 #define EN_REG              0x00000001
0050 #define OB_LO_IO            0x00000002
0051 #define XGENE_PCIE_DEVICEID     0xE004
0052 #define PIPE_PHY_RATE_RD(src)       ((0xc000 & (u32)(src)) >> 0xe)
0053 
0054 #define XGENE_V1_PCI_EXP_CAP        0x40
0055 
0056 /* PCIe IP version */
0057 #define XGENE_PCIE_IP_VER_UNKN      0
0058 #define XGENE_PCIE_IP_VER_1     1
0059 #define XGENE_PCIE_IP_VER_2     2
0060 
0061 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
0062 struct xgene_pcie {
0063     struct device_node  *node;
0064     struct device       *dev;
0065     struct clk      *clk;
0066     void __iomem        *csr_base;
0067     void __iomem        *cfg_base;
0068     unsigned long       cfg_addr;
0069     bool            link_up;
0070     u32         version;
0071 };
0072 
0073 static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)
0074 {
0075     return readl(port->csr_base + reg);
0076 }
0077 
0078 static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)
0079 {
0080     writel(val, port->csr_base + reg);
0081 }
0082 
0083 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
0084 {
0085     return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
0086 }
0087 
0088 static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus)
0089 {
0090     struct pci_config_window *cfg;
0091 
0092     if (acpi_disabled)
0093         return (struct xgene_pcie *)(bus->sysdata);
0094 
0095     cfg = bus->sysdata;
0096     return (struct xgene_pcie *)(cfg->priv);
0097 }
0098 
0099 /*
0100  * When the address bit [17:16] is 2'b01, the Configuration access will be
0101  * treated as Type 1 and it will be forwarded to external PCIe device.
0102  */
0103 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
0104 {
0105     struct xgene_pcie *port = pcie_bus_to_port(bus);
0106 
0107     if (bus->number >= (bus->primary + 1))
0108         return port->cfg_base + AXI_EP_CFG_ACCESS;
0109 
0110     return port->cfg_base;
0111 }
0112 
0113 /*
0114  * For Configuration request, RTDID register is used as Bus Number,
0115  * Device Number and Function number of the header fields.
0116  */
0117 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
0118 {
0119     struct xgene_pcie *port = pcie_bus_to_port(bus);
0120     unsigned int b, d, f;
0121     u32 rtdid_val = 0;
0122 
0123     b = bus->number;
0124     d = PCI_SLOT(devfn);
0125     f = PCI_FUNC(devfn);
0126 
0127     if (!pci_is_root_bus(bus))
0128         rtdid_val = (b << 8) | (d << 3) | f;
0129 
0130     xgene_pcie_writel(port, RTDID, rtdid_val);
0131     /* read the register back to ensure flush */
0132     xgene_pcie_readl(port, RTDID);
0133 }
0134 
0135 /*
0136  * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
0137  * the translation from PCI bus to native BUS.  Entire DDR region
0138  * is mapped into PCIe space using these registers, so it can be
0139  * reached by DMA from EP devices.  The BAR0/1 of bridge should be
0140  * hidden during enumeration to avoid the sizing and resource allocation
0141  * by PCIe core.
0142  */
0143 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
0144 {
0145     if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
0146                      (offset == PCI_BASE_ADDRESS_1)))
0147         return true;
0148 
0149     return false;
0150 }
0151 
0152 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
0153                     int offset)
0154 {
0155     if ((pci_is_root_bus(bus) && devfn != 0) ||
0156         xgene_pcie_hide_rc_bars(bus, offset))
0157         return NULL;
0158 
0159     xgene_pcie_set_rtdid_reg(bus, devfn);
0160     return xgene_pcie_get_cfg_base(bus) + offset;
0161 }
0162 
0163 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
0164                     int where, int size, u32 *val)
0165 {
0166     struct xgene_pcie *port = pcie_bus_to_port(bus);
0167 
0168     if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
0169         PCIBIOS_SUCCESSFUL)
0170         return PCIBIOS_DEVICE_NOT_FOUND;
0171 
0172     /*
0173      * The v1 controller has a bug in its Configuration Request Retry
0174      * Status (CRS) logic: when CRS Software Visibility is enabled and
0175      * we read the Vendor and Device ID of a non-existent device, the
0176      * controller fabricates return data of 0xFFFF0001 ("device exists
0177      * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE)
0178      * ("device does not exist").  This causes the PCI core to retry
0179      * the read until it times out.  Avoid this by not claiming to
0180      * support CRS SV.
0181      */
0182     if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
0183         ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
0184         *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
0185 
0186     if (size <= 2)
0187         *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
0188 
0189     return PCIBIOS_SUCCESSFUL;
0190 }
0191 #endif
0192 
0193 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
0194 static int xgene_get_csr_resource(struct acpi_device *adev,
0195                   struct resource *res)
0196 {
0197     struct device *dev = &adev->dev;
0198     struct resource_entry *entry;
0199     struct list_head list;
0200     unsigned long flags;
0201     int ret;
0202 
0203     INIT_LIST_HEAD(&list);
0204     flags = IORESOURCE_MEM;
0205     ret = acpi_dev_get_resources(adev, &list,
0206                      acpi_dev_filter_resource_type_cb,
0207                      (void *) flags);
0208     if (ret < 0) {
0209         dev_err(dev, "failed to parse _CRS method, error code %d\n",
0210             ret);
0211         return ret;
0212     }
0213 
0214     if (ret == 0) {
0215         dev_err(dev, "no IO and memory resources present in _CRS\n");
0216         return -EINVAL;
0217     }
0218 
0219     entry = list_first_entry(&list, struct resource_entry, node);
0220     *res = *entry->res;
0221     acpi_dev_free_resource_list(&list);
0222     return 0;
0223 }
0224 
0225 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
0226 {
0227     struct device *dev = cfg->parent;
0228     struct acpi_device *adev = to_acpi_device(dev);
0229     struct xgene_pcie *port;
0230     struct resource csr;
0231     int ret;
0232 
0233     port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
0234     if (!port)
0235         return -ENOMEM;
0236 
0237     ret = xgene_get_csr_resource(adev, &csr);
0238     if (ret) {
0239         dev_err(dev, "can't get CSR resource\n");
0240         return ret;
0241     }
0242     port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
0243     if (IS_ERR(port->csr_base))
0244         return PTR_ERR(port->csr_base);
0245 
0246     port->cfg_base = cfg->win;
0247     port->version = ipversion;
0248 
0249     cfg->priv = port;
0250     return 0;
0251 }
0252 
0253 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
0254 {
0255     return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
0256 }
0257 
0258 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
0259     .init       = xgene_v1_pcie_ecam_init,
0260     .pci_ops    = {
0261         .map_bus    = xgene_pcie_map_bus,
0262         .read       = xgene_pcie_config_read32,
0263         .write      = pci_generic_config_write,
0264     }
0265 };
0266 
0267 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
0268 {
0269     return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
0270 }
0271 
0272 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
0273     .init       = xgene_v2_pcie_ecam_init,
0274     .pci_ops    = {
0275         .map_bus    = xgene_pcie_map_bus,
0276         .read       = xgene_pcie_config_read32,
0277         .write      = pci_generic_config_write,
0278     }
0279 };
0280 #endif
0281 
0282 #if defined(CONFIG_PCI_XGENE)
0283 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,
0284                   u32 flags, u64 size)
0285 {
0286     u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
0287     u32 val32 = 0;
0288     u32 val;
0289 
0290     val32 = xgene_pcie_readl(port, addr);
0291     val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
0292     xgene_pcie_writel(port, addr, val);
0293 
0294     val32 = xgene_pcie_readl(port, addr + 0x04);
0295     val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
0296     xgene_pcie_writel(port, addr + 0x04, val);
0297 
0298     val32 = xgene_pcie_readl(port, addr + 0x04);
0299     val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
0300     xgene_pcie_writel(port, addr + 0x04, val);
0301 
0302     val32 = xgene_pcie_readl(port, addr + 0x08);
0303     val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
0304     xgene_pcie_writel(port, addr + 0x08, val);
0305 
0306     return mask;
0307 }
0308 
0309 static void xgene_pcie_linkup(struct xgene_pcie *port,
0310                   u32 *lanes, u32 *speed)
0311 {
0312     u32 val32;
0313 
0314     port->link_up = false;
0315     val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
0316     if (val32 & LINK_UP_MASK) {
0317         port->link_up = true;
0318         *speed = PIPE_PHY_RATE_RD(val32);
0319         val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
0320         *lanes = val32 >> 26;
0321     }
0322 }
0323 
0324 static int xgene_pcie_init_port(struct xgene_pcie *port)
0325 {
0326     struct device *dev = port->dev;
0327     int rc;
0328 
0329     port->clk = clk_get(dev, NULL);
0330     if (IS_ERR(port->clk)) {
0331         dev_err(dev, "clock not available\n");
0332         return -ENODEV;
0333     }
0334 
0335     rc = clk_prepare_enable(port->clk);
0336     if (rc) {
0337         dev_err(dev, "clock enable failed\n");
0338         return rc;
0339     }
0340 
0341     return 0;
0342 }
0343 
0344 static int xgene_pcie_map_reg(struct xgene_pcie *port,
0345                   struct platform_device *pdev)
0346 {
0347     struct device *dev = port->dev;
0348     struct resource *res;
0349 
0350     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
0351     port->csr_base = devm_pci_remap_cfg_resource(dev, res);
0352     if (IS_ERR(port->csr_base))
0353         return PTR_ERR(port->csr_base);
0354 
0355     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
0356     port->cfg_base = devm_ioremap_resource(dev, res);
0357     if (IS_ERR(port->cfg_base))
0358         return PTR_ERR(port->cfg_base);
0359     port->cfg_addr = res->start;
0360 
0361     return 0;
0362 }
0363 
0364 static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,
0365                     struct resource *res, u32 offset,
0366                     u64 cpu_addr, u64 pci_addr)
0367 {
0368     struct device *dev = port->dev;
0369     resource_size_t size = resource_size(res);
0370     u64 restype = resource_type(res);
0371     u64 mask = 0;
0372     u32 min_size;
0373     u32 flag = EN_REG;
0374 
0375     if (restype == IORESOURCE_MEM) {
0376         min_size = SZ_128M;
0377     } else {
0378         min_size = 128;
0379         flag |= OB_LO_IO;
0380     }
0381 
0382     if (size >= min_size)
0383         mask = ~(size - 1) | flag;
0384     else
0385         dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
0386              (u64)size, min_size);
0387 
0388     xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
0389     xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
0390     xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
0391     xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
0392     xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
0393     xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
0394 }
0395 
0396 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)
0397 {
0398     u64 addr = port->cfg_addr;
0399 
0400     xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
0401     xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
0402     xgene_pcie_writel(port, CFGCTL, EN_REG);
0403 }
0404 
0405 static int xgene_pcie_map_ranges(struct xgene_pcie *port)
0406 {
0407     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
0408     struct resource_entry *window;
0409     struct device *dev = port->dev;
0410 
0411     resource_list_for_each_entry(window, &bridge->windows) {
0412         struct resource *res = window->res;
0413         u64 restype = resource_type(res);
0414 
0415         dev_dbg(dev, "%pR\n", res);
0416 
0417         switch (restype) {
0418         case IORESOURCE_IO:
0419             xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
0420                         pci_pio_to_address(res->start),
0421                         res->start - window->offset);
0422             break;
0423         case IORESOURCE_MEM:
0424             if (res->flags & IORESOURCE_PREFETCH)
0425                 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
0426                             res->start,
0427                             res->start -
0428                             window->offset);
0429             else
0430                 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
0431                             res->start,
0432                             res->start -
0433                             window->offset);
0434             break;
0435         case IORESOURCE_BUS:
0436             break;
0437         default:
0438             dev_err(dev, "invalid resource %pR\n", res);
0439             return -EINVAL;
0440         }
0441     }
0442     xgene_pcie_setup_cfg_reg(port);
0443     return 0;
0444 }
0445 
0446 static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,
0447                   u64 pim, u64 size)
0448 {
0449     xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
0450     xgene_pcie_writel(port, pim_reg + 0x04,
0451               upper_32_bits(pim) | EN_COHERENCY);
0452     xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
0453     xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
0454 }
0455 
0456 /*
0457  * X-Gene PCIe support maximum 3 inbound memory regions
0458  * This function helps to select a region based on size of region
0459  */
0460 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
0461 {
0462     if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
0463         *ib_reg_mask |= (1 << 1);
0464         return 1;
0465     }
0466 
0467     if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
0468         *ib_reg_mask |= (1 << 0);
0469         return 0;
0470     }
0471 
0472     if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
0473         *ib_reg_mask |= (1 << 2);
0474         return 2;
0475     }
0476 
0477     return -EINVAL;
0478 }
0479 
0480 static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,
0481                     struct of_pci_range *range, u8 *ib_reg_mask)
0482 {
0483     void __iomem *cfg_base = port->cfg_base;
0484     struct device *dev = port->dev;
0485     void __iomem *bar_addr;
0486     u32 pim_reg;
0487     u64 cpu_addr = range->cpu_addr;
0488     u64 pci_addr = range->pci_addr;
0489     u64 size = range->size;
0490     u64 mask = ~(size - 1) | EN_REG;
0491     u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
0492     u32 bar_low;
0493     int region;
0494 
0495     region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
0496     if (region < 0) {
0497         dev_warn(dev, "invalid pcie dma-range config\n");
0498         return;
0499     }
0500 
0501     if (range->flags & IORESOURCE_PREFETCH)
0502         flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
0503 
0504     bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
0505     switch (region) {
0506     case 0:
0507         xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
0508         bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
0509         writel(bar_low, bar_addr);
0510         writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
0511         pim_reg = PIM1_1L;
0512         break;
0513     case 1:
0514         xgene_pcie_writel(port, IBAR2, bar_low);
0515         xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
0516         pim_reg = PIM2_1L;
0517         break;
0518     case 2:
0519         xgene_pcie_writel(port, IBAR3L, bar_low);
0520         xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
0521         xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
0522         xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
0523         pim_reg = PIM3_1L;
0524         break;
0525     }
0526 
0527     xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
0528 }
0529 
0530 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)
0531 {
0532     struct device_node *np = port->node;
0533     struct of_pci_range range;
0534     struct of_pci_range_parser parser;
0535     struct device *dev = port->dev;
0536     u8 ib_reg_mask = 0;
0537 
0538     if (of_pci_dma_range_parser_init(&parser, np)) {
0539         dev_err(dev, "missing dma-ranges property\n");
0540         return -EINVAL;
0541     }
0542 
0543     /* Get the dma-ranges from DT */
0544     for_each_of_pci_range(&parser, &range) {
0545         u64 end = range.cpu_addr + range.size - 1;
0546 
0547         dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
0548             range.flags, range.cpu_addr, end, range.pci_addr);
0549         xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
0550     }
0551     return 0;
0552 }
0553 
0554 /* clear BAR configuration which was done by firmware */
0555 static void xgene_pcie_clear_config(struct xgene_pcie *port)
0556 {
0557     int i;
0558 
0559     for (i = PIM1_1L; i <= CFGCTL; i += 4)
0560         xgene_pcie_writel(port, i, 0);
0561 }
0562 
0563 static int xgene_pcie_setup(struct xgene_pcie *port)
0564 {
0565     struct device *dev = port->dev;
0566     u32 val, lanes = 0, speed = 0;
0567     int ret;
0568 
0569     xgene_pcie_clear_config(port);
0570 
0571     /* setup the vendor and device IDs correctly */
0572     val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC;
0573     xgene_pcie_writel(port, BRIDGE_CFG_0, val);
0574 
0575     ret = xgene_pcie_map_ranges(port);
0576     if (ret)
0577         return ret;
0578 
0579     ret = xgene_pcie_parse_map_dma_ranges(port);
0580     if (ret)
0581         return ret;
0582 
0583     xgene_pcie_linkup(port, &lanes, &speed);
0584     if (!port->link_up)
0585         dev_info(dev, "(rc) link down\n");
0586     else
0587         dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
0588     return 0;
0589 }
0590 
0591 static struct pci_ops xgene_pcie_ops = {
0592     .map_bus = xgene_pcie_map_bus,
0593     .read = xgene_pcie_config_read32,
0594     .write = pci_generic_config_write32,
0595 };
0596 
0597 static int xgene_pcie_probe(struct platform_device *pdev)
0598 {
0599     struct device *dev = &pdev->dev;
0600     struct device_node *dn = dev->of_node;
0601     struct xgene_pcie *port;
0602     struct pci_host_bridge *bridge;
0603     int ret;
0604 
0605     bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
0606     if (!bridge)
0607         return -ENOMEM;
0608 
0609     port = pci_host_bridge_priv(bridge);
0610 
0611     port->node = of_node_get(dn);
0612     port->dev = dev;
0613 
0614     port->version = XGENE_PCIE_IP_VER_UNKN;
0615     if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
0616         port->version = XGENE_PCIE_IP_VER_1;
0617 
0618     ret = xgene_pcie_map_reg(port, pdev);
0619     if (ret)
0620         return ret;
0621 
0622     ret = xgene_pcie_init_port(port);
0623     if (ret)
0624         return ret;
0625 
0626     ret = xgene_pcie_setup(port);
0627     if (ret)
0628         return ret;
0629 
0630     bridge->sysdata = port;
0631     bridge->ops = &xgene_pcie_ops;
0632 
0633     return pci_host_probe(bridge);
0634 }
0635 
0636 static const struct of_device_id xgene_pcie_match_table[] = {
0637     {.compatible = "apm,xgene-pcie",},
0638     {},
0639 };
0640 
0641 static struct platform_driver xgene_pcie_driver = {
0642     .driver = {
0643         .name = "xgene-pcie",
0644         .of_match_table = xgene_pcie_match_table,
0645         .suppress_bind_attrs = true,
0646     },
0647     .probe = xgene_pcie_probe,
0648 };
0649 builtin_platform_driver(xgene_pcie_driver);
0650 #endif
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