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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
0004  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0005  *
0006  * Based on the code from arch/arm/mach-integrator/pci_v3.c
0007  * Copyright (C) 1999 ARM Limited
0008  * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
0009  *
0010  * Contributors to the old driver include:
0011  * Russell King <linux@armlinux.org.uk>
0012  * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
0013  * Rob Herring <robh@kernel.org>
0014  * Liviu Dudau <Liviu.Dudau@arm.com>
0015  * Grant Likely <grant.likely@secretlab.ca>
0016  * Arnd Bergmann <arnd@arndb.de>
0017  * Bjorn Helgaas <bhelgaas@google.com>
0018  */
0019 #include <linux/init.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/io.h>
0022 #include <linux/kernel.h>
0023 #include <linux/of_address.h>
0024 #include <linux/of_device.h>
0025 #include <linux/of_irq.h>
0026 #include <linux/of_pci.h>
0027 #include <linux/pci.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/slab.h>
0030 #include <linux/bitops.h>
0031 #include <linux/irq.h>
0032 #include <linux/mfd/syscon.h>
0033 #include <linux/regmap.h>
0034 #include <linux/clk.h>
0035 
0036 #include "../pci.h"
0037 
0038 #define V3_PCI_VENDOR           0x00000000
0039 #define V3_PCI_DEVICE           0x00000002
0040 #define V3_PCI_CMD          0x00000004
0041 #define V3_PCI_STAT         0x00000006
0042 #define V3_PCI_CC_REV           0x00000008
0043 #define V3_PCI_HDR_CFG          0x0000000C
0044 #define V3_PCI_IO_BASE          0x00000010
0045 #define V3_PCI_BASE0            0x00000014
0046 #define V3_PCI_BASE1            0x00000018
0047 #define V3_PCI_SUB_VENDOR       0x0000002C
0048 #define V3_PCI_SUB_ID           0x0000002E
0049 #define V3_PCI_ROM          0x00000030
0050 #define V3_PCI_BPARAM           0x0000003C
0051 #define V3_PCI_MAP0         0x00000040
0052 #define V3_PCI_MAP1         0x00000044
0053 #define V3_PCI_INT_STAT         0x00000048
0054 #define V3_PCI_INT_CFG          0x0000004C
0055 #define V3_LB_BASE0         0x00000054
0056 #define V3_LB_BASE1         0x00000058
0057 #define V3_LB_MAP0          0x0000005E
0058 #define V3_LB_MAP1          0x00000062
0059 #define V3_LB_BASE2         0x00000064
0060 #define V3_LB_MAP2          0x00000066
0061 #define V3_LB_SIZE          0x00000068
0062 #define V3_LB_IO_BASE           0x0000006E
0063 #define V3_FIFO_CFG         0x00000070
0064 #define V3_FIFO_PRIORITY        0x00000072
0065 #define V3_FIFO_STAT            0x00000074
0066 #define V3_LB_ISTAT         0x00000076
0067 #define V3_LB_IMASK         0x00000077
0068 #define V3_SYSTEM           0x00000078
0069 #define V3_LB_CFG           0x0000007A
0070 #define V3_PCI_CFG          0x0000007C
0071 #define V3_DMA_PCI_ADR0         0x00000080
0072 #define V3_DMA_PCI_ADR1         0x00000090
0073 #define V3_DMA_LOCAL_ADR0       0x00000084
0074 #define V3_DMA_LOCAL_ADR1       0x00000094
0075 #define V3_DMA_LENGTH0          0x00000088
0076 #define V3_DMA_LENGTH1          0x00000098
0077 #define V3_DMA_CSR0         0x0000008B
0078 #define V3_DMA_CSR1         0x0000009B
0079 #define V3_DMA_CTLB_ADR0        0x0000008C
0080 #define V3_DMA_CTLB_ADR1        0x0000009C
0081 #define V3_DMA_DELAY            0x000000E0
0082 #define V3_MAIL_DATA            0x000000C0
0083 #define V3_PCI_MAIL_IEWR        0x000000D0
0084 #define V3_PCI_MAIL_IERD        0x000000D2
0085 #define V3_LB_MAIL_IEWR         0x000000D4
0086 #define V3_LB_MAIL_IERD         0x000000D6
0087 #define V3_MAIL_WR_STAT         0x000000D8
0088 #define V3_MAIL_RD_STAT         0x000000DA
0089 #define V3_QBA_MAP          0x000000DC
0090 
0091 /* PCI STATUS bits */
0092 #define V3_PCI_STAT_PAR_ERR     BIT(15)
0093 #define V3_PCI_STAT_SYS_ERR     BIT(14)
0094 #define V3_PCI_STAT_M_ABORT_ERR     BIT(13)
0095 #define V3_PCI_STAT_T_ABORT_ERR     BIT(12)
0096 
0097 /* LB ISTAT bits */
0098 #define V3_LB_ISTAT_MAILBOX     BIT(7)
0099 #define V3_LB_ISTAT_PCI_RD      BIT(6)
0100 #define V3_LB_ISTAT_PCI_WR      BIT(5)
0101 #define V3_LB_ISTAT_PCI_INT     BIT(4)
0102 #define V3_LB_ISTAT_PCI_PERR        BIT(3)
0103 #define V3_LB_ISTAT_I2O_QWR     BIT(2)
0104 #define V3_LB_ISTAT_DMA1        BIT(1)
0105 #define V3_LB_ISTAT_DMA0        BIT(0)
0106 
0107 /* PCI COMMAND bits */
0108 #define V3_COMMAND_M_FBB_EN     BIT(9)
0109 #define V3_COMMAND_M_SERR_EN        BIT(8)
0110 #define V3_COMMAND_M_PAR_EN     BIT(6)
0111 #define V3_COMMAND_M_MASTER_EN      BIT(2)
0112 #define V3_COMMAND_M_MEM_EN     BIT(1)
0113 #define V3_COMMAND_M_IO_EN      BIT(0)
0114 
0115 /* SYSTEM bits */
0116 #define V3_SYSTEM_M_RST_OUT     BIT(15)
0117 #define V3_SYSTEM_M_LOCK        BIT(14)
0118 #define V3_SYSTEM_UNLOCK        0xa05f
0119 
0120 /* PCI CFG bits */
0121 #define V3_PCI_CFG_M_I2O_EN     BIT(15)
0122 #define V3_PCI_CFG_M_IO_REG_DIS     BIT(14)
0123 #define V3_PCI_CFG_M_IO_DIS     BIT(13)
0124 #define V3_PCI_CFG_M_EN3V       BIT(12)
0125 #define V3_PCI_CFG_M_RETRY_EN       BIT(10)
0126 #define V3_PCI_CFG_M_AD_LOW1        BIT(9)
0127 #define V3_PCI_CFG_M_AD_LOW0        BIT(8)
0128 /*
0129  * This is the value applied to C/BE[3:1], with bit 0 always held 0
0130  * during DMA access.
0131  */
0132 #define V3_PCI_CFG_M_RTYPE_SHIFT    5
0133 #define V3_PCI_CFG_M_WTYPE_SHIFT    1
0134 #define V3_PCI_CFG_TYPE_DEFAULT     0x3
0135 
0136 /* PCI BASE bits (PCI -> Local Bus) */
0137 #define V3_PCI_BASE_M_ADR_BASE      0xFFF00000U
0138 #define V3_PCI_BASE_M_ADR_BASEL     0x000FFF00U
0139 #define V3_PCI_BASE_M_PREFETCH      BIT(3)
0140 #define V3_PCI_BASE_M_TYPE      (3 << 1)
0141 #define V3_PCI_BASE_M_IO        BIT(0)
0142 
0143 /* PCI MAP bits (PCI -> Local bus) */
0144 #define V3_PCI_MAP_M_MAP_ADR        0xFFF00000U
0145 #define V3_PCI_MAP_M_RD_POST_INH    BIT(15)
0146 #define V3_PCI_MAP_M_ROM_SIZE       (3 << 10)
0147 #define V3_PCI_MAP_M_SWAP       (3 << 8)
0148 #define V3_PCI_MAP_M_ADR_SIZE       0x000000F0U
0149 #define V3_PCI_MAP_M_REG_EN     BIT(1)
0150 #define V3_PCI_MAP_M_ENABLE     BIT(0)
0151 
0152 /* LB_BASE0,1 bits (Local bus -> PCI) */
0153 #define V3_LB_BASE_ADR_BASE     0xfff00000U
0154 #define V3_LB_BASE_SWAP         (3 << 8)
0155 #define V3_LB_BASE_ADR_SIZE     (15 << 4)
0156 #define V3_LB_BASE_PREFETCH     BIT(3)
0157 #define V3_LB_BASE_ENABLE       BIT(0)
0158 
0159 #define V3_LB_BASE_ADR_SIZE_1MB     (0 << 4)
0160 #define V3_LB_BASE_ADR_SIZE_2MB     (1 << 4)
0161 #define V3_LB_BASE_ADR_SIZE_4MB     (2 << 4)
0162 #define V3_LB_BASE_ADR_SIZE_8MB     (3 << 4)
0163 #define V3_LB_BASE_ADR_SIZE_16MB    (4 << 4)
0164 #define V3_LB_BASE_ADR_SIZE_32MB    (5 << 4)
0165 #define V3_LB_BASE_ADR_SIZE_64MB    (6 << 4)
0166 #define V3_LB_BASE_ADR_SIZE_128MB   (7 << 4)
0167 #define V3_LB_BASE_ADR_SIZE_256MB   (8 << 4)
0168 #define V3_LB_BASE_ADR_SIZE_512MB   (9 << 4)
0169 #define V3_LB_BASE_ADR_SIZE_1GB     (10 << 4)
0170 #define V3_LB_BASE_ADR_SIZE_2GB     (11 << 4)
0171 
0172 #define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
0173 
0174 /* LB_MAP0,1 bits (Local bus -> PCI) */
0175 #define V3_LB_MAP_MAP_ADR       0xfff0U
0176 #define V3_LB_MAP_TYPE          (7 << 1)
0177 #define V3_LB_MAP_AD_LOW_EN     BIT(0)
0178 
0179 #define V3_LB_MAP_TYPE_IACK     (0 << 1)
0180 #define V3_LB_MAP_TYPE_IO       (1 << 1)
0181 #define V3_LB_MAP_TYPE_MEM      (3 << 1)
0182 #define V3_LB_MAP_TYPE_CONFIG       (5 << 1)
0183 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
0184 
0185 #define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
0186 
0187 /* LB_BASE2 bits (Local bus -> PCI IO) */
0188 #define V3_LB_BASE2_ADR_BASE        0xff00U
0189 #define V3_LB_BASE2_SWAP_AUTO       (3 << 6)
0190 #define V3_LB_BASE2_ENABLE      BIT(0)
0191 
0192 #define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
0193 
0194 /* LB_MAP2 bits (Local bus -> PCI IO) */
0195 #define V3_LB_MAP2_MAP_ADR      0xff00U
0196 
0197 #define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
0198 
0199 /* FIFO priority bits */
0200 #define V3_FIFO_PRIO_LOCAL      BIT(12)
0201 #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB   BIT(10)
0202 #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1   BIT(11)
0203 #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY   (BIT(10)|BIT(11))
0204 #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB   BIT(8)
0205 #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1   BIT(9)
0206 #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY   (BIT(8)|BIT(9))
0207 #define V3_FIFO_PRIO_PCI        BIT(4)
0208 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB  BIT(2)
0209 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1  BIT(3)
0210 #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY  (BIT(2)|BIT(3))
0211 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB  BIT(0)
0212 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1  BIT(1)
0213 #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY  (BIT(0)|BIT(1))
0214 
0215 /* Local bus configuration bits */
0216 #define V3_LB_CFG_LB_TO_64_CYCLES   0x0000
0217 #define V3_LB_CFG_LB_TO_256_CYCLES  BIT(13)
0218 #define V3_LB_CFG_LB_TO_512_CYCLES  BIT(14)
0219 #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14))
0220 #define V3_LB_CFG_LB_RST        BIT(12)
0221 #define V3_LB_CFG_LB_PPC_RDY        BIT(11)
0222 #define V3_LB_CFG_LB_LB_INT     BIT(10)
0223 #define V3_LB_CFG_LB_ERR_EN     BIT(9)
0224 #define V3_LB_CFG_LB_RDY_EN     BIT(8)
0225 #define V3_LB_CFG_LB_BE_IMODE       BIT(7)
0226 #define V3_LB_CFG_LB_BE_OMODE       BIT(6)
0227 #define V3_LB_CFG_LB_ENDIAN     BIT(5)
0228 #define V3_LB_CFG_LB_PARK_EN        BIT(4)
0229 #define V3_LB_CFG_LB_FBB_DIS        BIT(2)
0230 
0231 /* ARM Integrator-specific extended control registers */
0232 #define INTEGRATOR_SC_PCI_OFFSET    0x18
0233 #define INTEGRATOR_SC_PCI_ENABLE    BIT(0)
0234 #define INTEGRATOR_SC_PCI_INTCLR    BIT(1)
0235 #define INTEGRATOR_SC_LBFADDR_OFFSET    0x20
0236 #define INTEGRATOR_SC_LBFCODE_OFFSET    0x24
0237 
0238 struct v3_pci {
0239     struct device *dev;
0240     void __iomem *base;
0241     void __iomem *config_base;
0242     u32 config_mem;
0243     u32 non_pre_mem;
0244     u32 pre_mem;
0245     phys_addr_t non_pre_bus_addr;
0246     phys_addr_t pre_bus_addr;
0247     struct regmap *map;
0248 };
0249 
0250 /*
0251  * The V3 PCI interface chip in Integrator provides several windows from
0252  * local bus memory into the PCI memory areas. Unfortunately, there
0253  * are not really enough windows for our usage, therefore we reuse
0254  * one of the windows for access to PCI configuration space. On the
0255  * Integrator/AP, the memory map is as follows:
0256  *
0257  * Local Bus Memory         Usage
0258  *
0259  * 40000000 - 4FFFFFFF      PCI memory.  256M non-prefetchable
0260  * 50000000 - 5FFFFFFF      PCI memory.  256M prefetchable
0261  * 60000000 - 60FFFFFF      PCI IO.  16M
0262  * 61000000 - 61FFFFFF      PCI Configuration. 16M
0263  *
0264  * There are three V3 windows, each described by a pair of V3 registers.
0265  * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
0266  * Base0 and Base1 can be used for any type of PCI memory access.   Base2
0267  * can be used either for PCI I/O or for I20 accesses.  By default, uHAL
0268  * uses this only for PCI IO space.
0269  *
0270  * Normally these spaces are mapped using the following base registers:
0271  *
0272  * Usage Local Bus Memory         Base/Map registers used
0273  *
0274  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
0275  * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1
0276  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
0277  * Cfg   61000000 - 61FFFFFF
0278  *
0279  * This means that I20 and PCI configuration space accesses will fail.
0280  * When PCI configuration accesses are needed (via the uHAL PCI
0281  * configuration space primitives) we must remap the spaces as follows:
0282  *
0283  * Usage Local Bus Memory         Base/Map registers used
0284  *
0285  * Mem   40000000 - 4FFFFFFF      LB_BASE0/LB_MAP0
0286  * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0
0287  * IO    60000000 - 60FFFFFF      LB_BASE2/LB_MAP2
0288  * Cfg   61000000 - 61FFFFFF      LB_BASE1/LB_MAP1
0289  *
0290  * To make this work, the code depends on overlapping windows working.
0291  * The V3 chip translates an address by checking its range within
0292  * each of the BASE/MAP pairs in turn (in ascending register number
0293  * order).  It will use the first matching pair.   So, for example,
0294  * if the same address is mapped by both LB_BASE0/LB_MAP0 and
0295  * LB_BASE1/LB_MAP1, the V3 will use the translation from
0296  * LB_BASE0/LB_MAP0.
0297  *
0298  * To allow PCI Configuration space access, the code enlarges the
0299  * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M.  This occludes
0300  * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
0301  * be remapped for use by configuration cycles.
0302  *
0303  * At the end of the PCI Configuration space accesses,
0304  * LB_BASE1/LB_MAP1 is reset to map PCI Memory.  Finally the window
0305  * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
0306  * reveal the now restored LB_BASE1/LB_MAP1 window.
0307  *
0308  * NOTE: We do not set up I2O mapping.  I suspect that this is only
0309  * for an intelligent (target) device.  Using I2O disables most of
0310  * the mappings into PCI memory.
0311  */
0312 static void __iomem *v3_map_bus(struct pci_bus *bus,
0313                 unsigned int devfn, int offset)
0314 {
0315     struct v3_pci *v3 = bus->sysdata;
0316     unsigned int address, mapaddress, busnr;
0317 
0318     busnr = bus->number;
0319     if (busnr == 0) {
0320         int slot = PCI_SLOT(devfn);
0321 
0322         /*
0323          * local bus segment so need a type 0 config cycle
0324          *
0325          * build the PCI configuration "address" with one-hot in
0326          * A31-A11
0327          *
0328          * mapaddress:
0329          *  3:1 = config cycle (101)
0330          *  0   = PCI A1 & A0 are 0 (0)
0331          */
0332         address = PCI_FUNC(devfn) << 8;
0333         mapaddress = V3_LB_MAP_TYPE_CONFIG;
0334 
0335         if (slot > 12)
0336             /*
0337              * high order bits are handled by the MAP register
0338              */
0339             mapaddress |= BIT(slot - 5);
0340         else
0341             /*
0342              * low order bits handled directly in the address
0343              */
0344             address |= BIT(slot + 11);
0345     } else {
0346         /*
0347          * not the local bus segment so need a type 1 config cycle
0348          *
0349          * address:
0350          *  23:16 = bus number
0351          *  15:11 = slot number (7:3 of devfn)
0352          *  10:8  = func number (2:0 of devfn)
0353          *
0354          * mapaddress:
0355          *  3:1 = config cycle (101)
0356          *  0   = PCI A1 & A0 from host bus (1)
0357          */
0358         mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
0359         address = (busnr << 16) | (devfn << 8);
0360     }
0361 
0362     /*
0363      * Set up base0 to see all 512Mbytes of memory space (not
0364      * prefetchable), this frees up base1 for re-use by
0365      * configuration memory
0366      */
0367     writel(v3_addr_to_lb_base(v3->non_pre_mem) |
0368            V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE,
0369            v3->base + V3_LB_BASE0);
0370 
0371     /*
0372      * Set up base1/map1 to point into configuration space.
0373      * The config mem is always 16MB.
0374      */
0375     writel(v3_addr_to_lb_base(v3->config_mem) |
0376            V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE,
0377            v3->base + V3_LB_BASE1);
0378     writew(mapaddress, v3->base + V3_LB_MAP1);
0379 
0380     return v3->config_base + address + offset;
0381 }
0382 
0383 static void v3_unmap_bus(struct v3_pci *v3)
0384 {
0385     /*
0386      * Reassign base1 for use by prefetchable PCI memory
0387      */
0388     writel(v3_addr_to_lb_base(v3->pre_mem) |
0389            V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
0390            V3_LB_BASE_ENABLE,
0391            v3->base + V3_LB_BASE1);
0392     writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
0393            V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */
0394            v3->base + V3_LB_MAP1);
0395 
0396     /*
0397      * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
0398      */
0399     writel(v3_addr_to_lb_base(v3->non_pre_mem) |
0400            V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE,
0401            v3->base + V3_LB_BASE0);
0402 }
0403 
0404 static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn,
0405                   int config, int size, u32 *value)
0406 {
0407     struct v3_pci *v3 = bus->sysdata;
0408     int ret;
0409 
0410     dev_dbg(&bus->dev,
0411         "[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
0412         PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
0413     ret = pci_generic_config_read(bus, fn, config, size, value);
0414     v3_unmap_bus(v3);
0415     return ret;
0416 }
0417 
0418 static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn,
0419                     int config, int size, u32 value)
0420 {
0421     struct v3_pci *v3 = bus->sysdata;
0422     int ret;
0423 
0424     dev_dbg(&bus->dev,
0425         "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
0426         PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
0427     ret = pci_generic_config_write(bus, fn, config, size, value);
0428     v3_unmap_bus(v3);
0429     return ret;
0430 }
0431 
0432 static struct pci_ops v3_pci_ops = {
0433     .map_bus = v3_map_bus,
0434     .read = v3_pci_read_config,
0435     .write = v3_pci_write_config,
0436 };
0437 
0438 static irqreturn_t v3_irq(int irq, void *data)
0439 {
0440     struct v3_pci *v3 = data;
0441     struct device *dev = v3->dev;
0442     u32 status;
0443 
0444     status = readw(v3->base + V3_PCI_STAT);
0445     if (status & V3_PCI_STAT_PAR_ERR)
0446         dev_err(dev, "parity error interrupt\n");
0447     if (status & V3_PCI_STAT_SYS_ERR)
0448         dev_err(dev, "system error interrupt\n");
0449     if (status & V3_PCI_STAT_M_ABORT_ERR)
0450         dev_err(dev, "master abort error interrupt\n");
0451     if (status & V3_PCI_STAT_T_ABORT_ERR)
0452         dev_err(dev, "target abort error interrupt\n");
0453     writew(status, v3->base + V3_PCI_STAT);
0454 
0455     status = readb(v3->base + V3_LB_ISTAT);
0456     if (status & V3_LB_ISTAT_MAILBOX)
0457         dev_info(dev, "PCI mailbox interrupt\n");
0458     if (status & V3_LB_ISTAT_PCI_RD)
0459         dev_err(dev, "PCI target LB->PCI READ abort interrupt\n");
0460     if (status & V3_LB_ISTAT_PCI_WR)
0461         dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n");
0462     if (status &  V3_LB_ISTAT_PCI_INT)
0463         dev_info(dev, "PCI pin interrupt\n");
0464     if (status & V3_LB_ISTAT_PCI_PERR)
0465         dev_err(dev, "PCI parity error interrupt\n");
0466     if (status & V3_LB_ISTAT_I2O_QWR)
0467         dev_info(dev, "I2O inbound post queue interrupt\n");
0468     if (status & V3_LB_ISTAT_DMA1)
0469         dev_info(dev, "DMA channel 1 interrupt\n");
0470     if (status & V3_LB_ISTAT_DMA0)
0471         dev_info(dev, "DMA channel 0 interrupt\n");
0472     /* Clear all possible interrupts on the local bus */
0473     writeb(0, v3->base + V3_LB_ISTAT);
0474     if (v3->map)
0475         regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
0476                  INTEGRATOR_SC_PCI_ENABLE |
0477                  INTEGRATOR_SC_PCI_INTCLR);
0478 
0479     return IRQ_HANDLED;
0480 }
0481 
0482 static int v3_integrator_init(struct v3_pci *v3)
0483 {
0484     unsigned int val;
0485 
0486     v3->map =
0487         syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon");
0488     if (IS_ERR(v3->map)) {
0489         dev_err(v3->dev, "no syscon\n");
0490         return -ENODEV;
0491     }
0492 
0493     regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
0494     /* Take the PCI bridge out of reset, clear IRQs */
0495     regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
0496              INTEGRATOR_SC_PCI_ENABLE |
0497              INTEGRATOR_SC_PCI_INTCLR);
0498 
0499     if (!(val & INTEGRATOR_SC_PCI_ENABLE)) {
0500         /* If we were in reset we need to sleep a bit */
0501         msleep(230);
0502 
0503         /* Set the physical base for the controller itself */
0504         writel(0x6200, v3->base + V3_LB_IO_BASE);
0505 
0506         /* Wait for the mailbox to settle after reset */
0507         do {
0508             writeb(0xaa, v3->base + V3_MAIL_DATA);
0509             writeb(0x55, v3->base + V3_MAIL_DATA + 4);
0510         } while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
0511              readb(v3->base + V3_MAIL_DATA) != 0x55);
0512     }
0513 
0514     dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
0515 
0516     return 0;
0517 }
0518 
0519 static int v3_pci_setup_resource(struct v3_pci *v3,
0520                  struct pci_host_bridge *host,
0521                  struct resource_entry *win)
0522 {
0523     struct device *dev = v3->dev;
0524     struct resource *mem;
0525     struct resource *io;
0526 
0527     switch (resource_type(win->res)) {
0528     case IORESOURCE_IO:
0529         io = win->res;
0530 
0531         /* Setup window 2 - PCI I/O */
0532         writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) |
0533                V3_LB_BASE2_ENABLE,
0534                v3->base + V3_LB_BASE2);
0535         writew(v3_addr_to_lb_map2(io->start - win->offset),
0536                v3->base + V3_LB_MAP2);
0537         break;
0538     case IORESOURCE_MEM:
0539         mem = win->res;
0540         if (mem->flags & IORESOURCE_PREFETCH) {
0541             mem->name = "V3 PCI PRE-MEM";
0542             v3->pre_mem = mem->start;
0543             v3->pre_bus_addr = mem->start - win->offset;
0544             dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n",
0545                 mem, &v3->pre_bus_addr);
0546             if (resource_size(mem) != SZ_256M) {
0547                 dev_err(dev, "prefetchable memory range is not 256MB\n");
0548                 return -EINVAL;
0549             }
0550             if (v3->non_pre_mem &&
0551                 (mem->start != v3->non_pre_mem + SZ_256M)) {
0552                 dev_err(dev,
0553                     "prefetchable memory is not adjacent to non-prefetchable memory\n");
0554                 return -EINVAL;
0555             }
0556             /* Setup window 1 - PCI prefetchable memory */
0557             writel(v3_addr_to_lb_base(v3->pre_mem) |
0558                    V3_LB_BASE_ADR_SIZE_256MB |
0559                    V3_LB_BASE_PREFETCH |
0560                    V3_LB_BASE_ENABLE,
0561                    v3->base + V3_LB_BASE1);
0562             writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
0563                    V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */
0564                    v3->base + V3_LB_MAP1);
0565         } else {
0566             mem->name = "V3 PCI NON-PRE-MEM";
0567             v3->non_pre_mem = mem->start;
0568             v3->non_pre_bus_addr = mem->start - win->offset;
0569             dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n",
0570                 mem, &v3->non_pre_bus_addr);
0571             if (resource_size(mem) != SZ_256M) {
0572                 dev_err(dev,
0573                     "non-prefetchable memory range is not 256MB\n");
0574                 return -EINVAL;
0575             }
0576             /* Setup window 0 - PCI non-prefetchable memory */
0577             writel(v3_addr_to_lb_base(v3->non_pre_mem) |
0578                    V3_LB_BASE_ADR_SIZE_256MB |
0579                    V3_LB_BASE_ENABLE,
0580                    v3->base + V3_LB_BASE0);
0581             writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
0582                    V3_LB_MAP_TYPE_MEM,
0583                    v3->base + V3_LB_MAP0);
0584         }
0585         break;
0586     case IORESOURCE_BUS:
0587         break;
0588     default:
0589         dev_info(dev, "Unknown resource type %lu\n",
0590              resource_type(win->res));
0591         break;
0592     }
0593 
0594     return 0;
0595 }
0596 
0597 static int v3_get_dma_range_config(struct v3_pci *v3,
0598                    struct resource_entry *entry,
0599                    u32 *pci_base, u32 *pci_map)
0600 {
0601     struct device *dev = v3->dev;
0602     u64 cpu_addr = entry->res->start;
0603     u64 cpu_end = entry->res->end;
0604     u64 pci_end = cpu_end - entry->offset;
0605     u64 pci_addr = entry->res->start - entry->offset;
0606     u32 val;
0607 
0608     if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
0609         dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
0610         return -EINVAL;
0611     }
0612     val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE;
0613     *pci_base = val;
0614 
0615     if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
0616         dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
0617         return -EINVAL;
0618     }
0619     val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
0620 
0621     switch (resource_size(entry->res)) {
0622     case SZ_1M:
0623         val |= V3_LB_BASE_ADR_SIZE_1MB;
0624         break;
0625     case SZ_2M:
0626         val |= V3_LB_BASE_ADR_SIZE_2MB;
0627         break;
0628     case SZ_4M:
0629         val |= V3_LB_BASE_ADR_SIZE_4MB;
0630         break;
0631     case SZ_8M:
0632         val |= V3_LB_BASE_ADR_SIZE_8MB;
0633         break;
0634     case SZ_16M:
0635         val |= V3_LB_BASE_ADR_SIZE_16MB;
0636         break;
0637     case SZ_32M:
0638         val |= V3_LB_BASE_ADR_SIZE_32MB;
0639         break;
0640     case SZ_64M:
0641         val |= V3_LB_BASE_ADR_SIZE_64MB;
0642         break;
0643     case SZ_128M:
0644         val |= V3_LB_BASE_ADR_SIZE_128MB;
0645         break;
0646     case SZ_256M:
0647         val |= V3_LB_BASE_ADR_SIZE_256MB;
0648         break;
0649     case SZ_512M:
0650         val |= V3_LB_BASE_ADR_SIZE_512MB;
0651         break;
0652     case SZ_1G:
0653         val |= V3_LB_BASE_ADR_SIZE_1GB;
0654         break;
0655     case SZ_2G:
0656         val |= V3_LB_BASE_ADR_SIZE_2GB;
0657         break;
0658     default:
0659         dev_err(v3->dev, "illegal dma memory chunk size\n");
0660         return -EINVAL;
0661     }
0662     val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE;
0663     *pci_map = val;
0664 
0665     dev_dbg(dev,
0666         "DMA MEM CPU: 0x%016llx -> 0x%016llx => "
0667         "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
0668         cpu_addr, cpu_end,
0669         pci_addr, pci_end,
0670         *pci_base, *pci_map);
0671 
0672     return 0;
0673 }
0674 
0675 static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
0676                        struct device_node *np)
0677 {
0678     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3);
0679     struct device *dev = v3->dev;
0680     struct resource_entry *entry;
0681     int i = 0;
0682 
0683     resource_list_for_each_entry(entry, &bridge->dma_ranges) {
0684         int ret;
0685         u32 pci_base, pci_map;
0686 
0687         ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map);
0688         if (ret)
0689             return ret;
0690 
0691         if (i == 0) {
0692             writel(pci_base, v3->base + V3_PCI_BASE0);
0693             writel(pci_map, v3->base + V3_PCI_MAP0);
0694         } else if (i == 1) {
0695             writel(pci_base, v3->base + V3_PCI_BASE1);
0696             writel(pci_map, v3->base + V3_PCI_MAP1);
0697         } else {
0698             dev_err(dev, "too many ranges, only two supported\n");
0699             dev_err(dev, "range %d ignored\n", i);
0700         }
0701         i++;
0702     }
0703     return 0;
0704 }
0705 
0706 static int v3_pci_probe(struct platform_device *pdev)
0707 {
0708     struct device *dev = &pdev->dev;
0709     struct device_node *np = dev->of_node;
0710     struct resource *regs;
0711     struct resource_entry *win;
0712     struct v3_pci *v3;
0713     struct pci_host_bridge *host;
0714     struct clk *clk;
0715     u16 val;
0716     int irq;
0717     int ret;
0718 
0719     host = devm_pci_alloc_host_bridge(dev, sizeof(*v3));
0720     if (!host)
0721         return -ENOMEM;
0722 
0723     host->ops = &v3_pci_ops;
0724     v3 = pci_host_bridge_priv(host);
0725     host->sysdata = v3;
0726     v3->dev = dev;
0727 
0728     /* Get and enable host clock */
0729     clk = devm_clk_get(dev, NULL);
0730     if (IS_ERR(clk)) {
0731         dev_err(dev, "clock not found\n");
0732         return PTR_ERR(clk);
0733     }
0734     ret = clk_prepare_enable(clk);
0735     if (ret) {
0736         dev_err(dev, "unable to enable clock\n");
0737         return ret;
0738     }
0739 
0740     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0741     v3->base = devm_ioremap_resource(dev, regs);
0742     if (IS_ERR(v3->base))
0743         return PTR_ERR(v3->base);
0744     /*
0745      * The hardware has a register with the physical base address
0746      * of the V3 controller itself, verify that this is the same
0747      * as the physical memory we've remapped it from.
0748      */
0749     if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
0750         dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n",
0751             readl(v3->base + V3_LB_IO_BASE), regs);
0752 
0753     /* Configuration space is 16MB directly mapped */
0754     regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0755     if (resource_size(regs) != SZ_16M) {
0756         dev_err(dev, "config mem is not 16MB!\n");
0757         return -EINVAL;
0758     }
0759     v3->config_mem = regs->start;
0760     v3->config_base = devm_ioremap_resource(dev, regs);
0761     if (IS_ERR(v3->config_base))
0762         return PTR_ERR(v3->config_base);
0763 
0764     /* Get and request error IRQ resource */
0765     irq = platform_get_irq(pdev, 0);
0766     if (irq < 0)
0767         return irq;
0768 
0769     ret = devm_request_irq(dev, irq, v3_irq, 0,
0770             "PCIv3 error", v3);
0771     if (ret < 0) {
0772         dev_err(dev,
0773             "unable to request PCIv3 error IRQ %d (%d)\n",
0774             irq, ret);
0775         return ret;
0776     }
0777 
0778     /*
0779      * Unlock V3 registers, but only if they were previously locked.
0780      */
0781     if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
0782         writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
0783 
0784     /* Disable all slave access while we set up the windows */
0785     val = readw(v3->base + V3_PCI_CMD);
0786     val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
0787     writew(val, v3->base + V3_PCI_CMD);
0788 
0789     /* Put the PCI bus into reset */
0790     val = readw(v3->base + V3_SYSTEM);
0791     val &= ~V3_SYSTEM_M_RST_OUT;
0792     writew(val, v3->base + V3_SYSTEM);
0793 
0794     /* Retry until we're ready */
0795     val = readw(v3->base + V3_PCI_CFG);
0796     val |= V3_PCI_CFG_M_RETRY_EN;
0797     writew(val, v3->base + V3_PCI_CFG);
0798 
0799     /* Set up the local bus protocol */
0800     val = readw(v3->base + V3_LB_CFG);
0801     val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */
0802     val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */
0803     val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */
0804     val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */
0805     writew(val, v3->base + V3_LB_CFG);
0806 
0807     /* Enable the PCI bus master */
0808     val = readw(v3->base + V3_PCI_CMD);
0809     val |= PCI_COMMAND_MASTER;
0810     writew(val, v3->base + V3_PCI_CMD);
0811 
0812     /* Get the I/O and memory ranges from DT */
0813     resource_list_for_each_entry(win, &host->windows) {
0814         ret = v3_pci_setup_resource(v3, host, win);
0815         if (ret) {
0816             dev_err(dev, "error setting up resources\n");
0817             return ret;
0818         }
0819     }
0820     ret = v3_pci_parse_map_dma_ranges(v3, np);
0821     if (ret)
0822         return ret;
0823 
0824     /*
0825      * Disable PCI to host IO cycles, enable I/O buffers @3.3V,
0826      * set AD_LOW0 to 1 if one of the LB_MAP registers choose
0827      * to use this (should be unused).
0828      */
0829     writel(0x00000000, v3->base + V3_PCI_IO_BASE);
0830     val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS |
0831         V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0;
0832     /*
0833      * DMA read and write from PCI bus commands types
0834      */
0835     val |=  V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT;
0836     val |=  V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT;
0837     writew(val, v3->base + V3_PCI_CFG);
0838 
0839     /*
0840      * Set the V3 FIFO such that writes have higher priority than
0841      * reads, and local bus write causes local bus read fifo flush
0842      * on aperture 1. Same for PCI.
0843      */
0844     writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 |
0845            V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 |
0846            V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 |
0847            V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1,
0848            v3->base + V3_FIFO_PRIORITY);
0849 
0850 
0851     /*
0852      * Clear any error interrupts, and enable parity and write error
0853      * interrupts
0854      */
0855     writeb(0, v3->base + V3_LB_ISTAT);
0856     val = readw(v3->base + V3_LB_CFG);
0857     val |= V3_LB_CFG_LB_LB_INT;
0858     writew(val, v3->base + V3_LB_CFG);
0859     writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
0860            v3->base + V3_LB_IMASK);
0861 
0862     /* Special Integrator initialization */
0863     if (of_device_is_compatible(np, "arm,integrator-ap-pci")) {
0864         ret = v3_integrator_init(v3);
0865         if (ret)
0866             return ret;
0867     }
0868 
0869     /* Post-init: enable PCI memory and invalidate (master already on) */
0870     val = readw(v3->base + V3_PCI_CMD);
0871     val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
0872     writew(val, v3->base + V3_PCI_CMD);
0873 
0874     /* Clear pending interrupts */
0875     writeb(0, v3->base + V3_LB_ISTAT);
0876     /* Read or write errors and parity errors cause interrupts */
0877     writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
0878            v3->base + V3_LB_IMASK);
0879 
0880     /* Take the PCI bus out of reset so devices can initialize */
0881     val = readw(v3->base + V3_SYSTEM);
0882     val |= V3_SYSTEM_M_RST_OUT;
0883     writew(val, v3->base + V3_SYSTEM);
0884 
0885     /*
0886      * Re-lock the system register.
0887      */
0888     val = readw(v3->base + V3_SYSTEM);
0889     val |= V3_SYSTEM_M_LOCK;
0890     writew(val, v3->base + V3_SYSTEM);
0891 
0892     return pci_host_probe(host);
0893 }
0894 
0895 static const struct of_device_id v3_pci_of_match[] = {
0896     {
0897         .compatible = "v3,v360epc-pci",
0898     },
0899     {},
0900 };
0901 
0902 static struct platform_driver v3_pci_driver = {
0903     .driver = {
0904         .name = "pci-v3-semi",
0905         .of_match_table = of_match_ptr(v3_pci_of_match),
0906         .suppress_bind_attrs = true,
0907     },
0908     .probe  = v3_pci_probe,
0909 };
0910 builtin_platform_driver(v3_pci_driver);
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