pci/controller/pci-thunder-pem.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2015 - 2016 Cavium, Inc.
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/pci.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_pci.h>
0012 #include <linux/pci-acpi.h>
0013 #include <linux/pci-ecam.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/io-64-nonatomic-lo-hi.h>
0016 #include "../pci.h"
0017
0018 #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
0019
0020 #define PEM_CFG_WR 0x28
0021 #define PEM_CFG_RD 0x30
0022
0023 /*
0024  * Enhanced Configuration Access Mechanism (ECAM)
0025  *
0026  * N.B. This is a non-standard platform-specific ECAM bus shift value.  For
0027  * standard values defined in the PCI Express Base Specification see
0028  * include/linux/pci-ecam.h.
0029  */
0030 #define THUNDER_PCIE_ECAM_BUS_SHIFT 24
0031
0032 struct thunder_pem_pci {
0033     u32     ea_entry[3];
0034     void __iomem    *pem_reg_base;
0035 };
0036
0037 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
0038                    int where, int size, u32 *val)
0039 {
0040     u64 read_val, tmp_val;
0041     struct pci_config_window *cfg = bus->sysdata;
0042     struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
0043
0044     if (devfn != 0 || where >= 2048)
0045         return PCIBIOS_DEVICE_NOT_FOUND;
0046
0047     /*
0048      * 32-bit accesses only.  Write the address to the low order
0049      * bits of PEM_CFG_RD, then trigger the read by reading back.
0050      * The config data lands in the upper 32-bits of PEM_CFG_RD.
0051      */
0052     read_val = where & ~3ull;
0053     writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
0054     read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
0055     read_val >>= 32;
0056
0057     /*
0058      * The config space contains some garbage, fix it up.  Also
0059      * synthesize an EA capability for the BAR used by MSI-X.
0060      */
0061     switch (where & ~3) {
0062     case 0x40:
0063         read_val &= 0xffff00ff;
0064         read_val |= 0x00007000; /* Skip MSI CAP */
0065         break;
0066     case 0x70: /* Express Cap */
0067         /*
0068          * Change PME interrupt to vector 2 on T88 where it
0069          * reads as 0, else leave it alone.
0070          */
0071         if (!(read_val & (0x1f << 25)))
0072             read_val |= (2u << 25);
0073         break;
0074     case 0xb0: /* MSI-X Cap */
0075         /* TableSize=2 or 4, Next Cap is EA */
0076         read_val &= 0xc00000ff;
0077         /*
0078          * If Express Cap(0x70) raw PME vector reads as 0 we are on
0079          * T88 and TableSize is reported as 4, else TableSize
0080          * is 2.
0081          */
0082         writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
0083         tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
0084         tmp_val >>= 32;
0085         if (!(tmp_val & (0x1f << 25)))
0086             read_val |= 0x0003bc00;
0087         else
0088             read_val |= 0x0001bc00;
0089         break;
0090     case 0xb4:
0091         /* Table offset=0, BIR=0 */
0092         read_val = 0x00000000;
0093         break;
0094     case 0xb8:
0095         /* BPA offset=0xf0000, BIR=0 */
0096         read_val = 0x000f0000;
0097         break;
0098     case 0xbc:
0099         /* EA, 1 entry, no next Cap */
0100         read_val = 0x00010014;
0101         break;
0102     case 0xc0:
0103         /* DW2 for type-1 */
0104         read_val = 0x00000000;
0105         break;
0106     case 0xc4:
0107         /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
0108         read_val = 0x80ff0003;
0109         break;
0110     case 0xc8:
0111         read_val = pem_pci->ea_entry[0];
0112         break;
0113     case 0xcc:
0114         read_val = pem_pci->ea_entry[1];
0115         break;
0116     case 0xd0:
0117         read_val = pem_pci->ea_entry[2];
0118         break;
0119     default:
0120         break;
0121     }
0122     read_val >>= (8 * (where & 3));
0123     switch (size) {
0124     case 1:
0125         read_val &= 0xff;
0126         break;
0127     case 2:
0128         read_val &= 0xffff;
0129         break;
0130     default:
0131         break;
0132     }
0133     *val = read_val;
0134     return PCIBIOS_SUCCESSFUL;
0135 }
0136
0137 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
0138                    int where, int size, u32 *val)
0139 {
0140     struct pci_config_window *cfg = bus->sysdata;
0141
0142     if (bus->number < cfg->busr.start ||
0143         bus->number > cfg->busr.end)
0144         return PCIBIOS_DEVICE_NOT_FOUND;
0145
0146     /*
0147      * The first device on the bus is the PEM PCIe bridge.
0148      * Special case its config access.
0149      */
0150     if (bus->number == cfg->busr.start)
0151         return thunder_pem_bridge_read(bus, devfn, where, size, val);
0152
0153     return pci_generic_config_read(bus, devfn, where, size, val);
0154 }
0155
0156 /*
0157  * Some of the w1c_bits below also include read-only or non-writable
0158  * reserved bits, this makes the code simpler and is OK as the bits
0159  * are not affected by writing zeros to them.
0160  */
0161 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
0162 {
0163     u32 w1c_bits = 0;
0164
0165     switch (where_aligned) {
0166     case 0x04: /* Command/Status */
0167     case 0x1c: /* Base and I/O Limit/Secondary Status */
0168         w1c_bits = 0xff000000;
0169         break;
0170     case 0x44: /* Power Management Control and Status */
0171         w1c_bits = 0xfffffe00;
0172         break;
0173     case 0x78: /* Device Control/Device Status */
0174     case 0x80: /* Link Control/Link Status */
0175     case 0x88: /* Slot Control/Slot Status */
0176     case 0x90: /* Root Status */
0177     case 0xa0: /* Link Control 2 Registers/Link Status 2 */
0178         w1c_bits = 0xffff0000;
0179         break;
0180     case 0x104: /* Uncorrectable Error Status */
0181     case 0x110: /* Correctable Error Status */
0182     case 0x130: /* Error Status */
0183     case 0x160: /* Link Control 4 */
0184         w1c_bits = 0xffffffff;
0185         break;
0186     default:
0187         break;
0188     }
0189     return w1c_bits;
0190 }
0191
0192 /* Some bits must be written to one so they appear to be read-only. */
0193 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
0194 {
0195     u32 w1_bits;
0196
0197     switch (where_aligned) {
0198     case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
0199         /* Force 32-bit I/O addressing. */
0200         w1_bits = 0x0101;
0201         break;
0202     case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
0203         /* Force 64-bit addressing */
0204         w1_bits = 0x00010001;
0205         break;
0206     default:
0207         w1_bits = 0;
0208         break;
0209     }
0210     return w1_bits;
0211 }
0212
0213 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
0214                     int where, int size, u32 val)
0215 {
0216     struct pci_config_window *cfg = bus->sysdata;
0217     struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
0218     u64 write_val, read_val;
0219     u64 where_aligned = where & ~3ull;
0220     u32 mask = 0;
0221
0222
0223     if (devfn != 0 || where >= 2048)
0224         return PCIBIOS_DEVICE_NOT_FOUND;
0225
0226     /*
0227      * 32-bit accesses only.  If the write is for a size smaller
0228      * than 32-bits, we must first read the 32-bit value and merge
0229      * in the desired bits and then write the whole 32-bits back
0230      * out.
0231      */
0232     switch (size) {
0233     case 1:
0234         writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
0235         read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
0236         read_val >>= 32;
0237         mask = ~(0xff << (8 * (where & 3)));
0238         read_val &= mask;
0239         val = (val & 0xff) << (8 * (where & 3));
0240         val |= (u32)read_val;
0241         break;
0242     case 2:
0243         writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
0244         read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
0245         read_val >>= 32;
0246         mask = ~(0xffff << (8 * (where & 3)));
0247         read_val &= mask;
0248         val = (val & 0xffff) << (8 * (where & 3));
0249         val |= (u32)read_val;
0250         break;
0251     default:
0252         break;
0253     }
0254
0255     /*
0256      * By expanding the write width to 32 bits, we may
0257      * inadvertently hit some W1C bits that were not intended to
0258      * be written.  Calculate the mask that must be applied to the
0259      * data to be written to avoid these cases.
0260      */
0261     if (mask) {
0262         u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
0263
0264         if (w1c_bits) {
0265             mask &= w1c_bits;
0266             val &= ~mask;
0267         }
0268     }
0269
0270     /*
0271      * Some bits must be read-only with value of one.  Since the
0272      * access method allows these to be cleared if a zero is
0273      * written, force them to one before writing.
0274      */
0275     val |= thunder_pem_bridge_w1_bits(where_aligned);
0276
0277     /*
0278      * Low order bits are the config address, the high order 32
0279      * bits are the data to be written.
0280      */
0281     write_val = (((u64)val) << 32) | where_aligned;
0282     writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
0283     return PCIBIOS_SUCCESSFUL;
0284 }
0285
0286 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
0287                     int where, int size, u32 val)
0288 {
0289     struct pci_config_window *cfg = bus->sysdata;
0290
0291     if (bus->number < cfg->busr.start ||
0292         bus->number > cfg->busr.end)
0293         return PCIBIOS_DEVICE_NOT_FOUND;
0294     /*
0295      * The first device on the bus is the PEM PCIe bridge.
0296      * Special case its config access.
0297      */
0298     if (bus->number == cfg->busr.start)
0299         return thunder_pem_bridge_write(bus, devfn, where, size, val);
0300
0301
0302     return pci_generic_config_write(bus, devfn, where, size, val);
0303 }
0304
0305 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
0306                 struct resource *res_pem)
0307 {
0308     struct thunder_pem_pci *pem_pci;
0309     resource_size_t bar4_start;
0310
0311     pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
0312     if (!pem_pci)
0313         return -ENOMEM;
0314
0315     pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
0316     if (!pem_pci->pem_reg_base)
0317         return -ENOMEM;
0318
0319     /*
0320      * The MSI-X BAR for the PEM and AER interrupts is located at
0321      * a fixed offset from the PEM register base.  Generate a
0322      * fragment of the synthesized Enhanced Allocation capability
0323      * structure here for the BAR.
0324      */
0325     bar4_start = res_pem->start + 0xf00000;
0326     pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
0327     pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
0328     pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
0329
0330     cfg->priv = pem_pci;
0331     return 0;
0332 }
0333
0334 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
0335
0336 #define PEM_RES_BASE        0x87e0c0000000ULL
0337 #define PEM_NODE_MASK       GENMASK_ULL(45, 44)
0338 #define PEM_INDX_MASK       GENMASK_ULL(26, 24)
0339 #define PEM_MIN_DOM_IN_NODE 4
0340 #define PEM_MAX_DOM_IN_NODE 10
0341
0342 static void thunder_pem_reserve_range(struct device *dev, int seg,
0343                       struct resource *r)
0344 {
0345     resource_size_t start = r->start, end = r->end;
0346     struct resource *res;
0347     const char *regionid;
0348
0349     regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
0350     if (!regionid)
0351         return;
0352
0353     res = request_mem_region(start, end - start + 1, regionid);
0354     if (res)
0355         res->flags &= ~IORESOURCE_BUSY;
0356     else
0357         kfree(regionid);
0358
0359     dev_info(dev, "%pR %s reserved\n", r,
0360          res ? "has been" : "could not be");
0361 }
0362
0363 static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
0364                  struct resource *res_pem)
0365 {
0366     int node = acpi_get_node(root->device->handle);
0367     int index;
0368
0369     if (node == NUMA_NO_NODE)
0370         node = 0;
0371
0372     index = root->segment - PEM_MIN_DOM_IN_NODE;
0373     index -= node * PEM_MAX_DOM_IN_NODE;
0374     res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
0375                     FIELD_PREP(PEM_INDX_MASK, index);
0376     res_pem->flags = IORESOURCE_MEM;
0377 }
0378
0379 static int thunder_pem_acpi_init(struct pci_config_window *cfg)
0380 {
0381     struct device *dev = cfg->parent;
0382     struct acpi_device *adev = to_acpi_device(dev);
0383     struct acpi_pci_root *root = acpi_driver_data(adev);
0384     struct resource *res_pem;
0385     int ret;
0386
0387     res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
0388     if (!res_pem)
0389         return -ENOMEM;
0390
0391     ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
0392
0393     /*
0394      * If we fail to gather resources it means that we run with old
0395      * FW where we need to calculate PEM-specific resources manually.
0396      */
0397     if (ret) {
0398         thunder_pem_legacy_fw(root, res_pem);
0399         /*
0400          * Reserve 64K size PEM specific resources. The full 16M range
0401          * size is required for thunder_pem_init() call.
0402          */
0403         res_pem->end = res_pem->start + SZ_64K - 1;
0404         thunder_pem_reserve_range(dev, root->segment, res_pem);
0405         res_pem->end = res_pem->start + SZ_16M - 1;
0406
0407         /* Reserve PCI configuration space as well. */
0408         thunder_pem_reserve_range(dev, root->segment, &cfg->res);
0409     }
0410
0411     return thunder_pem_init(dev, cfg, res_pem);
0412 }
0413
0414 const struct pci_ecam_ops thunder_pem_ecam_ops = {
0415     .bus_shift  = THUNDER_PCIE_ECAM_BUS_SHIFT,
0416     .init       = thunder_pem_acpi_init,
0417     .pci_ops    = {
0418         .map_bus    = pci_ecam_map_bus,
0419         .read       = thunder_pem_config_read,
0420         .write      = thunder_pem_config_write,
0421     }
0422 };
0423
0424 #endif
0425
0426 #ifdef CONFIG_PCI_HOST_THUNDER_PEM
0427
0428 static int thunder_pem_platform_init(struct pci_config_window *cfg)
0429 {
0430     struct device *dev = cfg->parent;
0431     struct platform_device *pdev = to_platform_device(dev);
0432     struct resource *res_pem;
0433
0434     if (!dev->of_node)
0435         return -EINVAL;
0436
0437     /*
0438      * The second register range is the PEM bridge to the PCIe
0439      * bus.  It has a different config access method than those
0440      * devices behind the bridge.
0441      */
0442     res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0443     if (!res_pem) {
0444         dev_err(dev, "missing \"reg[1]\"property\n");
0445         return -EINVAL;
0446     }
0447
0448     return thunder_pem_init(dev, cfg, res_pem);
0449 }
0450
0451 static const struct pci_ecam_ops pci_thunder_pem_ops = {
0452     .bus_shift  = THUNDER_PCIE_ECAM_BUS_SHIFT,
0453     .init       = thunder_pem_platform_init,
0454     .pci_ops    = {
0455         .map_bus    = pci_ecam_map_bus,
0456         .read       = thunder_pem_config_read,
0457         .write      = thunder_pem_config_write,
0458     }
0459 };
0460
0461 static const struct of_device_id thunder_pem_of_match[] = {
0462     {
0463         .compatible = "cavium,pci-host-thunder-pem",
0464         .data = &pci_thunder_pem_ops,
0465     },
0466     { },
0467 };
0468
0469 static struct platform_driver thunder_pem_driver = {
0470     .driver = {
0471         .name = KBUILD_MODNAME,
0472         .of_match_table = thunder_pem_of_match,
0473         .suppress_bind_attrs = true,
0474     },
0475     .probe = pci_host_common_probe,
0476 };
0477 builtin_platform_driver(thunder_pem_driver);
0478
0479 #endif
0480 #endif