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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2015, 2016 Cavium, Inc.
0004  */
0005 
0006 #include <linux/kernel.h>
0007 #include <linux/init.h>
0008 #include <linux/ioport.h>
0009 #include <linux/of_pci.h>
0010 #include <linux/of.h>
0011 #include <linux/pci-ecam.h>
0012 #include <linux/platform_device.h>
0013 
0014 #if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
0015 
0016 static void set_val(u32 v, int where, int size, u32 *val)
0017 {
0018     int shift = (where & 3) * 8;
0019 
0020     pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v);
0021     v >>= shift;
0022     if (size == 1)
0023         v &= 0xff;
0024     else if (size == 2)
0025         v &= 0xffff;
0026     *val = v;
0027 }
0028 
0029 static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
0030              unsigned int devfn, int where, int size, u32 *val)
0031 {
0032     void __iomem *addr;
0033     u32 v;
0034 
0035     /* Entries are 16-byte aligned; bits[2,3] select word in entry */
0036     int where_a = where & 0xc;
0037 
0038     if (where_a == 0) {
0039         set_val(e0, where, size, val);
0040         return PCIBIOS_SUCCESSFUL;
0041     }
0042     if (where_a == 0x4) {
0043         addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
0044         if (!addr)
0045             return PCIBIOS_DEVICE_NOT_FOUND;
0046 
0047         v = readl(addr);
0048         v &= ~0xf;
0049         v |= 2; /* EA entry-1. Base-L */
0050         set_val(v, where, size, val);
0051         return PCIBIOS_SUCCESSFUL;
0052     }
0053     if (where_a == 0x8) {
0054         u32 barl_orig;
0055         u32 barl_rb;
0056 
0057         addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
0058         if (!addr)
0059             return PCIBIOS_DEVICE_NOT_FOUND;
0060 
0061         barl_orig = readl(addr + 0);
0062         writel(0xffffffff, addr + 0);
0063         barl_rb = readl(addr + 0);
0064         writel(barl_orig, addr + 0);
0065         /* zeros in unsettable bits */
0066         v = ~barl_rb & ~3;
0067         v |= 0xc; /* EA entry-2. Offset-L */
0068         set_val(v, where, size, val);
0069         return PCIBIOS_SUCCESSFUL;
0070     }
0071     if (where_a == 0xc) {
0072         addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */
0073         if (!addr)
0074             return PCIBIOS_DEVICE_NOT_FOUND;
0075 
0076         v = readl(addr); /* EA entry-3. Base-H */
0077         set_val(v, where, size, val);
0078         return PCIBIOS_SUCCESSFUL;
0079     }
0080     return PCIBIOS_DEVICE_NOT_FOUND;
0081 }
0082 
0083 static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn,
0084                        int where, int size, u32 *val)
0085 {
0086     struct pci_config_window *cfg = bus->sysdata;
0087     int where_a = where & ~3;
0088     void __iomem *addr;
0089     u32 node_bits;
0090     u32 v;
0091 
0092     /* EA Base[63:32] may be missing some bits ... */
0093     switch (where_a) {
0094     case 0xa8:
0095     case 0xbc:
0096     case 0xd0:
0097     case 0xe4:
0098         break;
0099     default:
0100         return pci_generic_config_read(bus, devfn, where, size, val);
0101     }
0102 
0103     addr = bus->ops->map_bus(bus, devfn, where_a);
0104     if (!addr)
0105         return PCIBIOS_DEVICE_NOT_FOUND;
0106 
0107     v = readl(addr);
0108 
0109     /*
0110      * Bit 44 of the 64-bit Base must match the same bit in
0111      * the config space access window.  Since we are working with
0112      * the high-order 32 bits, shift everything down by 32 bits.
0113      */
0114     node_bits = upper_32_bits(cfg->res.start) & (1 << 12);
0115 
0116     v |= node_bits;
0117     set_val(v, where, size, val);
0118 
0119     return PCIBIOS_SUCCESSFUL;
0120 }
0121 
0122 static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
0123                     int where, int size, u32 *val)
0124 {
0125     u32 v;
0126     u32 vendor_device;
0127     u32 class_rev;
0128     void __iomem *addr;
0129     int cfg_type;
0130     int where_a = where & ~3;
0131 
0132     addr = bus->ops->map_bus(bus, devfn, 0xc);
0133     if (!addr)
0134         return PCIBIOS_DEVICE_NOT_FOUND;
0135 
0136     v = readl(addr);
0137 
0138     /* Check for non type-00 header */
0139     cfg_type = (v >> 16) & 0x7f;
0140 
0141     addr = bus->ops->map_bus(bus, devfn, 8);
0142     if (!addr)
0143         return PCIBIOS_DEVICE_NOT_FOUND;
0144 
0145     class_rev = readl(addr);
0146     if (class_rev == 0xffffffff)
0147         goto no_emulation;
0148 
0149     if ((class_rev & 0xff) >= 8) {
0150         /* Pass-2 handling */
0151         if (cfg_type)
0152             goto no_emulation;
0153         return thunder_ecam_p2_config_read(bus, devfn, where,
0154                            size, val);
0155     }
0156 
0157     /*
0158      * All BARs have fixed addresses specified by the EA
0159      * capability; they must return zero on read.
0160      */
0161     if (cfg_type == 0 &&
0162         ((where >= 0x10 && where < 0x2c) ||
0163          (where >= 0x1a4 && where < 0x1bc))) {
0164         /* BAR or SR-IOV BAR */
0165         *val = 0;
0166         return PCIBIOS_SUCCESSFUL;
0167     }
0168 
0169     addr = bus->ops->map_bus(bus, devfn, 0);
0170     if (!addr)
0171         return PCIBIOS_DEVICE_NOT_FOUND;
0172 
0173     vendor_device = readl(addr);
0174     if (vendor_device == 0xffffffff)
0175         goto no_emulation;
0176 
0177     pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n",
0178          vendor_device & 0xffff, vendor_device >> 16, class_rev,
0179          (unsigned int)where, devfn);
0180 
0181     /* Check for non type-00 header */
0182     if (cfg_type == 0) {
0183         bool has_msix;
0184         bool is_nic = (vendor_device == 0xa01e177d);
0185         bool is_tns = (vendor_device == 0xa01f177d);
0186 
0187         addr = bus->ops->map_bus(bus, devfn, 0x70);
0188         if (!addr)
0189             return PCIBIOS_DEVICE_NOT_FOUND;
0190 
0191         /* E_CAP */
0192         v = readl(addr);
0193         has_msix = (v & 0xff00) != 0;
0194 
0195         if (!has_msix && where_a == 0x70) {
0196             v |= 0xbc00; /* next capability is EA at 0xbc */
0197             set_val(v, where, size, val);
0198             return PCIBIOS_SUCCESSFUL;
0199         }
0200         if (where_a == 0xb0) {
0201             addr = bus->ops->map_bus(bus, devfn, where_a);
0202             if (!addr)
0203                 return PCIBIOS_DEVICE_NOT_FOUND;
0204 
0205             v = readl(addr);
0206             if (v & 0xff00)
0207                 pr_err("Bad MSIX cap header: %08x\n", v);
0208             v |= 0xbc00; /* next capability is EA at 0xbc */
0209             set_val(v, where, size, val);
0210             return PCIBIOS_SUCCESSFUL;
0211         }
0212         if (where_a == 0xbc) {
0213             if (is_nic)
0214                 v = 0x40014; /* EA last in chain, 4 entries */
0215             else if (is_tns)
0216                 v = 0x30014; /* EA last in chain, 3 entries */
0217             else if (has_msix)
0218                 v = 0x20014; /* EA last in chain, 2 entries */
0219             else
0220                 v = 0x10014; /* EA last in chain, 1 entry */
0221             set_val(v, where, size, val);
0222             return PCIBIOS_SUCCESSFUL;
0223         }
0224         if (where_a >= 0xc0 && where_a < 0xd0)
0225             /* EA entry-0. PP=0, BAR0 Size:3 */
0226             return handle_ea_bar(0x80ff0003,
0227                          0x10, bus, devfn, where,
0228                          size, val);
0229         if (where_a >= 0xd0 && where_a < 0xe0 && has_msix)
0230              /* EA entry-1. PP=0, BAR4 Size:3 */
0231             return handle_ea_bar(0x80ff0043,
0232                          0x20, bus, devfn, where,
0233                          size, val);
0234         if (where_a >= 0xe0 && where_a < 0xf0 && is_tns)
0235             /* EA entry-2. PP=0, BAR2, Size:3 */
0236             return handle_ea_bar(0x80ff0023,
0237                          0x18, bus, devfn, where,
0238                          size, val);
0239         if (where_a >= 0xe0 && where_a < 0xf0 && is_nic)
0240             /* EA entry-2. PP=4, VF_BAR0 (9), Size:3 */
0241             return handle_ea_bar(0x80ff0493,
0242                          0x1a4, bus, devfn, where,
0243                          size, val);
0244         if (where_a >= 0xf0 && where_a < 0x100 && is_nic)
0245             /* EA entry-3. PP=4, VF_BAR4 (d), Size:3 */
0246             return handle_ea_bar(0x80ff04d3,
0247                          0x1b4, bus, devfn, where,
0248                          size, val);
0249     } else if (cfg_type == 1) {
0250         bool is_rsl_bridge = devfn == 0x08;
0251         bool is_rad_bridge = devfn == 0xa0;
0252         bool is_zip_bridge = devfn == 0xa8;
0253         bool is_dfa_bridge = devfn == 0xb0;
0254         bool is_nic_bridge = devfn == 0x10;
0255 
0256         if (where_a == 0x70) {
0257             addr = bus->ops->map_bus(bus, devfn, where_a);
0258             if (!addr)
0259                 return PCIBIOS_DEVICE_NOT_FOUND;
0260 
0261             v = readl(addr);
0262             if (v & 0xff00)
0263                 pr_err("Bad PCIe cap header: %08x\n", v);
0264             v |= 0xbc00; /* next capability is EA at 0xbc */
0265             set_val(v, where, size, val);
0266             return PCIBIOS_SUCCESSFUL;
0267         }
0268         if (where_a == 0xbc) {
0269             if (is_nic_bridge)
0270                 v = 0x10014; /* EA last in chain, 1 entry */
0271             else
0272                 v = 0x00014; /* EA last in chain, no entries */
0273             set_val(v, where, size, val);
0274             return PCIBIOS_SUCCESSFUL;
0275         }
0276         if (where_a == 0xc0) {
0277             if (is_rsl_bridge || is_nic_bridge)
0278                 v = 0x0101; /* subordinate:secondary = 1:1 */
0279             else if (is_rad_bridge)
0280                 v = 0x0202; /* subordinate:secondary = 2:2 */
0281             else if (is_zip_bridge)
0282                 v = 0x0303; /* subordinate:secondary = 3:3 */
0283             else if (is_dfa_bridge)
0284                 v = 0x0404; /* subordinate:secondary = 4:4 */
0285             set_val(v, where, size, val);
0286             return PCIBIOS_SUCCESSFUL;
0287         }
0288         if (where_a == 0xc4 && is_nic_bridge) {
0289             /* Enabled, not-Write, SP=ff, PP=05, BEI=6, ES=4 */
0290             v = 0x80ff0564;
0291             set_val(v, where, size, val);
0292             return PCIBIOS_SUCCESSFUL;
0293         }
0294         if (where_a == 0xc8 && is_nic_bridge) {
0295             v = 0x00000002; /* Base-L 64-bit */
0296             set_val(v, where, size, val);
0297             return PCIBIOS_SUCCESSFUL;
0298         }
0299         if (where_a == 0xcc && is_nic_bridge) {
0300             v = 0xfffffffe; /* MaxOffset-L 64-bit */
0301             set_val(v, where, size, val);
0302             return PCIBIOS_SUCCESSFUL;
0303         }
0304         if (where_a == 0xd0 && is_nic_bridge) {
0305             v = 0x00008430; /* NIC Base-H */
0306             set_val(v, where, size, val);
0307             return PCIBIOS_SUCCESSFUL;
0308         }
0309         if (where_a == 0xd4 && is_nic_bridge) {
0310             v = 0x0000000f; /* MaxOffset-H */
0311             set_val(v, where, size, val);
0312             return PCIBIOS_SUCCESSFUL;
0313         }
0314     }
0315 no_emulation:
0316     return pci_generic_config_read(bus, devfn, where, size, val);
0317 }
0318 
0319 static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
0320                      int where, int size, u32 val)
0321 {
0322     /*
0323      * All BARs have fixed addresses; ignore BAR writes so they
0324      * don't get corrupted.
0325      */
0326     if ((where >= 0x10 && where < 0x2c) ||
0327         (where >= 0x1a4 && where < 0x1bc))
0328         /* BAR or SR-IOV BAR */
0329         return PCIBIOS_SUCCESSFUL;
0330 
0331     return pci_generic_config_write(bus, devfn, where, size, val);
0332 }
0333 
0334 const struct pci_ecam_ops pci_thunder_ecam_ops = {
0335     .pci_ops    = {
0336         .map_bus        = pci_ecam_map_bus,
0337         .read           = thunder_ecam_config_read,
0338         .write          = thunder_ecam_config_write,
0339     }
0340 };
0341 
0342 #ifdef CONFIG_PCI_HOST_THUNDER_ECAM
0343 
0344 static const struct of_device_id thunder_ecam_of_match[] = {
0345     {
0346         .compatible = "cavium,pci-host-thunder-ecam",
0347         .data = &pci_thunder_ecam_ops,
0348     },
0349     { },
0350 };
0351 
0352 static struct platform_driver thunder_ecam_driver = {
0353     .driver = {
0354         .name = KBUILD_MODNAME,
0355         .of_match_table = thunder_ecam_of_match,
0356         .suppress_bind_attrs = true,
0357     },
0358     .probe = pci_host_common_probe,
0359 };
0360 builtin_platform_driver(thunder_ecam_driver);
0361 
0362 #endif
0363 #endif
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