Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Support for Intel IXP4xx PCI host controller
0004  *
0005  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0006  *
0007  * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
0008  * Copyright (C) 2002 Intel Corporation
0009  * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
0010  * Copyright (C) 2003-2004 MontaVista Software, Inc.
0011  * Copyright (C) 2005 Deepak Saxena <dsaxena@plexity.net>
0012  * Copyright (C) 2005 Alessandro Zummo <a.zummo@towertech.it>
0013  *
0014  * TODO:
0015  * - Test IO-space access
0016  * - DMA support
0017  */
0018 
0019 #include <linux/init.h>
0020 #include <linux/io.h>
0021 #include <linux/kernel.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_device.h>
0024 #include <linux/of_pci.h>
0025 #include <linux/pci.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/slab.h>
0028 #include <linux/bits.h>
0029 
0030 /* Register offsets */
0031 #define IXP4XX_PCI_NP_AD        0x00
0032 #define IXP4XX_PCI_NP_CBE       0x04
0033 #define IXP4XX_PCI_NP_WDATA     0x08
0034 #define IXP4XX_PCI_NP_RDATA     0x0c
0035 #define IXP4XX_PCI_CRP_AD_CBE       0x10
0036 #define IXP4XX_PCI_CRP_WDATA        0x14
0037 #define IXP4XX_PCI_CRP_RDATA        0x18
0038 #define IXP4XX_PCI_CSR          0x1c
0039 #define IXP4XX_PCI_ISR          0x20
0040 #define IXP4XX_PCI_INTEN        0x24
0041 #define IXP4XX_PCI_DMACTRL      0x28
0042 #define IXP4XX_PCI_AHBMEMBASE       0x2c
0043 #define IXP4XX_PCI_AHBIOBASE        0x30
0044 #define IXP4XX_PCI_PCIMEMBASE       0x34
0045 #define IXP4XX_PCI_AHBDOORBELL      0x38
0046 #define IXP4XX_PCI_PCIDOORBELL      0x3c
0047 #define IXP4XX_PCI_ATPDMA0_AHBADDR  0x40
0048 #define IXP4XX_PCI_ATPDMA0_PCIADDR  0x44
0049 #define IXP4XX_PCI_ATPDMA0_LENADDR  0x48
0050 #define IXP4XX_PCI_ATPDMA1_AHBADDR  0x4c
0051 #define IXP4XX_PCI_ATPDMA1_PCIADDR  0x50
0052 #define IXP4XX_PCI_ATPDMA1_LENADDR  0x54
0053 
0054 /* CSR bit definitions */
0055 #define IXP4XX_PCI_CSR_HOST     BIT(0)
0056 #define IXP4XX_PCI_CSR_ARBEN        BIT(1)
0057 #define IXP4XX_PCI_CSR_ADS      BIT(2)
0058 #define IXP4XX_PCI_CSR_PDS      BIT(3)
0059 #define IXP4XX_PCI_CSR_ABE      BIT(4)
0060 #define IXP4XX_PCI_CSR_DBT      BIT(5)
0061 #define IXP4XX_PCI_CSR_ASE      BIT(8)
0062 #define IXP4XX_PCI_CSR_IC       BIT(15)
0063 #define IXP4XX_PCI_CSR_PRST     BIT(16)
0064 
0065 /* ISR (Interrupt status) Register bit definitions */
0066 #define IXP4XX_PCI_ISR_PSE      BIT(0)
0067 #define IXP4XX_PCI_ISR_PFE      BIT(1)
0068 #define IXP4XX_PCI_ISR_PPE      BIT(2)
0069 #define IXP4XX_PCI_ISR_AHBE     BIT(3)
0070 #define IXP4XX_PCI_ISR_APDC     BIT(4)
0071 #define IXP4XX_PCI_ISR_PADC     BIT(5)
0072 #define IXP4XX_PCI_ISR_ADB      BIT(6)
0073 #define IXP4XX_PCI_ISR_PDB      BIT(7)
0074 
0075 /* INTEN (Interrupt Enable) Register bit definitions */
0076 #define IXP4XX_PCI_INTEN_PSE        BIT(0)
0077 #define IXP4XX_PCI_INTEN_PFE        BIT(1)
0078 #define IXP4XX_PCI_INTEN_PPE        BIT(2)
0079 #define IXP4XX_PCI_INTEN_AHBE       BIT(3)
0080 #define IXP4XX_PCI_INTEN_APDC       BIT(4)
0081 #define IXP4XX_PCI_INTEN_PADC       BIT(5)
0082 #define IXP4XX_PCI_INTEN_ADB        BIT(6)
0083 #define IXP4XX_PCI_INTEN_PDB        BIT(7)
0084 
0085 /* Shift value for byte enable on NP cmd/byte enable register */
0086 #define IXP4XX_PCI_NP_CBE_BESL      4
0087 
0088 /* PCI commands supported by NP access unit */
0089 #define NP_CMD_IOREAD           0x2
0090 #define NP_CMD_IOWRITE          0x3
0091 #define NP_CMD_CONFIGREAD       0xa
0092 #define NP_CMD_CONFIGWRITE      0xb
0093 #define NP_CMD_MEMREAD          0x6
0094 #define NP_CMD_MEMWRITE         0x7
0095 
0096 /* Constants for CRP access into local config space */
0097 #define CRP_AD_CBE_BESL         20
0098 #define CRP_AD_CBE_WRITE    0x00010000
0099 
0100 /* Special PCI configuration space registers for this controller */
0101 #define IXP4XX_PCI_RTOTTO       0x40
0102 
0103 struct ixp4xx_pci {
0104     struct device *dev;
0105     void __iomem *base;
0106     bool errata_hammer;
0107     bool host_mode;
0108 };
0109 
0110 /*
0111  * The IXP4xx has a peculiar address bus that will change the
0112  * byte order on SoC peripherals depending on whether the device
0113  * operates in big-endian or little-endian mode. That means that
0114  * readl() and writel() that always use little-endian access
0115  * will not work for SoC peripherals such as the PCI controller
0116  * when used in big-endian mode. The accesses to the individual
0117  * PCI devices on the other hand, are always little-endian and
0118  * can use readl() and writel().
0119  *
0120  * For local AHB bus access we need to use __raw_[readl|writel]()
0121  * to make sure that we access the SoC devices in the CPU native
0122  * endianness.
0123  */
0124 static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg)
0125 {
0126     return __raw_readl(p->base + reg);
0127 }
0128 
0129 static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val)
0130 {
0131     __raw_writel(val, p->base + reg);
0132 }
0133 
0134 static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p)
0135 {
0136     u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR);
0137 
0138     if (isr & IXP4XX_PCI_ISR_PFE) {
0139         /* Make sure the master abort bit is reset */
0140         ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE);
0141         dev_dbg(p->dev, "master abort detected\n");
0142         return -EINVAL;
0143     }
0144 
0145     return 0;
0146 }
0147 
0148 static int ixp4xx_pci_read_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data)
0149 {
0150     ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr);
0151 
0152     if (p->errata_hammer) {
0153         int i;
0154 
0155         /*
0156          * PCI workaround - only works if NP PCI space reads have
0157          * no side effects. Hammer the register and read twice 8
0158          * times. last one will be good.
0159          */
0160         for (i = 0; i < 8; i++) {
0161             ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
0162             *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
0163             *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
0164         }
0165     } else {
0166         ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
0167         *data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA);
0168     }
0169 
0170     return ixp4xx_pci_check_master_abort(p);
0171 }
0172 
0173 static int ixp4xx_pci_write_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data)
0174 {
0175     ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr);
0176 
0177     /* Set up the write */
0178     ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd);
0179 
0180     /* Execute the write by writing to NP_WDATA */
0181     ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data);
0182 
0183     return ixp4xx_pci_check_master_abort(p);
0184 }
0185 
0186 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
0187 {
0188     /* Root bus is always 0 in this hardware */
0189     if (bus_num == 0) {
0190         /* type 0 */
0191         return BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
0192             (where & ~3);
0193     } else {
0194         /* type 1 */
0195         return (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
0196             ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
0197     }
0198 }
0199 
0200 /*
0201  * CRP functions are "Controller Configuration Port" accesses
0202  * initiated from within this driver itself to read/write PCI
0203  * control information in the config space.
0204  */
0205 static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size)
0206 {
0207     if (size == 1)
0208         return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
0209     if (size == 2)
0210         return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
0211     if (size == 4)
0212         return 0;
0213     return 0xffffffff;
0214 }
0215 
0216 static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size,
0217                   u32 *value)
0218 {
0219     u32 n, cmd, val;
0220 
0221     n = where % 4;
0222     cmd = where & ~3;
0223 
0224     dev_dbg(p->dev, "%s from %d size %d cmd %08x\n",
0225         __func__, where, size, cmd);
0226 
0227     ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd);
0228     val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA);
0229 
0230     val >>= (8*n);
0231     switch (size) {
0232     case 1:
0233         val &= U8_MAX;
0234         dev_dbg(p->dev, "%s read byte %02x\n", __func__, val);
0235         break;
0236     case 2:
0237         val &= U16_MAX;
0238         dev_dbg(p->dev, "%s read word %04x\n", __func__, val);
0239         break;
0240     case 4:
0241         val &= U32_MAX;
0242         dev_dbg(p->dev, "%s read long %08x\n", __func__, val);
0243         break;
0244     default:
0245         /* Should not happen */
0246         dev_err(p->dev, "%s illegal size\n", __func__);
0247         return PCIBIOS_DEVICE_NOT_FOUND;
0248     }
0249     *value = val;
0250 
0251     return PCIBIOS_SUCCESSFUL;
0252 }
0253 
0254 static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size,
0255                    u32 value)
0256 {
0257     u32 n, cmd, val;
0258 
0259     n = where % 4;
0260     cmd = ixp4xx_crp_byte_lane_enable_bits(n, size);
0261     if (cmd == 0xffffffff)
0262         return PCIBIOS_BAD_REGISTER_NUMBER;
0263     cmd |= where & ~3;
0264     cmd |= CRP_AD_CBE_WRITE;
0265 
0266     val = value << (8*n);
0267 
0268     dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n",
0269         __func__, where, size, cmd, val);
0270 
0271     ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd);
0272     ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val);
0273 
0274     return PCIBIOS_SUCCESSFUL;
0275 }
0276 
0277 /*
0278  * Then follows the functions that read and write from the common PCI
0279  * configuration space.
0280  */
0281 static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size)
0282 {
0283     if (size == 1)
0284         return (0xf & ~BIT(n)) << 4;
0285     if (size == 2)
0286         return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
0287     if (size == 4)
0288         return 0;
0289     return 0xffffffff;
0290 }
0291 
0292 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
0293                   int where, int size, u32 *value)
0294 {
0295     struct ixp4xx_pci *p = bus->sysdata;
0296     u32 n, addr, val, cmd;
0297     u8 bus_num = bus->number;
0298     int ret;
0299 
0300     *value = 0xffffffff;
0301     n = where % 4;
0302     cmd = ixp4xx_byte_lane_enable_bits(n, size);
0303     if (cmd == 0xffffffff)
0304         return PCIBIOS_BAD_REGISTER_NUMBER;
0305 
0306     addr = ixp4xx_config_addr(bus_num, devfn, where);
0307     cmd |= NP_CMD_CONFIGREAD;
0308     dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n",
0309         where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd);
0310 
0311     ret = ixp4xx_pci_read_indirect(p, addr, cmd, &val);
0312     if (ret)
0313         return PCIBIOS_DEVICE_NOT_FOUND;
0314 
0315     val >>= (8*n);
0316     switch (size) {
0317     case 1:
0318         val &= U8_MAX;
0319         dev_dbg(p->dev, "%s read byte %02x\n", __func__, val);
0320         break;
0321     case 2:
0322         val &= U16_MAX;
0323         dev_dbg(p->dev, "%s read word %04x\n", __func__, val);
0324         break;
0325     case 4:
0326         val &= U32_MAX;
0327         dev_dbg(p->dev, "%s read long %08x\n", __func__, val);
0328         break;
0329     default:
0330         /* Should not happen */
0331         dev_err(p->dev, "%s illegal size\n", __func__);
0332         return PCIBIOS_DEVICE_NOT_FOUND;
0333     }
0334     *value = val;
0335 
0336     return PCIBIOS_SUCCESSFUL;
0337 }
0338 
0339 static int ixp4xx_pci_write_config(struct pci_bus *bus,  unsigned int devfn,
0340                    int where, int size, u32 value)
0341 {
0342     struct ixp4xx_pci *p = bus->sysdata;
0343     u32 n, addr, val, cmd;
0344     u8 bus_num = bus->number;
0345     int ret;
0346 
0347     n = where % 4;
0348     cmd = ixp4xx_byte_lane_enable_bits(n, size);
0349     if (cmd == 0xffffffff)
0350         return PCIBIOS_BAD_REGISTER_NUMBER;
0351 
0352     addr = ixp4xx_config_addr(bus_num, devfn, where);
0353     cmd |= NP_CMD_CONFIGWRITE;
0354     val = value << (8*n);
0355 
0356     dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n",
0357         value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd);
0358 
0359     ret = ixp4xx_pci_write_indirect(p, addr, cmd, val);
0360     if (ret)
0361         return PCIBIOS_DEVICE_NOT_FOUND;
0362 
0363     return PCIBIOS_SUCCESSFUL;
0364 }
0365 
0366 static struct pci_ops ixp4xx_pci_ops = {
0367     .read = ixp4xx_pci_read_config,
0368     .write = ixp4xx_pci_write_config,
0369 };
0370 
0371 static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr)
0372 {
0373     u8 base;
0374 
0375     base = ((addr & 0xff000000) >> 24);
0376     return (base << 24) | ((base + 1) << 16)
0377         | ((base + 2) << 8) | (base + 3);
0378 }
0379 
0380 static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p)
0381 {
0382     struct device *dev = p->dev;
0383     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
0384     struct resource_entry *win;
0385     struct resource *res;
0386     phys_addr_t addr;
0387 
0388     win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
0389     if (win) {
0390         u32 pcimembase;
0391 
0392         res = win->res;
0393         addr = res->start - win->offset;
0394 
0395         if (res->flags & IORESOURCE_PREFETCH)
0396             res->name = "IXP4xx PCI PRE-MEM";
0397         else
0398             res->name = "IXP4xx PCI NON-PRE-MEM";
0399 
0400         dev_dbg(dev, "%s window %pR, bus addr %pa\n",
0401             res->name, res, &addr);
0402         if (resource_size(res) != SZ_64M) {
0403             dev_err(dev, "memory range is not 64MB\n");
0404             return -EINVAL;
0405         }
0406 
0407         pcimembase = ixp4xx_pci_addr_to_64mconf(addr);
0408         /* Commit configuration */
0409         ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase);
0410     } else {
0411         dev_err(dev, "no AHB memory mapping defined\n");
0412     }
0413 
0414     win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
0415     if (win) {
0416         res = win->res;
0417 
0418         addr = pci_pio_to_address(res->start);
0419         if (addr & 0xff) {
0420             dev_err(dev, "IO mem at uneven address: %pa\n", &addr);
0421             return -EINVAL;
0422         }
0423 
0424         res->name = "IXP4xx PCI IO MEM";
0425         /*
0426          * Setup I/O space location for PCI->AHB access, the
0427          * upper 24 bits of the address goes into the lower
0428          * 24 bits of this register.
0429          */
0430         ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8));
0431     } else {
0432         dev_info(dev, "no IO space AHB memory mapping defined\n");
0433     }
0434 
0435     return 0;
0436 }
0437 
0438 static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p)
0439 {
0440     struct device *dev = p->dev;
0441     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
0442     struct resource_entry *win;
0443     struct resource *res;
0444     phys_addr_t addr;
0445     u32 ahbmembase;
0446 
0447     win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM);
0448     if (win) {
0449         res = win->res;
0450         addr = res->start - win->offset;
0451 
0452         if (resource_size(res) != SZ_64M) {
0453             dev_err(dev, "DMA memory range is not 64MB\n");
0454             return -EINVAL;
0455         }
0456 
0457         dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr);
0458         /*
0459          * 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits
0460          * into each byte of the PCI_AHBMEMBASE register.
0461          */
0462         ahbmembase = ixp4xx_pci_addr_to_64mconf(addr);
0463         /* Commit AHB membase */
0464         ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase);
0465     } else {
0466         dev_err(dev, "no DMA memory range defined\n");
0467     }
0468 
0469     return 0;
0470 }
0471 
0472 /* Only used to get context for abort handling */
0473 static struct ixp4xx_pci *ixp4xx_pci_abort_singleton;
0474 
0475 static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr,
0476                     struct pt_regs *regs)
0477 {
0478     struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton;
0479     u32 isr, status;
0480     int ret;
0481 
0482     isr = ixp4xx_readl(p, IXP4XX_PCI_ISR);
0483     ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status);
0484     if (ret) {
0485         dev_err(p->dev, "unable to read abort status\n");
0486         return -EINVAL;
0487     }
0488 
0489     dev_err(p->dev,
0490         "PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n",
0491         addr, isr, status);
0492 
0493     /* Make sure the Master Abort bit is reset */
0494     ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE);
0495     status |= PCI_STATUS_REC_MASTER_ABORT;
0496     ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status);
0497     if (ret)
0498         dev_err(p->dev, "unable to clear abort status bit\n");
0499 
0500     /*
0501      * If it was an imprecise abort, then we need to correct the
0502      * return address to be _after_ the instruction.
0503      */
0504     if (fsr & (1 << 10)) {
0505         dev_err(p->dev, "imprecise abort\n");
0506         regs->ARM_pc += 4;
0507     }
0508 
0509     return 0;
0510 }
0511 
0512 static int __init ixp4xx_pci_probe(struct platform_device *pdev)
0513 {
0514     struct device *dev = &pdev->dev;
0515     struct device_node *np = dev->of_node;
0516     struct ixp4xx_pci *p;
0517     struct pci_host_bridge *host;
0518     int ret;
0519     u32 val;
0520     phys_addr_t addr;
0521     u32 basereg[4] = {
0522         PCI_BASE_ADDRESS_0,
0523         PCI_BASE_ADDRESS_1,
0524         PCI_BASE_ADDRESS_2,
0525         PCI_BASE_ADDRESS_3,
0526     };
0527     int i;
0528 
0529     host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
0530     if (!host)
0531         return -ENOMEM;
0532 
0533     host->ops = &ixp4xx_pci_ops;
0534     p = pci_host_bridge_priv(host);
0535     host->sysdata = p;
0536     p->dev = dev;
0537     dev_set_drvdata(dev, p);
0538 
0539     /*
0540      * Set up quirk for erratic behaviour in the 42x variant
0541      * when accessing config space.
0542      */
0543     if (of_device_is_compatible(np, "intel,ixp42x-pci")) {
0544         p->errata_hammer = true;
0545         dev_info(dev, "activate hammering errata\n");
0546     }
0547 
0548     p->base = devm_platform_ioremap_resource(pdev, 0);
0549     if (IS_ERR(p->base))
0550         return PTR_ERR(p->base);
0551 
0552     val = ixp4xx_readl(p, IXP4XX_PCI_CSR);
0553     p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST);
0554     dev_info(dev, "controller is in %s mode\n",
0555          p->host_mode ? "host" : "option");
0556 
0557     /* Hook in our fault handler for PCI errors */
0558     ixp4xx_pci_abort_singleton = p;
0559     hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0,
0560             "imprecise external abort");
0561 
0562     ret = ixp4xx_pci_parse_map_ranges(p);
0563     if (ret)
0564         return ret;
0565 
0566     ret = ixp4xx_pci_parse_map_dma_ranges(p);
0567     if (ret)
0568         return ret;
0569 
0570     /* This is only configured in host mode */
0571     if (p->host_mode) {
0572         addr = __pa(PAGE_OFFSET);
0573         /* This is a noop (0x00) but explains what is going on */
0574         addr |= PCI_BASE_ADDRESS_SPACE_MEMORY;
0575 
0576         for (i = 0; i < 4; i++) {
0577             /* Write this directly into the config space */
0578             ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr);
0579             if (ret)
0580                 dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i);
0581             else
0582                 dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr);
0583             addr += SZ_16M;
0584         }
0585 
0586         /*
0587          * Enable CSR window at 64 MiB to allow PCI masters to continue
0588          * prefetching past the 64 MiB boundary, if all AHB to PCI
0589          * windows are consecutive.
0590          */
0591         ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr);
0592         if (ret)
0593             dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n");
0594         else
0595             dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr);
0596 
0597         /*
0598          * Put the IO memory window at the very end of physical memory
0599          * at 0xfffffc00. This is when the system is trying to access IO
0600          * memory over AHB.
0601          */
0602         addr = 0xfffffc00;
0603         addr |= PCI_BASE_ADDRESS_SPACE_IO;
0604         ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr);
0605         if (ret)
0606             dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n");
0607         else
0608             dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr);
0609 
0610         /*
0611          * Retry timeout to 0x80
0612          * Transfer ready timeout to 0xff
0613          */
0614         ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4,
0615                           0x000080ff);
0616         if (ret)
0617             dev_err(dev, "failed to set up TRDY limit\n");
0618         else
0619             dev_info(dev, "set TRDY limit to 0x80ff\n");
0620     }
0621 
0622     /* Clear interrupts */
0623     val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE;
0624     ixp4xx_writel(p, IXP4XX_PCI_ISR, val);
0625 
0626     /*
0627      * Set Initialize Complete in PCI Control Register: allow IXP4XX to
0628      * generate PCI configuration cycles. Specify that the AHB bus is
0629      * operating in big-endian mode. Set up byte lane swapping between
0630      * little-endian PCI and the big-endian AHB bus.
0631      */
0632     val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE;
0633     if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
0634         val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS);
0635     ixp4xx_writel(p, IXP4XX_PCI_CSR, val);
0636 
0637     ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
0638     if (ret)
0639         dev_err(dev, "unable to initialize master and command memory\n");
0640     else
0641         dev_info(dev, "initialized as master\n");
0642 
0643     pci_host_probe(host);
0644 
0645     return 0;
0646 }
0647 
0648 static const struct of_device_id ixp4xx_pci_of_match[] = {
0649     {
0650         .compatible = "intel,ixp42x-pci",
0651     },
0652     {
0653         .compatible = "intel,ixp43x-pci",
0654     },
0655     {},
0656 };
0657 
0658 /*
0659  * This driver needs to be a builtin module with suppressed bind
0660  * attributes since the probe() is initializing a hard exception
0661  * handler and this can only be done from __init-tagged code
0662  * sections. This module cannot be removed and inserted at all.
0663  */
0664 static struct platform_driver ixp4xx_pci_driver = {
0665     .driver = {
0666         .name = "ixp4xx-pci",
0667         .suppress_bind_attrs = true,
0668         .of_match_table = ixp4xx_pci_of_match,
0669     },
0670 };
0671 builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!