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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Support for Faraday Technology FTPC100 PCI Controller
0004  *
0005  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0006  *
0007  * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
0008  * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
0009  * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
0010  * Based on SL2312 PCI controller code
0011  * Storlink (C) 2003
0012  */
0013 
0014 #include <linux/init.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/kernel.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/of_pci.h>
0022 #include <linux/pci.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/slab.h>
0025 #include <linux/irqdomain.h>
0026 #include <linux/irqchip/chained_irq.h>
0027 #include <linux/bitops.h>
0028 #include <linux/irq.h>
0029 #include <linux/clk.h>
0030 
0031 #include "../pci.h"
0032 
0033 /*
0034  * Special configuration registers directly in the first few words
0035  * in I/O space.
0036  */
0037 #define FTPCI_IOSIZE    0x00
0038 #define FTPCI_PROT  0x04 /* AHB protection */
0039 #define FTPCI_CTRL  0x08 /* PCI control signal */
0040 #define FTPCI_SOFTRST   0x10 /* Soft reset counter and response error enable */
0041 #define FTPCI_CONFIG    0x28 /* PCI configuration command register */
0042 #define FTPCI_DATA  0x2C
0043 
0044 #define FARADAY_PCI_STATUS_CMD      0x04 /* Status and command */
0045 #define FARADAY_PCI_PMC         0x40 /* Power management control */
0046 #define FARADAY_PCI_PMCSR       0x44 /* Power management status */
0047 #define FARADAY_PCI_CTRL1       0x48 /* Control register 1 */
0048 #define FARADAY_PCI_CTRL2       0x4C /* Control register 2 */
0049 #define FARADAY_PCI_MEM1_BASE_SIZE  0x50 /* Memory base and size #1 */
0050 #define FARADAY_PCI_MEM2_BASE_SIZE  0x54 /* Memory base and size #2 */
0051 #define FARADAY_PCI_MEM3_BASE_SIZE  0x58 /* Memory base and size #3 */
0052 
0053 #define PCI_STATUS_66MHZ_CAPABLE    BIT(21)
0054 
0055 /* Bits 31..28 gives INTD..INTA status */
0056 #define PCI_CTRL2_INTSTS_SHIFT      28
0057 #define PCI_CTRL2_INTMASK_CMDERR    BIT(27)
0058 #define PCI_CTRL2_INTMASK_PARERR    BIT(26)
0059 /* Bits 25..22 masks INTD..INTA */
0060 #define PCI_CTRL2_INTMASK_SHIFT     22
0061 #define PCI_CTRL2_INTMASK_MABRT_RX  BIT(21)
0062 #define PCI_CTRL2_INTMASK_TABRT_RX  BIT(20)
0063 #define PCI_CTRL2_INTMASK_TABRT_TX  BIT(19)
0064 #define PCI_CTRL2_INTMASK_RETRY4    BIT(18)
0065 #define PCI_CTRL2_INTMASK_SERR_RX   BIT(17)
0066 #define PCI_CTRL2_INTMASK_PERR_RX   BIT(16)
0067 /* Bit 15 reserved */
0068 #define PCI_CTRL2_MSTPRI_REQ6       BIT(14)
0069 #define PCI_CTRL2_MSTPRI_REQ5       BIT(13)
0070 #define PCI_CTRL2_MSTPRI_REQ4       BIT(12)
0071 #define PCI_CTRL2_MSTPRI_REQ3       BIT(11)
0072 #define PCI_CTRL2_MSTPRI_REQ2       BIT(10)
0073 #define PCI_CTRL2_MSTPRI_REQ1       BIT(9)
0074 #define PCI_CTRL2_MSTPRI_REQ0       BIT(8)
0075 /* Bits 7..4 reserved */
0076 /* Bits 3..0 TRDYW */
0077 
0078 /*
0079  * Memory configs:
0080  * Bit 31..20 defines the PCI side memory base
0081  * Bit 19..16 (4 bits) defines the size per below
0082  */
0083 #define FARADAY_PCI_MEMBASE_MASK    0xfff00000
0084 #define FARADAY_PCI_MEMSIZE_1MB     0x0
0085 #define FARADAY_PCI_MEMSIZE_2MB     0x1
0086 #define FARADAY_PCI_MEMSIZE_4MB     0x2
0087 #define FARADAY_PCI_MEMSIZE_8MB     0x3
0088 #define FARADAY_PCI_MEMSIZE_16MB    0x4
0089 #define FARADAY_PCI_MEMSIZE_32MB    0x5
0090 #define FARADAY_PCI_MEMSIZE_64MB    0x6
0091 #define FARADAY_PCI_MEMSIZE_128MB   0x7
0092 #define FARADAY_PCI_MEMSIZE_256MB   0x8
0093 #define FARADAY_PCI_MEMSIZE_512MB   0x9
0094 #define FARADAY_PCI_MEMSIZE_1GB     0xa
0095 #define FARADAY_PCI_MEMSIZE_2GB     0xb
0096 #define FARADAY_PCI_MEMSIZE_SHIFT   16
0097 
0098 /*
0099  * The DMA base is set to 0x0 for all memory segments, it reflects the
0100  * fact that the memory of the host system starts at 0x0.
0101  */
0102 #define FARADAY_PCI_DMA_MEM1_BASE   0x00000000
0103 #define FARADAY_PCI_DMA_MEM2_BASE   0x00000000
0104 #define FARADAY_PCI_DMA_MEM3_BASE   0x00000000
0105 
0106 /* Defines for PCI configuration command register */
0107 #define PCI_CONF_ENABLE     BIT(31)
0108 #define PCI_CONF_WHERE(r)   ((r) & 0xFC)
0109 #define PCI_CONF_BUS(b)     (((b) & 0xFF) << 16)
0110 #define PCI_CONF_DEVICE(d)  (((d) & 0x1F) << 11)
0111 #define PCI_CONF_FUNCTION(f)    (((f) & 0x07) << 8)
0112 
0113 /**
0114  * struct faraday_pci_variant - encodes IP block differences
0115  * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
0116  *  embedded in the host bridge.
0117  */
0118 struct faraday_pci_variant {
0119     bool cascaded_irq;
0120 };
0121 
0122 struct faraday_pci {
0123     struct device *dev;
0124     void __iomem *base;
0125     struct irq_domain *irqdomain;
0126     struct pci_bus *bus;
0127     struct clk *bus_clk;
0128 };
0129 
0130 static int faraday_res_to_memcfg(resource_size_t mem_base,
0131                  resource_size_t mem_size, u32 *val)
0132 {
0133     u32 outval;
0134 
0135     switch (mem_size) {
0136     case SZ_1M:
0137         outval = FARADAY_PCI_MEMSIZE_1MB;
0138         break;
0139     case SZ_2M:
0140         outval = FARADAY_PCI_MEMSIZE_2MB;
0141         break;
0142     case SZ_4M:
0143         outval = FARADAY_PCI_MEMSIZE_4MB;
0144         break;
0145     case SZ_8M:
0146         outval = FARADAY_PCI_MEMSIZE_8MB;
0147         break;
0148     case SZ_16M:
0149         outval = FARADAY_PCI_MEMSIZE_16MB;
0150         break;
0151     case SZ_32M:
0152         outval = FARADAY_PCI_MEMSIZE_32MB;
0153         break;
0154     case SZ_64M:
0155         outval = FARADAY_PCI_MEMSIZE_64MB;
0156         break;
0157     case SZ_128M:
0158         outval = FARADAY_PCI_MEMSIZE_128MB;
0159         break;
0160     case SZ_256M:
0161         outval = FARADAY_PCI_MEMSIZE_256MB;
0162         break;
0163     case SZ_512M:
0164         outval = FARADAY_PCI_MEMSIZE_512MB;
0165         break;
0166     case SZ_1G:
0167         outval = FARADAY_PCI_MEMSIZE_1GB;
0168         break;
0169     case SZ_2G:
0170         outval = FARADAY_PCI_MEMSIZE_2GB;
0171         break;
0172     default:
0173         return -EINVAL;
0174     }
0175     outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
0176 
0177     /* This is probably not good */
0178     if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
0179         pr_warn("truncated PCI memory base\n");
0180     /* Translate to bridge side address space */
0181     outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
0182     pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
0183          &mem_base, &mem_size, outval);
0184 
0185     *val = outval;
0186     return 0;
0187 }
0188 
0189 static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
0190                        unsigned int fn, int config, int size,
0191                        u32 *value)
0192 {
0193     writel(PCI_CONF_BUS(bus_number) |
0194             PCI_CONF_DEVICE(PCI_SLOT(fn)) |
0195             PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
0196             PCI_CONF_WHERE(config) |
0197             PCI_CONF_ENABLE,
0198             p->base + FTPCI_CONFIG);
0199 
0200     *value = readl(p->base + FTPCI_DATA);
0201 
0202     if (size == 1)
0203         *value = (*value >> (8 * (config & 3))) & 0xFF;
0204     else if (size == 2)
0205         *value = (*value >> (8 * (config & 3))) & 0xFFFF;
0206 
0207     return PCIBIOS_SUCCESSFUL;
0208 }
0209 
0210 static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
0211                    int config, int size, u32 *value)
0212 {
0213     struct faraday_pci *p = bus->sysdata;
0214 
0215     dev_dbg(&bus->dev,
0216         "[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
0217         PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
0218 
0219     return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
0220 }
0221 
0222 static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
0223                      unsigned int fn, int config, int size,
0224                      u32 value)
0225 {
0226     int ret = PCIBIOS_SUCCESSFUL;
0227 
0228     writel(PCI_CONF_BUS(bus_number) |
0229             PCI_CONF_DEVICE(PCI_SLOT(fn)) |
0230             PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
0231             PCI_CONF_WHERE(config) |
0232             PCI_CONF_ENABLE,
0233             p->base + FTPCI_CONFIG);
0234 
0235     switch (size) {
0236     case 4:
0237         writel(value, p->base + FTPCI_DATA);
0238         break;
0239     case 2:
0240         writew(value, p->base + FTPCI_DATA + (config & 3));
0241         break;
0242     case 1:
0243         writeb(value, p->base + FTPCI_DATA + (config & 3));
0244         break;
0245     default:
0246         ret = PCIBIOS_BAD_REGISTER_NUMBER;
0247     }
0248 
0249     return ret;
0250 }
0251 
0252 static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
0253                     int config, int size, u32 value)
0254 {
0255     struct faraday_pci *p = bus->sysdata;
0256 
0257     dev_dbg(&bus->dev,
0258         "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
0259         PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
0260 
0261     return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
0262                         value);
0263 }
0264 
0265 static struct pci_ops faraday_pci_ops = {
0266     .read   = faraday_pci_read_config,
0267     .write  = faraday_pci_write_config,
0268 };
0269 
0270 static void faraday_pci_ack_irq(struct irq_data *d)
0271 {
0272     struct faraday_pci *p = irq_data_get_irq_chip_data(d);
0273     unsigned int reg;
0274 
0275     faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
0276     reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
0277     reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
0278     faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
0279 }
0280 
0281 static void faraday_pci_mask_irq(struct irq_data *d)
0282 {
0283     struct faraday_pci *p = irq_data_get_irq_chip_data(d);
0284     unsigned int reg;
0285 
0286     faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
0287     reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
0288          | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
0289     faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
0290 }
0291 
0292 static void faraday_pci_unmask_irq(struct irq_data *d)
0293 {
0294     struct faraday_pci *p = irq_data_get_irq_chip_data(d);
0295     unsigned int reg;
0296 
0297     faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
0298     reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
0299     reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
0300     faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
0301 }
0302 
0303 static void faraday_pci_irq_handler(struct irq_desc *desc)
0304 {
0305     struct faraday_pci *p = irq_desc_get_handler_data(desc);
0306     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0307     unsigned int irq_stat, reg, i;
0308 
0309     faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
0310     irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
0311 
0312     chained_irq_enter(irqchip, desc);
0313 
0314     for (i = 0; i < 4; i++) {
0315         if ((irq_stat & BIT(i)) == 0)
0316             continue;
0317         generic_handle_domain_irq(p->irqdomain, i);
0318     }
0319 
0320     chained_irq_exit(irqchip, desc);
0321 }
0322 
0323 static struct irq_chip faraday_pci_irq_chip = {
0324     .name = "PCI",
0325     .irq_ack = faraday_pci_ack_irq,
0326     .irq_mask = faraday_pci_mask_irq,
0327     .irq_unmask = faraday_pci_unmask_irq,
0328 };
0329 
0330 static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
0331                    irq_hw_number_t hwirq)
0332 {
0333     irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
0334     irq_set_chip_data(irq, domain->host_data);
0335 
0336     return 0;
0337 }
0338 
0339 static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
0340     .map = faraday_pci_irq_map,
0341 };
0342 
0343 static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
0344 {
0345     struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
0346     int irq;
0347     int i;
0348 
0349     if (!intc) {
0350         dev_err(p->dev, "missing child interrupt-controller node\n");
0351         return -EINVAL;
0352     }
0353 
0354     /* All PCI IRQs cascade off this one */
0355     irq = of_irq_get(intc, 0);
0356     if (irq <= 0) {
0357         dev_err(p->dev, "failed to get parent IRQ\n");
0358         of_node_put(intc);
0359         return irq ?: -EINVAL;
0360     }
0361 
0362     p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
0363                          &faraday_pci_irqdomain_ops, p);
0364     of_node_put(intc);
0365     if (!p->irqdomain) {
0366         dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
0367         return -EINVAL;
0368     }
0369 
0370     irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
0371 
0372     for (i = 0; i < 4; i++)
0373         irq_create_mapping(p->irqdomain, i);
0374 
0375     return 0;
0376 }
0377 
0378 static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p)
0379 {
0380     struct device *dev = p->dev;
0381     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
0382     struct resource_entry *entry;
0383     u32 confreg[3] = {
0384         FARADAY_PCI_MEM1_BASE_SIZE,
0385         FARADAY_PCI_MEM2_BASE_SIZE,
0386         FARADAY_PCI_MEM3_BASE_SIZE,
0387     };
0388     int i = 0;
0389     u32 val;
0390 
0391     resource_list_for_each_entry(entry, &bridge->dma_ranges) {
0392         u64 pci_addr = entry->res->start - entry->offset;
0393         u64 end = entry->res->end - entry->offset;
0394         int ret;
0395 
0396         ret = faraday_res_to_memcfg(pci_addr,
0397                         resource_size(entry->res), &val);
0398         if (ret) {
0399             dev_err(dev,
0400                 "DMA range %d: illegal MEM resource size\n", i);
0401             return -EINVAL;
0402         }
0403 
0404         dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
0405              i + 1, pci_addr, end, val);
0406         if (i <= 2) {
0407             faraday_raw_pci_write_config(p, 0, 0, confreg[i],
0408                              4, val);
0409         } else {
0410             dev_err(dev, "ignore extraneous dma-range %d\n", i);
0411             break;
0412         }
0413 
0414         i++;
0415     }
0416 
0417     return 0;
0418 }
0419 
0420 static int faraday_pci_probe(struct platform_device *pdev)
0421 {
0422     struct device *dev = &pdev->dev;
0423     const struct faraday_pci_variant *variant =
0424         of_device_get_match_data(dev);
0425     struct resource_entry *win;
0426     struct faraday_pci *p;
0427     struct resource *io;
0428     struct pci_host_bridge *host;
0429     struct clk *clk;
0430     unsigned char max_bus_speed = PCI_SPEED_33MHz;
0431     unsigned char cur_bus_speed = PCI_SPEED_33MHz;
0432     int ret;
0433     u32 val;
0434 
0435     host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
0436     if (!host)
0437         return -ENOMEM;
0438 
0439     host->ops = &faraday_pci_ops;
0440     p = pci_host_bridge_priv(host);
0441     host->sysdata = p;
0442     p->dev = dev;
0443 
0444     /* Retrieve and enable optional clocks */
0445     clk = devm_clk_get(dev, "PCLK");
0446     if (IS_ERR(clk))
0447         return PTR_ERR(clk);
0448     ret = clk_prepare_enable(clk);
0449     if (ret) {
0450         dev_err(dev, "could not prepare PCLK\n");
0451         return ret;
0452     }
0453     p->bus_clk = devm_clk_get(dev, "PCICLK");
0454     if (IS_ERR(p->bus_clk))
0455         return PTR_ERR(p->bus_clk);
0456     ret = clk_prepare_enable(p->bus_clk);
0457     if (ret) {
0458         dev_err(dev, "could not prepare PCICLK\n");
0459         return ret;
0460     }
0461 
0462     p->base = devm_platform_ioremap_resource(pdev, 0);
0463     if (IS_ERR(p->base))
0464         return PTR_ERR(p->base);
0465 
0466     win = resource_list_first_type(&host->windows, IORESOURCE_IO);
0467     if (win) {
0468         io = win->res;
0469         if (!faraday_res_to_memcfg(io->start - win->offset,
0470                        resource_size(io), &val)) {
0471             /* setup I/O space size */
0472             writel(val, p->base + FTPCI_IOSIZE);
0473         } else {
0474             dev_err(dev, "illegal IO mem size\n");
0475             return -EINVAL;
0476         }
0477     }
0478 
0479     /* Setup hostbridge */
0480     val = readl(p->base + FTPCI_CTRL);
0481     val |= PCI_COMMAND_IO;
0482     val |= PCI_COMMAND_MEMORY;
0483     val |= PCI_COMMAND_MASTER;
0484     writel(val, p->base + FTPCI_CTRL);
0485     /* Mask and clear all interrupts */
0486     faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
0487     if (variant->cascaded_irq) {
0488         ret = faraday_pci_setup_cascaded_irq(p);
0489         if (ret) {
0490             dev_err(dev, "failed to setup cascaded IRQ\n");
0491             return ret;
0492         }
0493     }
0494 
0495     /* Check bus clock if we can gear up to 66 MHz */
0496     if (!IS_ERR(p->bus_clk)) {
0497         unsigned long rate;
0498         u32 val;
0499 
0500         faraday_raw_pci_read_config(p, 0, 0,
0501                         FARADAY_PCI_STATUS_CMD, 4, &val);
0502         rate = clk_get_rate(p->bus_clk);
0503 
0504         if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
0505             dev_info(dev, "33MHz bus is 66MHz capable\n");
0506             max_bus_speed = PCI_SPEED_66MHz;
0507             ret = clk_set_rate(p->bus_clk, 66000000);
0508             if (ret)
0509                 dev_err(dev, "failed to set bus clock\n");
0510         } else {
0511             dev_info(dev, "33MHz only bus\n");
0512             max_bus_speed = PCI_SPEED_33MHz;
0513         }
0514 
0515         /* Bumping the clock may fail so read back the rate */
0516         rate = clk_get_rate(p->bus_clk);
0517         if (rate == 33000000)
0518             cur_bus_speed = PCI_SPEED_33MHz;
0519         if (rate == 66000000)
0520             cur_bus_speed = PCI_SPEED_66MHz;
0521     }
0522 
0523     ret = faraday_pci_parse_map_dma_ranges(p);
0524     if (ret)
0525         return ret;
0526 
0527     ret = pci_scan_root_bus_bridge(host);
0528     if (ret) {
0529         dev_err(dev, "failed to scan host: %d\n", ret);
0530         return ret;
0531     }
0532     p->bus = host->bus;
0533     p->bus->max_bus_speed = max_bus_speed;
0534     p->bus->cur_bus_speed = cur_bus_speed;
0535 
0536     pci_bus_assign_resources(p->bus);
0537     pci_bus_add_devices(p->bus);
0538 
0539     return 0;
0540 }
0541 
0542 /*
0543  * We encode bridge variants here, we have at least two so it doesn't
0544  * hurt to have infrastructure to encompass future variants as well.
0545  */
0546 static const struct faraday_pci_variant faraday_regular = {
0547     .cascaded_irq = true,
0548 };
0549 
0550 static const struct faraday_pci_variant faraday_dual = {
0551     .cascaded_irq = false,
0552 };
0553 
0554 static const struct of_device_id faraday_pci_of_match[] = {
0555     {
0556         .compatible = "faraday,ftpci100",
0557         .data = &faraday_regular,
0558     },
0559     {
0560         .compatible = "faraday,ftpci100-dual",
0561         .data = &faraday_dual,
0562     },
0563     {},
0564 };
0565 
0566 static struct platform_driver faraday_pci_driver = {
0567     .driver = {
0568         .name = "ftpci100",
0569         .of_match_table = of_match_ptr(faraday_pci_of_match),
0570         .suppress_bind_attrs = true,
0571     },
0572     .probe  = faraday_pci_probe,
0573 };
0574 builtin_platform_driver(faraday_pci_driver);
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