controller/mobiveil/pcie-mobiveil.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * PCIe host controller driver for Mobiveil PCIe Host controller
0004  *
0005  * Copyright (c) 2018 Mobiveil Inc.
0006  * Copyright 2019 NXP
0007  *
0008  * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
0009  *     Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
0010  */
0011
0012 #ifndef _PCIE_MOBIVEIL_H
0013 #define _PCIE_MOBIVEIL_H
0014
0015 #include <linux/pci.h>
0016 #include <linux/irq.h>
0017 #include <linux/msi.h>
0018 #include "../../pci.h"
0019
0020 /* register offsets and bit positions */
0021
0022 /*
0023  * translation tables are grouped into windows, each window registers are
0024  * grouped into blocks of 4 or 16 registers each
0025  */
0026 #define PAB_REG_BLOCK_SIZE      16
0027 #define PAB_EXT_REG_BLOCK_SIZE      4
0028
0029 #define PAB_REG_ADDR(offset, win)   \
0030     (offset + (win * PAB_REG_BLOCK_SIZE))
0031 #define PAB_EXT_REG_ADDR(offset, win)   \
0032     (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
0033
0034 #define LTSSM_STATUS            0x0404
0035 #define  LTSSM_STATUS_L0_MASK       0x3f
0036 #define  LTSSM_STATUS_L0        0x2d
0037
0038 #define PAB_CTRL            0x0808
0039 #define  AMBA_PIO_ENABLE_SHIFT      0
0040 #define  PEX_PIO_ENABLE_SHIFT       1
0041 #define  PAGE_SEL_SHIFT         13
0042 #define  PAGE_SEL_MASK          0x3f
0043 #define  PAGE_LO_MASK           0x3ff
0044 #define  PAGE_SEL_OFFSET_SHIFT      10
0045
0046 #define PAB_ACTIVITY_STAT       0x81c
0047
0048 #define PAB_AXI_PIO_CTRL        0x0840
0049 #define  APIO_EN_MASK           0xf
0050
0051 #define PAB_PEX_PIO_CTRL        0x08c0
0052 #define  PIO_ENABLE_SHIFT       0
0053
0054 #define PAB_INTP_AMBA_MISC_ENB      0x0b0c
0055 #define PAB_INTP_AMBA_MISC_STAT     0x0b1c
0056 #define  PAB_INTP_RESET         BIT(1)
0057 #define  PAB_INTP_MSI           BIT(3)
0058 #define  PAB_INTP_INTA          BIT(5)
0059 #define  PAB_INTP_INTB          BIT(6)
0060 #define  PAB_INTP_INTC          BIT(7)
0061 #define  PAB_INTP_INTD          BIT(8)
0062 #define  PAB_INTP_PCIE_UE       BIT(9)
0063 #define  PAB_INTP_IE_PMREDI     BIT(29)
0064 #define  PAB_INTP_IE_EC         BIT(30)
0065 #define  PAB_INTP_MSI_MASK      PAB_INTP_MSI
0066 #define  PAB_INTP_INTX_MASK     (PAB_INTP_INTA | PAB_INTP_INTB |\
0067                     PAB_INTP_INTC | PAB_INTP_INTD)
0068
0069 #define PAB_AXI_AMAP_CTRL(win)      PAB_REG_ADDR(0x0ba0, win)
0070 #define  WIN_ENABLE_SHIFT       0
0071 #define  WIN_TYPE_SHIFT         1
0072 #define  WIN_TYPE_MASK          0x3
0073 #define  WIN_SIZE_MASK          0xfffffc00
0074
0075 #define PAB_EXT_AXI_AMAP_SIZE(win)  PAB_EXT_REG_ADDR(0xbaf0, win)
0076
0077 #define PAB_EXT_AXI_AMAP_AXI_WIN(win)   PAB_EXT_REG_ADDR(0x80a0, win)
0078 #define PAB_AXI_AMAP_AXI_WIN(win)   PAB_REG_ADDR(0x0ba4, win)
0079 #define  AXI_WINDOW_ALIGN_MASK      3
0080
0081 #define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
0082 #define  PAB_BUS_SHIFT          24
0083 #define  PAB_DEVICE_SHIFT       19
0084 #define  PAB_FUNCTION_SHIFT     16
0085
0086 #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
0087 #define PAB_INTP_AXI_PIO_CLASS      0x474
0088
0089 #define PAB_PEX_AMAP_CTRL(win)      PAB_REG_ADDR(0x4ba0, win)
0090 #define  AMAP_CTRL_EN_SHIFT     0
0091 #define  AMAP_CTRL_TYPE_SHIFT       1
0092 #define  AMAP_CTRL_TYPE_MASK        3
0093
0094 #define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
0095 #define PAB_EXT_PEX_AMAP_AXI_WIN(win)   PAB_EXT_REG_ADDR(0xb4a0, win)
0096 #define PAB_PEX_AMAP_AXI_WIN(win)   PAB_REG_ADDR(0x4ba4, win)
0097 #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
0098 #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
0099
0100 /* starting offset of INTX bits in status register */
0101 #define PAB_INTX_START          5
0102
0103 /* supported number of MSI interrupts */
0104 #define PCI_NUM_MSI         16
0105
0106 /* MSI registers */
0107 #define MSI_BASE_LO_OFFSET      0x04
0108 #define MSI_BASE_HI_OFFSET      0x08
0109 #define MSI_SIZE_OFFSET         0x0c
0110 #define MSI_ENABLE_OFFSET       0x14
0111 #define MSI_STATUS_OFFSET       0x18
0112 #define MSI_DATA_OFFSET         0x20
0113 #define MSI_ADDR_L_OFFSET       0x24
0114 #define MSI_ADDR_H_OFFSET       0x28
0115
0116 /* outbound and inbound window definitions */
0117 #define WIN_NUM_0           0
0118 #define WIN_NUM_1           1
0119 #define CFG_WINDOW_TYPE         0
0120 #define IO_WINDOW_TYPE          1
0121 #define MEM_WINDOW_TYPE         2
0122 #define IB_WIN_SIZE         ((u64)256 * 1024 * 1024 * 1024)
0123 #define MAX_PIO_WINDOWS         8
0124
0125 /* Parameters for the waiting for link up routine */
0126 #define LINK_WAIT_MAX_RETRIES       10
0127 #define LINK_WAIT_MIN           90000
0128 #define LINK_WAIT_MAX           100000
0129
0130 #define PAGED_ADDR_BNDRY        0xc00
0131 #define OFFSET_TO_PAGE_ADDR(off)    \
0132     ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
0133 #define OFFSET_TO_PAGE_IDX(off)     \
0134     ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
0135
0136 struct mobiveil_msi {           /* MSI information */
0137     struct mutex lock;      /* protect bitmap variable */
0138     struct irq_domain *msi_domain;
0139     struct irq_domain *dev_domain;
0140     phys_addr_t msi_pages_phys;
0141     int num_of_vectors;
0142     DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
0143 };
0144
0145 struct mobiveil_pcie;
0146
0147 struct mobiveil_rp_ops {
0148     int (*interrupt_init)(struct mobiveil_pcie *pcie);
0149 };
0150
0151 struct mobiveil_root_port {
0152     void __iomem *config_axi_slave_base;    /* endpoint config base */
0153     struct resource *ob_io_res;
0154     struct mobiveil_rp_ops *ops;
0155     int irq;
0156     raw_spinlock_t intx_mask_lock;
0157     struct irq_domain *intx_domain;
0158     struct mobiveil_msi msi;
0159     struct pci_host_bridge *bridge;
0160 };
0161
0162 struct mobiveil_pab_ops {
0163     int (*link_up)(struct mobiveil_pcie *pcie);
0164 };
0165
0166 struct mobiveil_pcie {
0167     struct platform_device *pdev;
0168     void __iomem *csr_axi_slave_base;   /* root port config base */
0169     void __iomem *apb_csr_base; /* MSI register base */
0170     phys_addr_t pcie_reg_base;  /* Physical PCIe Controller Base */
0171     int apio_wins;
0172     int ppio_wins;
0173     int ob_wins_configured;     /* configured outbound windows */
0174     int ib_wins_configured;     /* configured inbound windows */
0175     const struct mobiveil_pab_ops *ops;
0176     struct mobiveil_root_port rp;
0177 };
0178
0179 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
0180 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
0181 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
0182 int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
0183 void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
0184             u64 pci_addr, u32 type, u64 size);
0185 void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
0186             u64 pci_addr, u32 type, u64 size);
0187 u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
0188 void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
0189             size_t size);
0190
0191 static inline u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
0192 {
0193     return mobiveil_csr_read(pcie, off, 0x4);
0194 }
0195
0196 static inline u16 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32 off)
0197 {
0198     return mobiveil_csr_read(pcie, off, 0x2);
0199 }
0200
0201 static inline u8 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32 off)
0202 {
0203     return mobiveil_csr_read(pcie, off, 0x1);
0204 }
0205
0206
0207 static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
0208                        u32 off)
0209 {
0210     mobiveil_csr_write(pcie, val, off, 0x4);
0211 }
0212
0213 static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u16 val,
0214                        u32 off)
0215 {
0216     mobiveil_csr_write(pcie, val, off, 0x2);
0217 }
0218
0219 static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u8 val,
0220                        u32 off)
0221 {
0222     mobiveil_csr_write(pcie, val, off, 0x1);
0223 }
0224
0225 #endif /* _PCIE_MOBIVEIL_H */