controller/dwc/pcie-uniphier.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe host controller driver for UniPhier SoCs
0004  * Copyright 2018 Socionext Inc.
0005  * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
0006  */
0007
0008 #include <linux/bitops.h>
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/irqchip/chained_irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/pci.h>
0019 #include <linux/phy/phy.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/reset.h>
0022
0023 #include "pcie-designware.h"
0024
0025 #define PCL_PINCTRL0            0x002c
0026 #define PCL_PERST_PLDN_REGEN        BIT(12)
0027 #define PCL_PERST_NOE_REGEN     BIT(11)
0028 #define PCL_PERST_OUT_REGEN     BIT(8)
0029 #define PCL_PERST_PLDN_REGVAL       BIT(4)
0030 #define PCL_PERST_NOE_REGVAL        BIT(3)
0031 #define PCL_PERST_OUT_REGVAL        BIT(0)
0032
0033 #define PCL_PIPEMON         0x0044
0034 #define PCL_PCLK_ALIVE          BIT(15)
0035
0036 #define PCL_MODE            0x8000
0037 #define PCL_MODE_REGEN          BIT(8)
0038 #define PCL_MODE_REGVAL         BIT(0)
0039
0040 #define PCL_APP_READY_CTRL      0x8008
0041 #define PCL_APP_LTSSM_ENABLE        BIT(0)
0042
0043 #define PCL_APP_PM0         0x8078
0044 #define PCL_SYS_AUX_PWR_DET     BIT(8)
0045
0046 #define PCL_RCV_INT         0x8108
0047 #define PCL_RCV_INT_ALL_ENABLE      GENMASK(20, 17)
0048 #define PCL_CFG_BW_MGT_STATUS       BIT(4)
0049 #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
0050 #define PCL_CFG_AER_RC_ERR_MSI_STATUS   BIT(2)
0051 #define PCL_CFG_PME_MSI_STATUS      BIT(1)
0052
0053 #define PCL_RCV_INTX            0x810c
0054 #define PCL_RCV_INTX_ALL_ENABLE     GENMASK(19, 16)
0055 #define PCL_RCV_INTX_ALL_MASK       GENMASK(11, 8)
0056 #define PCL_RCV_INTX_MASK_SHIFT     8
0057 #define PCL_RCV_INTX_ALL_STATUS     GENMASK(3, 0)
0058 #define PCL_RCV_INTX_STATUS_SHIFT   0
0059
0060 #define PCL_STATUS_LINK         0x8140
0061 #define PCL_RDLH_LINK_UP        BIT(1)
0062 #define PCL_XMLH_LINK_UP        BIT(0)
0063
0064 struct uniphier_pcie {
0065     struct dw_pcie pci;
0066     void __iomem *base;
0067     struct clk *clk;
0068     struct reset_control *rst;
0069     struct phy *phy;
0070     struct irq_domain *legacy_irq_domain;
0071 };
0072
0073 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
0074
0075 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie,
0076                        bool enable)
0077 {
0078     u32 val;
0079
0080     val = readl(pcie->base + PCL_APP_READY_CTRL);
0081     if (enable)
0082         val |= PCL_APP_LTSSM_ENABLE;
0083     else
0084         val &= ~PCL_APP_LTSSM_ENABLE;
0085     writel(val, pcie->base + PCL_APP_READY_CTRL);
0086 }
0087
0088 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie)
0089 {
0090     u32 val;
0091
0092     /* set RC MODE */
0093     val = readl(pcie->base + PCL_MODE);
0094     val |= PCL_MODE_REGEN;
0095     val &= ~PCL_MODE_REGVAL;
0096     writel(val, pcie->base + PCL_MODE);
0097
0098     /* use auxiliary power detection */
0099     val = readl(pcie->base + PCL_APP_PM0);
0100     val |= PCL_SYS_AUX_PWR_DET;
0101     writel(val, pcie->base + PCL_APP_PM0);
0102
0103     /* assert PERST# */
0104     val = readl(pcie->base + PCL_PINCTRL0);
0105     val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
0106          | PCL_PERST_PLDN_REGVAL);
0107     val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
0108         | PCL_PERST_PLDN_REGEN;
0109     writel(val, pcie->base + PCL_PINCTRL0);
0110
0111     uniphier_pcie_ltssm_enable(pcie, false);
0112
0113     usleep_range(100000, 200000);
0114
0115     /* deassert PERST# */
0116     val = readl(pcie->base + PCL_PINCTRL0);
0117     val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
0118     writel(val, pcie->base + PCL_PINCTRL0);
0119 }
0120
0121 static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie)
0122 {
0123     u32 status;
0124     int ret;
0125
0126     /* wait PIPE clock */
0127     ret = readl_poll_timeout(pcie->base + PCL_PIPEMON, status,
0128                  status & PCL_PCLK_ALIVE, 100000, 1000000);
0129     if (ret) {
0130         dev_err(pcie->pci.dev,
0131             "Failed to initialize controller in RC mode\n");
0132         return ret;
0133     }
0134
0135     return 0;
0136 }
0137
0138 static int uniphier_pcie_link_up(struct dw_pcie *pci)
0139 {
0140     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0141     u32 val, mask;
0142
0143     val = readl(pcie->base + PCL_STATUS_LINK);
0144     mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
0145
0146     return (val & mask) == mask;
0147 }
0148
0149 static int uniphier_pcie_start_link(struct dw_pcie *pci)
0150 {
0151     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0152
0153     uniphier_pcie_ltssm_enable(pcie, true);
0154
0155     return 0;
0156 }
0157
0158 static void uniphier_pcie_stop_link(struct dw_pcie *pci)
0159 {
0160     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0161
0162     uniphier_pcie_ltssm_enable(pcie, false);
0163 }
0164
0165 static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie)
0166 {
0167     writel(PCL_RCV_INT_ALL_ENABLE, pcie->base + PCL_RCV_INT);
0168     writel(PCL_RCV_INTX_ALL_ENABLE, pcie->base + PCL_RCV_INTX);
0169 }
0170
0171
0172 static void uniphier_pcie_irq_mask(struct irq_data *d)
0173 {
0174     struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
0175     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0176     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0177     unsigned long flags;
0178     u32 val;
0179
0180     raw_spin_lock_irqsave(&pp->lock, flags);
0181
0182     val = readl(pcie->base + PCL_RCV_INTX);
0183     val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
0184     writel(val, pcie->base + PCL_RCV_INTX);
0185
0186     raw_spin_unlock_irqrestore(&pp->lock, flags);
0187 }
0188
0189 static void uniphier_pcie_irq_unmask(struct irq_data *d)
0190 {
0191     struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
0192     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0193     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0194     unsigned long flags;
0195     u32 val;
0196
0197     raw_spin_lock_irqsave(&pp->lock, flags);
0198
0199     val = readl(pcie->base + PCL_RCV_INTX);
0200     val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
0201     writel(val, pcie->base + PCL_RCV_INTX);
0202
0203     raw_spin_unlock_irqrestore(&pp->lock, flags);
0204 }
0205
0206 static struct irq_chip uniphier_pcie_irq_chip = {
0207     .name = "PCI",
0208     .irq_mask = uniphier_pcie_irq_mask,
0209     .irq_unmask = uniphier_pcie_irq_unmask,
0210 };
0211
0212 static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
0213                   irq_hw_number_t hwirq)
0214 {
0215     irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
0216                  handle_level_irq);
0217     irq_set_chip_data(irq, domain->host_data);
0218
0219     return 0;
0220 }
0221
0222 static const struct irq_domain_ops uniphier_intx_domain_ops = {
0223     .map = uniphier_pcie_intx_map,
0224 };
0225
0226 static void uniphier_pcie_irq_handler(struct irq_desc *desc)
0227 {
0228     struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
0229     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0230     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0231     struct irq_chip *chip = irq_desc_get_chip(desc);
0232     unsigned long reg;
0233     u32 val, bit;
0234
0235     /* INT for debug */
0236     val = readl(pcie->base + PCL_RCV_INT);
0237
0238     if (val & PCL_CFG_BW_MGT_STATUS)
0239         dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
0240     if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
0241         dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
0242     if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
0243         dev_dbg(pci->dev, "Root Error\n");
0244     if (val & PCL_CFG_PME_MSI_STATUS)
0245         dev_dbg(pci->dev, "PME Interrupt\n");
0246
0247     writel(val, pcie->base + PCL_RCV_INT);
0248
0249     /* INTx */
0250     chained_irq_enter(chip, desc);
0251
0252     val = readl(pcie->base + PCL_RCV_INTX);
0253     reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
0254
0255     for_each_set_bit(bit, &reg, PCI_NUM_INTX)
0256         generic_handle_domain_irq(pcie->legacy_irq_domain, bit);
0257
0258     chained_irq_exit(chip, desc);
0259 }
0260
0261 static int uniphier_pcie_config_legacy_irq(struct dw_pcie_rp *pp)
0262 {
0263     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0264     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0265     struct device_node *np = pci->dev->of_node;
0266     struct device_node *np_intc;
0267     int ret = 0;
0268
0269     np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
0270     if (!np_intc) {
0271         dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
0272         return -EINVAL;
0273     }
0274
0275     pp->irq = irq_of_parse_and_map(np_intc, 0);
0276     if (!pp->irq) {
0277         dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
0278         ret = -EINVAL;
0279         goto out_put_node;
0280     }
0281
0282     pcie->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
0283                         &uniphier_intx_domain_ops, pp);
0284     if (!pcie->legacy_irq_domain) {
0285         dev_err(pci->dev, "Failed to get INTx domain\n");
0286         ret = -ENODEV;
0287         goto out_put_node;
0288     }
0289
0290     irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
0291                      pp);
0292
0293 out_put_node:
0294     of_node_put(np_intc);
0295     return ret;
0296 }
0297
0298 static int uniphier_pcie_host_init(struct dw_pcie_rp *pp)
0299 {
0300     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0301     struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
0302     int ret;
0303
0304     ret = uniphier_pcie_config_legacy_irq(pp);
0305     if (ret)
0306         return ret;
0307
0308     uniphier_pcie_irq_enable(pcie);
0309
0310     return 0;
0311 }
0312
0313 static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
0314     .host_init = uniphier_pcie_host_init,
0315 };
0316
0317 static int uniphier_pcie_host_enable(struct uniphier_pcie *pcie)
0318 {
0319     int ret;
0320
0321     ret = clk_prepare_enable(pcie->clk);
0322     if (ret)
0323         return ret;
0324
0325     ret = reset_control_deassert(pcie->rst);
0326     if (ret)
0327         goto out_clk_disable;
0328
0329     uniphier_pcie_init_rc(pcie);
0330
0331     ret = phy_init(pcie->phy);
0332     if (ret)
0333         goto out_rst_assert;
0334
0335     ret = uniphier_pcie_wait_rc(pcie);
0336     if (ret)
0337         goto out_phy_exit;
0338
0339     return 0;
0340
0341 out_phy_exit:
0342     phy_exit(pcie->phy);
0343 out_rst_assert:
0344     reset_control_assert(pcie->rst);
0345 out_clk_disable:
0346     clk_disable_unprepare(pcie->clk);
0347
0348     return ret;
0349 }
0350
0351 static const struct dw_pcie_ops dw_pcie_ops = {
0352     .start_link = uniphier_pcie_start_link,
0353     .stop_link = uniphier_pcie_stop_link,
0354     .link_up = uniphier_pcie_link_up,
0355 };
0356
0357 static int uniphier_pcie_probe(struct platform_device *pdev)
0358 {
0359     struct device *dev = &pdev->dev;
0360     struct uniphier_pcie *pcie;
0361     int ret;
0362
0363     pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
0364     if (!pcie)
0365         return -ENOMEM;
0366
0367     pcie->pci.dev = dev;
0368     pcie->pci.ops = &dw_pcie_ops;
0369
0370     pcie->base = devm_platform_ioremap_resource_byname(pdev, "link");
0371     if (IS_ERR(pcie->base))
0372         return PTR_ERR(pcie->base);
0373
0374     pcie->clk = devm_clk_get(dev, NULL);
0375     if (IS_ERR(pcie->clk))
0376         return PTR_ERR(pcie->clk);
0377
0378     pcie->rst = devm_reset_control_get_shared(dev, NULL);
0379     if (IS_ERR(pcie->rst))
0380         return PTR_ERR(pcie->rst);
0381
0382     pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
0383     if (IS_ERR(pcie->phy))
0384         return PTR_ERR(pcie->phy);
0385
0386     platform_set_drvdata(pdev, pcie);
0387
0388     ret = uniphier_pcie_host_enable(pcie);
0389     if (ret)
0390         return ret;
0391
0392     pcie->pci.pp.ops = &uniphier_pcie_host_ops;
0393
0394     return dw_pcie_host_init(&pcie->pci.pp);
0395 }
0396
0397 static const struct of_device_id uniphier_pcie_match[] = {
0398     { .compatible = "socionext,uniphier-pcie", },
0399     { /* sentinel */ },
0400 };
0401
0402 static struct platform_driver uniphier_pcie_driver = {
0403     .probe  = uniphier_pcie_probe,
0404     .driver = {
0405         .name = "uniphier-pcie",
0406         .of_match_table = uniphier_pcie_match,
0407     },
0408 };
0409 builtin_platform_driver(uniphier_pcie_driver);