Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe host controller driver for Kirin Phone SoCs
0004  *
0005  * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
0006  *      https://www.huawei.com
0007  *
0008  * Author: Xiaowei Song <songxiaowei@huawei.com>
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/compiler.h>
0013 #include <linux/delay.h>
0014 #include <linux/err.h>
0015 #include <linux/gpio.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/mfd/syscon.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/of_pci.h>
0022 #include <linux/phy/phy.h>
0023 #include <linux/pci.h>
0024 #include <linux/pci_regs.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/regmap.h>
0027 #include <linux/resource.h>
0028 #include <linux/types.h>
0029 #include "pcie-designware.h"
0030 
0031 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
0032 
0033 /* PCIe ELBI registers */
0034 #define SOC_PCIECTRL_CTRL0_ADDR     0x000
0035 #define SOC_PCIECTRL_CTRL1_ADDR     0x004
0036 #define PCIE_ELBI_SLV_DBI_ENABLE    (0x1 << 21)
0037 
0038 /* info located in APB */
0039 #define PCIE_APP_LTSSM_ENABLE   0x01c
0040 #define PCIE_APB_PHY_STATUS0    0x400
0041 #define PCIE_LINKUP_ENABLE  (0x8020)
0042 #define PCIE_LTSSM_ENABLE_BIT   (0x1 << 11)
0043 
0044 /* info located in sysctrl */
0045 #define SCTRL_PCIE_CMOS_OFFSET  0x60
0046 #define SCTRL_PCIE_CMOS_BIT 0x10
0047 #define SCTRL_PCIE_ISO_OFFSET   0x44
0048 #define SCTRL_PCIE_ISO_BIT  0x30
0049 #define SCTRL_PCIE_HPCLK_OFFSET 0x190
0050 #define SCTRL_PCIE_HPCLK_BIT    0x184000
0051 #define SCTRL_PCIE_OE_OFFSET    0x14a
0052 #define PCIE_DEBOUNCE_PARAM 0xF0F400
0053 #define PCIE_OE_BYPASS      (0x3 << 28)
0054 
0055 /*
0056  * Max number of connected PCI slots at an external PCI bridge
0057  *
0058  * This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected
0059  * lanes (lane 0 upstream, and the other three lanes, one connected to an
0060  * in-board Ethernet adapter and the other two connected to M.2 and mini
0061  * PCI slots.
0062  *
0063  * Each slot has a different clock source and uses a separate PERST# pin.
0064  */
0065 #define MAX_PCI_SLOTS       3
0066 
0067 enum pcie_kirin_phy_type {
0068     PCIE_KIRIN_INTERNAL_PHY,
0069     PCIE_KIRIN_EXTERNAL_PHY
0070 };
0071 
0072 struct kirin_pcie {
0073     enum pcie_kirin_phy_type    type;
0074 
0075     struct dw_pcie  *pci;
0076     struct regmap   *apb;
0077     struct phy  *phy;
0078     void        *phy_priv;  /* only for PCIE_KIRIN_INTERNAL_PHY */
0079 
0080     /* DWC PERST# */
0081     int     gpio_id_dwc_perst;
0082 
0083     /* Per-slot PERST# */
0084     int     num_slots;
0085     int     gpio_id_reset[MAX_PCI_SLOTS];
0086     const char  *reset_names[MAX_PCI_SLOTS];
0087 
0088     /* Per-slot clkreq */
0089     int     n_gpio_clkreq;
0090     int     gpio_id_clkreq[MAX_PCI_SLOTS];
0091     const char  *clkreq_names[MAX_PCI_SLOTS];
0092 };
0093 
0094 /*
0095  * Kirin 960 PHY. Can't be split into a PHY driver without changing the
0096  * DT schema.
0097  */
0098 
0099 #define REF_CLK_FREQ            100000000
0100 
0101 /* PHY info located in APB */
0102 #define PCIE_APB_PHY_CTRL0  0x0
0103 #define PCIE_APB_PHY_CTRL1  0x4
0104 #define PCIE_APB_PHY_STATUS0   0x400
0105 #define PIPE_CLK_STABLE     BIT(19)
0106 #define PHY_REF_PAD_BIT     BIT(8)
0107 #define PHY_PWR_DOWN_BIT    BIT(22)
0108 #define PHY_RST_ACK_BIT     BIT(16)
0109 
0110 /* peri_crg ctrl */
0111 #define CRGCTRL_PCIE_ASSERT_OFFSET  0x88
0112 #define CRGCTRL_PCIE_ASSERT_BIT     0x8c000000
0113 
0114 /* Time for delay */
0115 #define REF_2_PERST_MIN     21000
0116 #define REF_2_PERST_MAX     25000
0117 #define PERST_2_ACCESS_MIN  10000
0118 #define PERST_2_ACCESS_MAX  12000
0119 #define PIPE_CLK_WAIT_MIN   550
0120 #define PIPE_CLK_WAIT_MAX   600
0121 #define TIME_CMOS_MIN       100
0122 #define TIME_CMOS_MAX       105
0123 #define TIME_PHY_PD_MIN     10
0124 #define TIME_PHY_PD_MAX     11
0125 
0126 struct hi3660_pcie_phy {
0127     struct device   *dev;
0128     void __iomem    *base;
0129     struct regmap   *crgctrl;
0130     struct regmap   *sysctrl;
0131     struct clk  *apb_sys_clk;
0132     struct clk  *apb_phy_clk;
0133     struct clk  *phy_ref_clk;
0134     struct clk  *aclk;
0135     struct clk  *aux_clk;
0136 };
0137 
0138 /* Registers in PCIePHY */
0139 static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy,
0140                     u32 val, u32 reg)
0141 {
0142     writel(val, hi3660_pcie_phy->base + reg);
0143 }
0144 
0145 static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy,
0146                       u32 reg)
0147 {
0148     return readl(hi3660_pcie_phy->base + reg);
0149 }
0150 
0151 static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy)
0152 {
0153     struct device *dev = phy->dev;
0154 
0155     phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
0156     if (IS_ERR(phy->phy_ref_clk))
0157         return PTR_ERR(phy->phy_ref_clk);
0158 
0159     phy->aux_clk = devm_clk_get(dev, "pcie_aux");
0160     if (IS_ERR(phy->aux_clk))
0161         return PTR_ERR(phy->aux_clk);
0162 
0163     phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
0164     if (IS_ERR(phy->apb_phy_clk))
0165         return PTR_ERR(phy->apb_phy_clk);
0166 
0167     phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
0168     if (IS_ERR(phy->apb_sys_clk))
0169         return PTR_ERR(phy->apb_sys_clk);
0170 
0171     phy->aclk = devm_clk_get(dev, "pcie_aclk");
0172     if (IS_ERR(phy->aclk))
0173         return PTR_ERR(phy->aclk);
0174 
0175     return 0;
0176 }
0177 
0178 static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy)
0179 {
0180     struct device *dev = phy->dev;
0181     struct platform_device *pdev;
0182 
0183     /* registers */
0184     pdev = container_of(dev, struct platform_device, dev);
0185 
0186     phy->base = devm_platform_ioremap_resource_byname(pdev, "phy");
0187     if (IS_ERR(phy->base))
0188         return PTR_ERR(phy->base);
0189 
0190     phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
0191     if (IS_ERR(phy->crgctrl))
0192         return PTR_ERR(phy->crgctrl);
0193 
0194     phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
0195     if (IS_ERR(phy->sysctrl))
0196         return PTR_ERR(phy->sysctrl);
0197 
0198     return 0;
0199 }
0200 
0201 static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy)
0202 {
0203     struct device *dev = phy->dev;
0204     u32 reg_val;
0205 
0206     reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
0207     reg_val &= ~PHY_REF_PAD_BIT;
0208     kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
0209 
0210     reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0);
0211     reg_val &= ~PHY_PWR_DOWN_BIT;
0212     kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0);
0213     usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
0214 
0215     reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1);
0216     reg_val &= ~PHY_RST_ACK_BIT;
0217     kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1);
0218 
0219     usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
0220     reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0);
0221     if (reg_val & PIPE_CLK_STABLE) {
0222         dev_err(dev, "PIPE clk is not stable\n");
0223         return -EINVAL;
0224     }
0225 
0226     return 0;
0227 }
0228 
0229 static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy)
0230 {
0231     u32 val;
0232 
0233     regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
0234     val |= PCIE_DEBOUNCE_PARAM;
0235     val &= ~PCIE_OE_BYPASS;
0236     regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
0237 }
0238 
0239 static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable)
0240 {
0241     int ret = 0;
0242 
0243     if (!enable)
0244         goto close_clk;
0245 
0246     ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
0247     if (ret)
0248         return ret;
0249 
0250     ret = clk_prepare_enable(phy->phy_ref_clk);
0251     if (ret)
0252         return ret;
0253 
0254     ret = clk_prepare_enable(phy->apb_sys_clk);
0255     if (ret)
0256         goto apb_sys_fail;
0257 
0258     ret = clk_prepare_enable(phy->apb_phy_clk);
0259     if (ret)
0260         goto apb_phy_fail;
0261 
0262     ret = clk_prepare_enable(phy->aclk);
0263     if (ret)
0264         goto aclk_fail;
0265 
0266     ret = clk_prepare_enable(phy->aux_clk);
0267     if (ret)
0268         goto aux_clk_fail;
0269 
0270     return 0;
0271 
0272 close_clk:
0273     clk_disable_unprepare(phy->aux_clk);
0274 aux_clk_fail:
0275     clk_disable_unprepare(phy->aclk);
0276 aclk_fail:
0277     clk_disable_unprepare(phy->apb_phy_clk);
0278 apb_phy_fail:
0279     clk_disable_unprepare(phy->apb_sys_clk);
0280 apb_sys_fail:
0281     clk_disable_unprepare(phy->phy_ref_clk);
0282 
0283     return ret;
0284 }
0285 
0286 static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie)
0287 {
0288     struct hi3660_pcie_phy *phy = pcie->phy_priv;
0289     int ret;
0290 
0291     /* Power supply for Host */
0292     regmap_write(phy->sysctrl,
0293              SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
0294     usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
0295 
0296     hi3660_pcie_phy_oe_enable(phy);
0297 
0298     ret = hi3660_pcie_phy_clk_ctrl(phy, true);
0299     if (ret)
0300         return ret;
0301 
0302     /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
0303     regmap_write(phy->sysctrl,
0304              SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
0305     regmap_write(phy->crgctrl,
0306              CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
0307     regmap_write(phy->sysctrl,
0308              SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
0309 
0310     ret = hi3660_pcie_phy_start(phy);
0311     if (ret)
0312         goto disable_clks;
0313 
0314     return 0;
0315 
0316 disable_clks:
0317     hi3660_pcie_phy_clk_ctrl(phy, false);
0318     return ret;
0319 }
0320 
0321 static int hi3660_pcie_phy_init(struct platform_device *pdev,
0322                 struct kirin_pcie *pcie)
0323 {
0324     struct device *dev = &pdev->dev;
0325     struct hi3660_pcie_phy *phy;
0326     int ret;
0327 
0328     phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
0329     if (!phy)
0330         return -ENOMEM;
0331 
0332     pcie->phy_priv = phy;
0333     phy->dev = dev;
0334 
0335     ret = hi3660_pcie_phy_get_clk(phy);
0336     if (ret)
0337         return ret;
0338 
0339     return hi3660_pcie_phy_get_resource(phy);
0340 }
0341 
0342 static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie)
0343 {
0344     struct hi3660_pcie_phy *phy = pcie->phy_priv;
0345 
0346     /* Drop power supply for Host */
0347     regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00);
0348 
0349     hi3660_pcie_phy_clk_ctrl(phy, false);
0350 
0351     return 0;
0352 }
0353 
0354 /*
0355  * The non-PHY part starts here
0356  */
0357 
0358 static const struct regmap_config pcie_kirin_regmap_conf = {
0359     .name = "kirin_pcie_apb",
0360     .reg_bits = 32,
0361     .val_bits = 32,
0362     .reg_stride = 4,
0363 };
0364 
0365 static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie,
0366                       struct platform_device *pdev)
0367 {
0368     struct device *dev = &pdev->dev;
0369     struct device_node *np = dev->of_node;
0370     char name[32];
0371     int ret, i;
0372 
0373     /* This is an optional property */
0374     ret = of_gpio_named_count(np, "hisilicon,clken-gpios");
0375     if (ret < 0)
0376         return 0;
0377 
0378     if (ret > MAX_PCI_SLOTS) {
0379         dev_err(dev, "Too many GPIO clock requests!\n");
0380         return -EINVAL;
0381     }
0382 
0383     pcie->n_gpio_clkreq = ret;
0384 
0385     for (i = 0; i < pcie->n_gpio_clkreq; i++) {
0386         pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node,
0387                             "hisilicon,clken-gpios", i);
0388         if (pcie->gpio_id_clkreq[i] < 0)
0389             return pcie->gpio_id_clkreq[i];
0390 
0391         sprintf(name, "pcie_clkreq_%d", i);
0392         pcie->clkreq_names[i] = devm_kstrdup_const(dev, name,
0393                                 GFP_KERNEL);
0394         if (!pcie->clkreq_names[i])
0395             return -ENOMEM;
0396     }
0397 
0398     return 0;
0399 }
0400 
0401 static int kirin_pcie_parse_port(struct kirin_pcie *pcie,
0402                  struct platform_device *pdev,
0403                  struct device_node *node)
0404 {
0405     struct device *dev = &pdev->dev;
0406     struct device_node *parent, *child;
0407     int ret, slot, i;
0408     char name[32];
0409 
0410     for_each_available_child_of_node(node, parent) {
0411         for_each_available_child_of_node(parent, child) {
0412             i = pcie->num_slots;
0413 
0414             pcie->gpio_id_reset[i] = of_get_named_gpio(child,
0415                             "reset-gpios", 0);
0416             if (pcie->gpio_id_reset[i] < 0)
0417                 continue;
0418 
0419             pcie->num_slots++;
0420             if (pcie->num_slots > MAX_PCI_SLOTS) {
0421                 dev_err(dev, "Too many PCI slots!\n");
0422                 ret = -EINVAL;
0423                 goto put_node;
0424             }
0425 
0426             ret = of_pci_get_devfn(child);
0427             if (ret < 0) {
0428                 dev_err(dev, "failed to parse devfn: %d\n", ret);
0429                 goto put_node;
0430             }
0431 
0432             slot = PCI_SLOT(ret);
0433 
0434             sprintf(name, "pcie_perst_%d", slot);
0435             pcie->reset_names[i] = devm_kstrdup_const(dev, name,
0436                                 GFP_KERNEL);
0437             if (!pcie->reset_names[i]) {
0438                 ret = -ENOMEM;
0439                 goto put_node;
0440             }
0441         }
0442     }
0443 
0444     return 0;
0445 
0446 put_node:
0447     of_node_put(child);
0448     of_node_put(parent);
0449     return ret;
0450 }
0451 
0452 static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
0453                     struct platform_device *pdev)
0454 {
0455     struct device *dev = &pdev->dev;
0456     struct device_node *child, *node = dev->of_node;
0457     void __iomem *apb_base;
0458     int ret;
0459 
0460     apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
0461     if (IS_ERR(apb_base))
0462         return PTR_ERR(apb_base);
0463 
0464     kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base,
0465                         &pcie_kirin_regmap_conf);
0466     if (IS_ERR(kirin_pcie->apb))
0467         return PTR_ERR(kirin_pcie->apb);
0468 
0469     /* pcie internal PERST# gpio */
0470     kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node,
0471                               "reset-gpios", 0);
0472     if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) {
0473         return -EPROBE_DEFER;
0474     } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) {
0475         dev_err(dev, "unable to get a valid gpio pin\n");
0476         return -ENODEV;
0477     }
0478 
0479     ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev);
0480     if (ret)
0481         return ret;
0482 
0483     /* Parse OF children */
0484     for_each_available_child_of_node(node, child) {
0485         ret = kirin_pcie_parse_port(kirin_pcie, pdev, child);
0486         if (ret)
0487             goto put_node;
0488     }
0489 
0490     return 0;
0491 
0492 put_node:
0493     of_node_put(child);
0494     return ret;
0495 }
0496 
0497 static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
0498                        bool on)
0499 {
0500     u32 val;
0501 
0502     regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val);
0503     if (on)
0504         val = val | PCIE_ELBI_SLV_DBI_ENABLE;
0505     else
0506         val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
0507 
0508     regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val);
0509 }
0510 
0511 static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
0512                        bool on)
0513 {
0514     u32 val;
0515 
0516     regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val);
0517     if (on)
0518         val = val | PCIE_ELBI_SLV_DBI_ENABLE;
0519     else
0520         val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
0521 
0522     regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val);
0523 }
0524 
0525 static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
0526                   int where, int size, u32 *val)
0527 {
0528     struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
0529 
0530     if (PCI_SLOT(devfn))
0531         return PCIBIOS_DEVICE_NOT_FOUND;
0532 
0533     *val = dw_pcie_read_dbi(pci, where, size);
0534     return PCIBIOS_SUCCESSFUL;
0535 }
0536 
0537 static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
0538                   int where, int size, u32 val)
0539 {
0540     struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
0541 
0542     if (PCI_SLOT(devfn))
0543         return PCIBIOS_DEVICE_NOT_FOUND;
0544 
0545     dw_pcie_write_dbi(pci, where, size, val);
0546     return PCIBIOS_SUCCESSFUL;
0547 }
0548 
0549 static int kirin_pcie_add_bus(struct pci_bus *bus)
0550 {
0551     struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
0552     struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
0553     int i, ret;
0554 
0555     if (!kirin_pcie->num_slots)
0556         return 0;
0557 
0558     /* Send PERST# to each slot */
0559     for (i = 0; i < kirin_pcie->num_slots; i++) {
0560         ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1);
0561         if (ret) {
0562             dev_err(pci->dev, "PERST# %s error: %d\n",
0563                 kirin_pcie->reset_names[i], ret);
0564         }
0565     }
0566     usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
0567 
0568     return 0;
0569 }
0570 
0571 static struct pci_ops kirin_pci_ops = {
0572     .read = kirin_pcie_rd_own_conf,
0573     .write = kirin_pcie_wr_own_conf,
0574     .add_bus = kirin_pcie_add_bus,
0575 };
0576 
0577 static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
0578                    u32 reg, size_t size)
0579 {
0580     struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
0581     u32 ret;
0582 
0583     kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
0584     dw_pcie_read(base + reg, size, &ret);
0585     kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
0586 
0587     return ret;
0588 }
0589 
0590 static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
0591                  u32 reg, size_t size, u32 val)
0592 {
0593     struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
0594 
0595     kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
0596     dw_pcie_write(base + reg, size, val);
0597     kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
0598 }
0599 
0600 static int kirin_pcie_link_up(struct dw_pcie *pci)
0601 {
0602     struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
0603     u32 val;
0604 
0605     regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val);
0606     if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
0607         return 1;
0608 
0609     return 0;
0610 }
0611 
0612 static int kirin_pcie_start_link(struct dw_pcie *pci)
0613 {
0614     struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
0615 
0616     /* assert LTSSM enable */
0617     regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE,
0618              PCIE_LTSSM_ENABLE_BIT);
0619 
0620     return 0;
0621 }
0622 
0623 static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
0624 {
0625     pp->bridge->ops = &kirin_pci_ops;
0626 
0627     return 0;
0628 }
0629 
0630 static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie,
0631                    struct device *dev)
0632 {
0633     int ret, i;
0634 
0635     for (i = 0; i < kirin_pcie->num_slots; i++) {
0636         if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) {
0637             dev_err(dev, "unable to get a valid %s gpio\n",
0638                 kirin_pcie->reset_names[i]);
0639             return -ENODEV;
0640         }
0641 
0642         ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i],
0643                     kirin_pcie->reset_names[i]);
0644         if (ret)
0645             return ret;
0646     }
0647 
0648     for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) {
0649         if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) {
0650             dev_err(dev, "unable to get a valid %s gpio\n",
0651                 kirin_pcie->clkreq_names[i]);
0652             return -ENODEV;
0653         }
0654 
0655         ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i],
0656                     kirin_pcie->clkreq_names[i]);
0657         if (ret)
0658             return ret;
0659 
0660         ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0);
0661         if (ret)
0662             return ret;
0663     }
0664 
0665     return 0;
0666 }
0667 
0668 static const struct dw_pcie_ops kirin_dw_pcie_ops = {
0669     .read_dbi = kirin_pcie_read_dbi,
0670     .write_dbi = kirin_pcie_write_dbi,
0671     .link_up = kirin_pcie_link_up,
0672     .start_link = kirin_pcie_start_link,
0673 };
0674 
0675 static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
0676     .host_init = kirin_pcie_host_init,
0677 };
0678 
0679 static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie)
0680 {
0681     int i;
0682 
0683     if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY)
0684         return hi3660_pcie_phy_power_off(kirin_pcie);
0685 
0686     for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++)
0687         gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1);
0688 
0689     phy_power_off(kirin_pcie->phy);
0690     phy_exit(kirin_pcie->phy);
0691 
0692     return 0;
0693 }
0694 
0695 static int kirin_pcie_power_on(struct platform_device *pdev,
0696                    struct kirin_pcie *kirin_pcie)
0697 {
0698     struct device *dev = &pdev->dev;
0699     int ret;
0700 
0701     if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) {
0702         ret = hi3660_pcie_phy_init(pdev, kirin_pcie);
0703         if (ret)
0704             return ret;
0705 
0706         ret = hi3660_pcie_phy_power_on(kirin_pcie);
0707         if (ret)
0708             return ret;
0709     } else {
0710         kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL);
0711         if (IS_ERR(kirin_pcie->phy))
0712             return PTR_ERR(kirin_pcie->phy);
0713 
0714         ret = kirin_pcie_gpio_request(kirin_pcie, dev);
0715         if (ret)
0716             return ret;
0717 
0718         ret = phy_init(kirin_pcie->phy);
0719         if (ret)
0720             goto err;
0721 
0722         ret = phy_power_on(kirin_pcie->phy);
0723         if (ret)
0724             goto err;
0725     }
0726 
0727     /* perst assert Endpoint */
0728     usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
0729 
0730     if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) {
0731         ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1);
0732         if (ret)
0733             goto err;
0734     }
0735 
0736     usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
0737 
0738     return 0;
0739 err:
0740     kirin_pcie_power_off(kirin_pcie);
0741 
0742     return ret;
0743 }
0744 
0745 static int __exit kirin_pcie_remove(struct platform_device *pdev)
0746 {
0747     struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev);
0748 
0749     dw_pcie_host_deinit(&kirin_pcie->pci->pp);
0750 
0751     kirin_pcie_power_off(kirin_pcie);
0752 
0753     return 0;
0754 }
0755 
0756 struct kirin_pcie_data {
0757     enum pcie_kirin_phy_type    phy_type;
0758 };
0759 
0760 static const struct kirin_pcie_data kirin_960_data = {
0761     .phy_type = PCIE_KIRIN_INTERNAL_PHY,
0762 };
0763 
0764 static const struct kirin_pcie_data kirin_970_data = {
0765     .phy_type = PCIE_KIRIN_EXTERNAL_PHY,
0766 };
0767 
0768 static const struct of_device_id kirin_pcie_match[] = {
0769     { .compatible = "hisilicon,kirin960-pcie", .data = &kirin_960_data },
0770     { .compatible = "hisilicon,kirin970-pcie", .data = &kirin_970_data },
0771     {},
0772 };
0773 
0774 static int kirin_pcie_probe(struct platform_device *pdev)
0775 {
0776     struct device *dev = &pdev->dev;
0777     const struct kirin_pcie_data *data;
0778     struct kirin_pcie *kirin_pcie;
0779     struct dw_pcie *pci;
0780     int ret;
0781 
0782     if (!dev->of_node) {
0783         dev_err(dev, "NULL node\n");
0784         return -EINVAL;
0785     }
0786 
0787     data = of_device_get_match_data(dev);
0788     if (!data) {
0789         dev_err(dev, "OF data missing\n");
0790         return -EINVAL;
0791     }
0792 
0793     kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
0794     if (!kirin_pcie)
0795         return -ENOMEM;
0796 
0797     pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
0798     if (!pci)
0799         return -ENOMEM;
0800 
0801     pci->dev = dev;
0802     pci->ops = &kirin_dw_pcie_ops;
0803     pci->pp.ops = &kirin_pcie_host_ops;
0804     kirin_pcie->pci = pci;
0805     kirin_pcie->type = data->phy_type;
0806 
0807     ret = kirin_pcie_get_resource(kirin_pcie, pdev);
0808     if (ret)
0809         return ret;
0810 
0811     platform_set_drvdata(pdev, kirin_pcie);
0812 
0813     ret = kirin_pcie_power_on(pdev, kirin_pcie);
0814     if (ret)
0815         return ret;
0816 
0817     return dw_pcie_host_init(&pci->pp);
0818 }
0819 
0820 static struct platform_driver kirin_pcie_driver = {
0821     .probe          = kirin_pcie_probe,
0822     .remove             = __exit_p(kirin_pcie_remove),
0823     .driver         = {
0824         .name           = "kirin-pcie",
0825         .of_match_table     = kirin_pcie_match,
0826         .suppress_bind_attrs    = true,
0827     },
0828 };
0829 module_platform_driver(kirin_pcie_driver);
0830 
0831 MODULE_DEVICE_TABLE(of, kirin_pcie_match);
0832 MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs");
0833 MODULE_AUTHOR("Xiaowei Song <songxiaowei@huawei.com>");
0834 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!