controller/dwc/pcie-fu740.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FU740 DesignWare PCIe Controller integration
0004  * Copyright (C) 2019-2021 SiFive, Inc.
0005  * Paul Walmsley
0006  * Greentime Hu
0007  *
0008  * Based in part on the i.MX6 PCIe host controller shim which is:
0009  *
0010  * Copyright (C) 2013 Kosagi
0011  *      https://www.kosagi.com
0012  */
0013
0014 #include <linux/clk.h>
0015 #include <linux/delay.h>
0016 #include <linux/gpio.h>
0017 #include <linux/gpio/consumer.h>
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/pci.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/resource.h>
0023 #include <linux/types.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/iopoll.h>
0026 #include <linux/reset.h>
0027
0028 #include "pcie-designware.h"
0029
0030 #define to_fu740_pcie(x)    dev_get_drvdata((x)->dev)
0031
0032 struct fu740_pcie {
0033     struct dw_pcie pci;
0034     void __iomem *mgmt_base;
0035     struct gpio_desc *reset;
0036     struct gpio_desc *pwren;
0037     struct clk *pcie_aux;
0038     struct reset_control *rst;
0039 };
0040
0041 #define SIFIVE_DEVICESRESETREG      0x28
0042
0043 #define PCIEX8MGMT_PERST_N      0x0
0044 #define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
0045 #define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
0046 #define PCIEX8MGMT_DEVICE_TYPE      0x708
0047 #define PCIEX8MGMT_PHY0_CR_PARA_ADDR    0x860
0048 #define PCIEX8MGMT_PHY0_CR_PARA_RD_EN   0x870
0049 #define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
0050 #define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
0051 #define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
0052 #define PCIEX8MGMT_PHY0_CR_PARA_WR_EN   0x890
0053 #define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
0054 #define PCIEX8MGMT_PHY1_CR_PARA_ADDR    0x8a0
0055 #define PCIEX8MGMT_PHY1_CR_PARA_RD_EN   0x8b0
0056 #define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
0057 #define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
0058 #define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
0059 #define PCIEX8MGMT_PHY1_CR_PARA_WR_EN   0x8d0
0060 #define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
0061
0062 #define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0)
0063 #define PCIEX8MGMT_PHY_LOS_THRSHLD  BIT(5)
0064 #define PCIEX8MGMT_PHY_TERM_EN      BIT(9)
0065 #define PCIEX8MGMT_PHY_TERM_ACDC    BIT(10)
0066 #define PCIEX8MGMT_PHY_EN       BIT(11)
0067 #define PCIEX8MGMT_PHY_INIT_VAL     (PCIEX8MGMT_PHY_CDR_TRACK_EN|\
0068                      PCIEX8MGMT_PHY_LOS_THRSHLD|\
0069                      PCIEX8MGMT_PHY_TERM_EN|\
0070                      PCIEX8MGMT_PHY_TERM_ACDC|\
0071                      PCIEX8MGMT_PHY_EN)
0072
0073 #define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3  0x1008
0074 #define PCIEX8MGMT_PHY_LANE_OFF     0x100
0075 #define PCIEX8MGMT_PHY_LANE0_BASE   (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0)
0076 #define PCIEX8MGMT_PHY_LANE1_BASE   (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1)
0077 #define PCIEX8MGMT_PHY_LANE2_BASE   (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2)
0078 #define PCIEX8MGMT_PHY_LANE3_BASE   (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3)
0079
0080 static void fu740_pcie_assert_reset(struct fu740_pcie *afp)
0081 {
0082     /* Assert PERST_N GPIO */
0083     gpiod_set_value_cansleep(afp->reset, 0);
0084     /* Assert controller PERST_N */
0085     writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);
0086 }
0087
0088 static void fu740_pcie_deassert_reset(struct fu740_pcie *afp)
0089 {
0090     /* Deassert controller PERST_N */
0091     writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);
0092     /* Deassert PERST_N GPIO */
0093     gpiod_set_value_cansleep(afp->reset, 1);
0094 }
0095
0096 static void fu740_pcie_power_on(struct fu740_pcie *afp)
0097 {
0098     gpiod_set_value_cansleep(afp->pwren, 1);
0099     /*
0100      * Ensure that PERST has been asserted for at least 100 ms.
0101      * Section 2.2 of PCI Express Card Electromechanical Specification
0102      * Revision 3.0
0103      */
0104     msleep(100);
0105 }
0106
0107 static void fu740_pcie_drive_reset(struct fu740_pcie *afp)
0108 {
0109     fu740_pcie_assert_reset(afp);
0110     fu740_pcie_power_on(afp);
0111     fu740_pcie_deassert_reset(afp);
0112 }
0113
0114 static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr,
0115                   const uint16_t wrdata, struct fu740_pcie *afp)
0116 {
0117     struct device *dev = afp->pci.dev;
0118     void __iomem *phy_cr_para_addr;
0119     void __iomem *phy_cr_para_wr_data;
0120     void __iomem *phy_cr_para_wr_en;
0121     void __iomem *phy_cr_para_ack;
0122     int ret, val;
0123
0124     /* Setup */
0125     if (phy) {
0126         phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;
0127         phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA;
0128         phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;
0129         phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;
0130     } else {
0131         phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;
0132         phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA;
0133         phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;
0134         phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;
0135     }
0136
0137     writel_relaxed(addr, phy_cr_para_addr);
0138     writel_relaxed(wrdata, phy_cr_para_wr_data);
0139     writel_relaxed(1, phy_cr_para_wr_en);
0140
0141     /* Wait for wait_idle */
0142     ret = readl_poll_timeout(phy_cr_para_ack, val, val, 10, 5000);
0143     if (ret)
0144         dev_warn(dev, "Wait for wait_idle state failed!\n");
0145
0146     /* Clear */
0147     writel_relaxed(0, phy_cr_para_wr_en);
0148
0149     /* Wait for ~wait_idle */
0150     ret = readl_poll_timeout(phy_cr_para_ack, val, !val, 10, 5000);
0151     if (ret)
0152         dev_warn(dev, "Wait for !wait_idle state failed!\n");
0153 }
0154
0155 static void fu740_pcie_init_phy(struct fu740_pcie *afp)
0156 {
0157     /* Enable phy cr_para_sel interfaces */
0158     writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
0159     writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
0160
0161     /*
0162      * Wait 10 cr_para cycles to guarantee that the registers are ready
0163      * to be edited.
0164      */
0165     ndelay(10);
0166
0167     /* Set PHY AC termination mode */
0168     fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0169     fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0170     fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0171     fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0172     fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0173     fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0174     fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0175     fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
0176 }
0177
0178 static int fu740_pcie_start_link(struct dw_pcie *pci)
0179 {
0180     struct device *dev = pci->dev;
0181     struct fu740_pcie *afp = dev_get_drvdata(dev);
0182     u8 cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
0183     int ret;
0184     u32 orig, tmp;
0185
0186     /*
0187      * Force 2.5GT/s when starting the link, due to some devices not
0188      * probing at higher speeds. This happens with the PCIe switch
0189      * on the Unmatched board when U-Boot has not initialised the PCIe.
0190      * The fix in U-Boot is to force 2.5GT/s, which then gets cleared
0191      * by the soft reset done by this driver.
0192      */
0193     dev_dbg(dev, "cap_exp at %x\n", cap_exp);
0194     dw_pcie_dbi_ro_wr_en(pci);
0195
0196     tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
0197     orig = tmp & PCI_EXP_LNKCAP_SLS;
0198     tmp &= ~PCI_EXP_LNKCAP_SLS;
0199     tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
0200     dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
0201
0202     /* Enable LTSSM */
0203     writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
0204
0205     ret = dw_pcie_wait_for_link(pci);
0206     if (ret) {
0207         dev_err(dev, "error: link did not start\n");
0208         goto err;
0209     }
0210
0211     tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
0212     if ((tmp & PCI_EXP_LNKCAP_SLS) != orig) {
0213         dev_dbg(dev, "changing speed back to original\n");
0214
0215         tmp &= ~PCI_EXP_LNKCAP_SLS;
0216         tmp |= orig;
0217         dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
0218
0219         tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
0220         tmp |= PORT_LOGIC_SPEED_CHANGE;
0221         dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
0222
0223         ret = dw_pcie_wait_for_link(pci);
0224         if (ret) {
0225             dev_err(dev, "error: link did not start at new speed\n");
0226             goto err;
0227         }
0228     }
0229
0230     ret = 0;
0231 err:
0232     WARN_ON(ret);   /* we assume that errors will be very rare */
0233     dw_pcie_dbi_ro_wr_dis(pci);
0234     return ret;
0235 }
0236
0237 static int fu740_pcie_host_init(struct dw_pcie_rp *pp)
0238 {
0239     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0240     struct fu740_pcie *afp = to_fu740_pcie(pci);
0241     struct device *dev = pci->dev;
0242     int ret;
0243
0244     /* Power on reset */
0245     fu740_pcie_drive_reset(afp);
0246
0247     /* Enable pcieauxclk */
0248     ret = clk_prepare_enable(afp->pcie_aux);
0249     if (ret) {
0250         dev_err(dev, "unable to enable pcie_aux clock\n");
0251         return ret;
0252     }
0253
0254     /*
0255      * Assert hold_phy_rst (hold the controller LTSSM in reset after
0256      * power_up_rst_n for register programming with cr_para)
0257      */
0258     writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
0259
0260     /* Deassert power_up_rst_n */
0261     ret = reset_control_deassert(afp->rst);
0262     if (ret) {
0263         dev_err(dev, "unable to deassert pcie_power_up_rst_n\n");
0264         return ret;
0265     }
0266
0267     fu740_pcie_init_phy(afp);
0268
0269     /* Disable pcieauxclk */
0270     clk_disable_unprepare(afp->pcie_aux);
0271     /* Clear hold_phy_rst */
0272     writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
0273     /* Enable pcieauxclk */
0274     clk_prepare_enable(afp->pcie_aux);
0275     /* Set RC mode */
0276     writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);
0277
0278     return 0;
0279 }
0280
0281 static const struct dw_pcie_host_ops fu740_pcie_host_ops = {
0282     .host_init = fu740_pcie_host_init,
0283 };
0284
0285 static const struct dw_pcie_ops dw_pcie_ops = {
0286     .start_link = fu740_pcie_start_link,
0287 };
0288
0289 static int fu740_pcie_probe(struct platform_device *pdev)
0290 {
0291     struct device *dev = &pdev->dev;
0292     struct dw_pcie *pci;
0293     struct fu740_pcie *afp;
0294
0295     afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL);
0296     if (!afp)
0297         return -ENOMEM;
0298     pci = &afp->pci;
0299     pci->dev = dev;
0300     pci->ops = &dw_pcie_ops;
0301     pci->pp.ops = &fu740_pcie_host_ops;
0302
0303     /* SiFive specific region: mgmt */
0304     afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");
0305     if (IS_ERR(afp->mgmt_base))
0306         return PTR_ERR(afp->mgmt_base);
0307
0308     /* Fetch GPIOs */
0309     afp->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
0310     if (IS_ERR(afp->reset))
0311         return dev_err_probe(dev, PTR_ERR(afp->reset), "unable to get reset-gpios\n");
0312
0313     afp->pwren = devm_gpiod_get_optional(dev, "pwren", GPIOD_OUT_LOW);
0314     if (IS_ERR(afp->pwren))
0315         return dev_err_probe(dev, PTR_ERR(afp->pwren), "unable to get pwren-gpios\n");
0316
0317     /* Fetch clocks */
0318     afp->pcie_aux = devm_clk_get(dev, "pcie_aux");
0319     if (IS_ERR(afp->pcie_aux))
0320         return dev_err_probe(dev, PTR_ERR(afp->pcie_aux),
0321                          "pcie_aux clock source missing or invalid\n");
0322
0323     /* Fetch reset */
0324     afp->rst = devm_reset_control_get_exclusive(dev, NULL);
0325     if (IS_ERR(afp->rst))
0326         return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n");
0327
0328     platform_set_drvdata(pdev, afp);
0329
0330     return dw_pcie_host_init(&pci->pp);
0331 }
0332
0333 static void fu740_pcie_shutdown(struct platform_device *pdev)
0334 {
0335     struct fu740_pcie *afp = platform_get_drvdata(pdev);
0336
0337     /* Bring down link, so bootloader gets clean state in case of reboot */
0338     fu740_pcie_assert_reset(afp);
0339 }
0340
0341 static const struct of_device_id fu740_pcie_of_match[] = {
0342     { .compatible = "sifive,fu740-pcie", },
0343     {},
0344 };
0345
0346 static struct platform_driver fu740_pcie_driver = {
0347     .driver = {
0348            .name = "fu740-pcie",
0349            .of_match_table = fu740_pcie_of_match,
0350            .suppress_bind_attrs = true,
0351     },
0352     .probe = fu740_pcie_probe,
0353     .shutdown = fu740_pcie_shutdown,
0354 };
0355
0356 builtin_platform_driver(fu740_pcie_driver);