controller/dwc/pci-meson.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe host controller driver for Amlogic MESON SoCs
0004  *
0005  * Copyright (c) 2018 Amlogic, inc.
0006  * Author: Yue Wang <yue.wang@amlogic.com>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_gpio.h>
0014 #include <linux/pci.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/reset.h>
0017 #include <linux/resource.h>
0018 #include <linux/types.h>
0019 #include <linux/phy/phy.h>
0020 #include <linux/module.h>
0021
0022 #include "pcie-designware.h"
0023
0024 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
0025
0026 #define PCIE_CAP_MAX_PAYLOAD_SIZE(x)    ((x) << 5)
0027 #define PCIE_CAP_MAX_READ_REQ_SIZE(x)   ((x) << 12)
0028
0029 /* PCIe specific config registers */
0030 #define PCIE_CFG0           0x0
0031 #define APP_LTSSM_ENABLE        BIT(7)
0032
0033 #define PCIE_CFG_STATUS12       0x30
0034 #define IS_SMLH_LINK_UP(x)      ((x) & (1 << 6))
0035 #define IS_RDLH_LINK_UP(x)      ((x) & (1 << 16))
0036 #define IS_LTSSM_UP(x)          ((((x) >> 10) & 0x1f) == 0x11)
0037
0038 #define PCIE_CFG_STATUS17       0x44
0039 #define PM_CURRENT_STATE(x)     (((x) >> 7) & 0x1)
0040
0041 #define WAIT_LINKUP_TIMEOUT     4000
0042 #define PORT_CLK_RATE           100000000UL
0043 #define MAX_PAYLOAD_SIZE        256
0044 #define MAX_READ_REQ_SIZE       256
0045 #define PCIE_RESET_DELAY        500
0046 #define PCIE_SHARED_RESET       1
0047 #define PCIE_NORMAL_RESET       0
0048
0049 enum pcie_data_rate {
0050     PCIE_GEN1,
0051     PCIE_GEN2,
0052     PCIE_GEN3,
0053     PCIE_GEN4
0054 };
0055
0056 struct meson_pcie_clk_res {
0057     struct clk *clk;
0058     struct clk *port_clk;
0059     struct clk *general_clk;
0060 };
0061
0062 struct meson_pcie_rc_reset {
0063     struct reset_control *port;
0064     struct reset_control *apb;
0065 };
0066
0067 struct meson_pcie {
0068     struct dw_pcie pci;
0069     void __iomem *cfg_base;
0070     struct meson_pcie_clk_res clk_res;
0071     struct meson_pcie_rc_reset mrst;
0072     struct gpio_desc *reset_gpio;
0073     struct phy *phy;
0074 };
0075
0076 static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
0077                           const char *id,
0078                           u32 reset_type)
0079 {
0080     struct device *dev = mp->pci.dev;
0081     struct reset_control *reset;
0082
0083     if (reset_type == PCIE_SHARED_RESET)
0084         reset = devm_reset_control_get_shared(dev, id);
0085     else
0086         reset = devm_reset_control_get(dev, id);
0087
0088     return reset;
0089 }
0090
0091 static int meson_pcie_get_resets(struct meson_pcie *mp)
0092 {
0093     struct meson_pcie_rc_reset *mrst = &mp->mrst;
0094
0095     mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
0096     if (IS_ERR(mrst->port))
0097         return PTR_ERR(mrst->port);
0098     reset_control_deassert(mrst->port);
0099
0100     mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
0101     if (IS_ERR(mrst->apb))
0102         return PTR_ERR(mrst->apb);
0103     reset_control_deassert(mrst->apb);
0104
0105     return 0;
0106 }
0107
0108 static int meson_pcie_get_mems(struct platform_device *pdev,
0109                    struct meson_pcie *mp)
0110 {
0111     struct dw_pcie *pci = &mp->pci;
0112
0113     pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
0114     if (IS_ERR(pci->dbi_base))
0115         return PTR_ERR(pci->dbi_base);
0116
0117     mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
0118     if (IS_ERR(mp->cfg_base))
0119         return PTR_ERR(mp->cfg_base);
0120
0121     return 0;
0122 }
0123
0124 static int meson_pcie_power_on(struct meson_pcie *mp)
0125 {
0126     int ret = 0;
0127
0128     ret = phy_init(mp->phy);
0129     if (ret)
0130         return ret;
0131
0132     ret = phy_power_on(mp->phy);
0133     if (ret) {
0134         phy_exit(mp->phy);
0135         return ret;
0136     }
0137
0138     return 0;
0139 }
0140
0141 static void meson_pcie_power_off(struct meson_pcie *mp)
0142 {
0143     phy_power_off(mp->phy);
0144     phy_exit(mp->phy);
0145 }
0146
0147 static int meson_pcie_reset(struct meson_pcie *mp)
0148 {
0149     struct meson_pcie_rc_reset *mrst = &mp->mrst;
0150     int ret = 0;
0151
0152     ret = phy_reset(mp->phy);
0153     if (ret)
0154         return ret;
0155
0156     reset_control_assert(mrst->port);
0157     reset_control_assert(mrst->apb);
0158     udelay(PCIE_RESET_DELAY);
0159     reset_control_deassert(mrst->port);
0160     reset_control_deassert(mrst->apb);
0161     udelay(PCIE_RESET_DELAY);
0162
0163     return 0;
0164 }
0165
0166 static inline struct clk *meson_pcie_probe_clock(struct device *dev,
0167                          const char *id, u64 rate)
0168 {
0169     struct clk *clk;
0170     int ret;
0171
0172     clk = devm_clk_get(dev, id);
0173     if (IS_ERR(clk))
0174         return clk;
0175
0176     if (rate) {
0177         ret = clk_set_rate(clk, rate);
0178         if (ret) {
0179             dev_err(dev, "set clk rate failed, ret = %d\n", ret);
0180             return ERR_PTR(ret);
0181         }
0182     }
0183
0184     ret = clk_prepare_enable(clk);
0185     if (ret) {
0186         dev_err(dev, "couldn't enable clk\n");
0187         return ERR_PTR(ret);
0188     }
0189
0190     devm_add_action_or_reset(dev,
0191                  (void (*) (void *))clk_disable_unprepare,
0192                  clk);
0193
0194     return clk;
0195 }
0196
0197 static int meson_pcie_probe_clocks(struct meson_pcie *mp)
0198 {
0199     struct device *dev = mp->pci.dev;
0200     struct meson_pcie_clk_res *res = &mp->clk_res;
0201
0202     res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
0203     if (IS_ERR(res->port_clk))
0204         return PTR_ERR(res->port_clk);
0205
0206     res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
0207     if (IS_ERR(res->general_clk))
0208         return PTR_ERR(res->general_clk);
0209
0210     res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
0211     if (IS_ERR(res->clk))
0212         return PTR_ERR(res->clk);
0213
0214     return 0;
0215 }
0216
0217 static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
0218 {
0219     return readl(mp->cfg_base + reg);
0220 }
0221
0222 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
0223 {
0224     writel(val, mp->cfg_base + reg);
0225 }
0226
0227 static void meson_pcie_assert_reset(struct meson_pcie *mp)
0228 {
0229     gpiod_set_value_cansleep(mp->reset_gpio, 1);
0230     udelay(500);
0231     gpiod_set_value_cansleep(mp->reset_gpio, 0);
0232 }
0233
0234 static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
0235 {
0236     u32 val;
0237
0238     val = meson_cfg_readl(mp, PCIE_CFG0);
0239     val |= APP_LTSSM_ENABLE;
0240     meson_cfg_writel(mp, val, PCIE_CFG0);
0241 }
0242
0243 static int meson_size_to_payload(struct meson_pcie *mp, int size)
0244 {
0245     struct device *dev = mp->pci.dev;
0246
0247     /*
0248      * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
0249      * So if input size is not 2^order alignment or less than 2^7 or bigger
0250      * than 2^12, just set to default size 2^(1+7).
0251      */
0252     if (!is_power_of_2(size) || size < 128 || size > 4096) {
0253         dev_warn(dev, "payload size %d, set to default 256\n", size);
0254         return 1;
0255     }
0256
0257     return fls(size) - 8;
0258 }
0259
0260 static void meson_set_max_payload(struct meson_pcie *mp, int size)
0261 {
0262     struct dw_pcie *pci = &mp->pci;
0263     u32 val;
0264     u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
0265     int max_payload_size = meson_size_to_payload(mp, size);
0266
0267     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
0268     val &= ~PCI_EXP_DEVCTL_PAYLOAD;
0269     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
0270
0271     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
0272     val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
0273     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
0274 }
0275
0276 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
0277 {
0278     struct dw_pcie *pci = &mp->pci;
0279     u32 val;
0280     u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
0281     int max_rd_req_size = meson_size_to_payload(mp, size);
0282
0283     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
0284     val &= ~PCI_EXP_DEVCTL_READRQ;
0285     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
0286
0287     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
0288     val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
0289     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
0290 }
0291
0292 static int meson_pcie_start_link(struct dw_pcie *pci)
0293 {
0294     struct meson_pcie *mp = to_meson_pcie(pci);
0295
0296     meson_pcie_ltssm_enable(mp);
0297     meson_pcie_assert_reset(mp);
0298
0299     return 0;
0300 }
0301
0302 static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
0303                   int where, int size, u32 *val)
0304 {
0305     int ret;
0306
0307     ret = pci_generic_config_read(bus, devfn, where, size, val);
0308     if (ret != PCIBIOS_SUCCESSFUL)
0309         return ret;
0310
0311     /*
0312      * There is a bug in the MESON AXG PCIe controller whereby software
0313      * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
0314      * the return value in the config accessors.
0315      */
0316     if ((where & ~3) == PCI_CLASS_REVISION) {
0317         if (size <= 2)
0318             *val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
0319         *val &= ~0xffffff00;
0320         *val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
0321         if (size <= 2)
0322             *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
0323     }
0324
0325     return PCIBIOS_SUCCESSFUL;
0326 }
0327
0328 static struct pci_ops meson_pci_ops = {
0329     .map_bus = dw_pcie_own_conf_map_bus,
0330     .read = meson_pcie_rd_own_conf,
0331     .write = pci_generic_config_write,
0332 };
0333
0334 static int meson_pcie_link_up(struct dw_pcie *pci)
0335 {
0336     struct meson_pcie *mp = to_meson_pcie(pci);
0337     struct device *dev = pci->dev;
0338     u32 speed_okay = 0;
0339     u32 cnt = 0;
0340     u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
0341
0342     do {
0343         state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
0344         state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
0345         smlh_up = IS_SMLH_LINK_UP(state12);
0346         rdlh_up = IS_RDLH_LINK_UP(state12);
0347         ltssm_up = IS_LTSSM_UP(state12);
0348
0349         if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
0350             speed_okay = 1;
0351
0352         if (smlh_up)
0353             dev_dbg(dev, "smlh_link_up is on\n");
0354         if (rdlh_up)
0355             dev_dbg(dev, "rdlh_link_up is on\n");
0356         if (ltssm_up)
0357             dev_dbg(dev, "ltssm_up is on\n");
0358         if (speed_okay)
0359             dev_dbg(dev, "speed_okay\n");
0360
0361         if (smlh_up && rdlh_up && ltssm_up && speed_okay)
0362             return 1;
0363
0364         cnt++;
0365
0366         udelay(10);
0367     } while (cnt < WAIT_LINKUP_TIMEOUT);
0368
0369     dev_err(dev, "error: wait linkup timeout\n");
0370     return 0;
0371 }
0372
0373 static int meson_pcie_host_init(struct dw_pcie_rp *pp)
0374 {
0375     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0376     struct meson_pcie *mp = to_meson_pcie(pci);
0377
0378     pp->bridge->ops = &meson_pci_ops;
0379
0380     meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
0381     meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
0382
0383     return 0;
0384 }
0385
0386 static const struct dw_pcie_host_ops meson_pcie_host_ops = {
0387     .host_init = meson_pcie_host_init,
0388 };
0389
0390 static const struct dw_pcie_ops dw_pcie_ops = {
0391     .link_up = meson_pcie_link_up,
0392     .start_link = meson_pcie_start_link,
0393 };
0394
0395 static int meson_pcie_probe(struct platform_device *pdev)
0396 {
0397     struct device *dev = &pdev->dev;
0398     struct dw_pcie *pci;
0399     struct meson_pcie *mp;
0400     int ret;
0401
0402     mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
0403     if (!mp)
0404         return -ENOMEM;
0405
0406     pci = &mp->pci;
0407     pci->dev = dev;
0408     pci->ops = &dw_pcie_ops;
0409     pci->pp.ops = &meson_pcie_host_ops;
0410     pci->num_lanes = 1;
0411
0412     mp->phy = devm_phy_get(dev, "pcie");
0413     if (IS_ERR(mp->phy)) {
0414         dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
0415         return PTR_ERR(mp->phy);
0416     }
0417
0418     mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
0419     if (IS_ERR(mp->reset_gpio)) {
0420         dev_err(dev, "get reset gpio failed\n");
0421         return PTR_ERR(mp->reset_gpio);
0422     }
0423
0424     ret = meson_pcie_get_resets(mp);
0425     if (ret) {
0426         dev_err(dev, "get reset resource failed, %d\n", ret);
0427         return ret;
0428     }
0429
0430     ret = meson_pcie_get_mems(pdev, mp);
0431     if (ret) {
0432         dev_err(dev, "get memory resource failed, %d\n", ret);
0433         return ret;
0434     }
0435
0436     ret = meson_pcie_power_on(mp);
0437     if (ret) {
0438         dev_err(dev, "phy power on failed, %d\n", ret);
0439         return ret;
0440     }
0441
0442     ret = meson_pcie_reset(mp);
0443     if (ret) {
0444         dev_err(dev, "reset failed, %d\n", ret);
0445         goto err_phy;
0446     }
0447
0448     ret = meson_pcie_probe_clocks(mp);
0449     if (ret) {
0450         dev_err(dev, "init clock resources failed, %d\n", ret);
0451         goto err_phy;
0452     }
0453
0454     platform_set_drvdata(pdev, mp);
0455
0456     ret = dw_pcie_host_init(&pci->pp);
0457     if (ret < 0) {
0458         dev_err(dev, "Add PCIe port failed, %d\n", ret);
0459         goto err_phy;
0460     }
0461
0462     return 0;
0463
0464 err_phy:
0465     meson_pcie_power_off(mp);
0466     return ret;
0467 }
0468
0469 static const struct of_device_id meson_pcie_of_match[] = {
0470     {
0471         .compatible = "amlogic,axg-pcie",
0472     },
0473     {
0474         .compatible = "amlogic,g12a-pcie",
0475     },
0476     {},
0477 };
0478 MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
0479
0480 static struct platform_driver meson_pcie_driver = {
0481     .probe = meson_pcie_probe,
0482     .driver = {
0483         .name = "meson-pcie",
0484         .of_match_table = meson_pcie_of_match,
0485     },
0486 };
0487
0488 module_platform_driver(meson_pcie_driver);
0489
0490 MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
0491 MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
0492 MODULE_LICENSE("GPL v2");