controller/dwc/pci-layerscape.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe host controller driver for Freescale Layerscape SoCs
0004  *
0005  * Copyright (C) 2014 Freescale Semiconductor.
0006  * Copyright 2021 NXP
0007  *
0008  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/init.h>
0014 #include <linux/of_pci.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/of_address.h>
0018 #include <linux/pci.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/resource.h>
0021 #include <linux/mfd/syscon.h>
0022 #include <linux/regmap.h>
0023
0024 #include "pcie-designware.h"
0025
0026 /* PEX Internal Configuration Registers */
0027 #define PCIE_STRFMR1        0x71c /* Symbol Timer & Filter Mask Register1 */
0028 #define PCIE_ABSERR     0x8d0 /* Bridge Slave Error Response Register */
0029 #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
0030
0031 #define PCIE_IATU_NUM       6
0032
0033 struct ls_pcie {
0034     struct dw_pcie *pci;
0035 };
0036
0037 #define to_ls_pcie(x)   dev_get_drvdata((x)->dev)
0038
0039 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
0040 {
0041     struct dw_pcie *pci = pcie->pci;
0042     u32 header_type;
0043
0044     header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
0045     header_type &= 0x7f;
0046
0047     return header_type == PCI_HEADER_TYPE_BRIDGE;
0048 }
0049
0050 /* Clear multi-function bit */
0051 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
0052 {
0053     struct dw_pcie *pci = pcie->pci;
0054
0055     iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
0056 }
0057
0058 /* Drop MSG TLP except for Vendor MSG */
0059 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
0060 {
0061     u32 val;
0062     struct dw_pcie *pci = pcie->pci;
0063
0064     val = ioread32(pci->dbi_base + PCIE_STRFMR1);
0065     val &= 0xDFFFFFFF;
0066     iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
0067 }
0068
0069 /* Forward error response of outbound non-posted requests */
0070 static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
0071 {
0072     struct dw_pcie *pci = pcie->pci;
0073
0074     iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
0075 }
0076
0077 static int ls_pcie_host_init(struct dw_pcie_rp *pp)
0078 {
0079     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0080     struct ls_pcie *pcie = to_ls_pcie(pci);
0081
0082     ls_pcie_fix_error_response(pcie);
0083
0084     dw_pcie_dbi_ro_wr_en(pci);
0085     ls_pcie_clear_multifunction(pcie);
0086     dw_pcie_dbi_ro_wr_dis(pci);
0087
0088     ls_pcie_drop_msg_tlp(pcie);
0089
0090     return 0;
0091 }
0092
0093 static const struct dw_pcie_host_ops ls_pcie_host_ops = {
0094     .host_init = ls_pcie_host_init,
0095 };
0096
0097 static const struct of_device_id ls_pcie_of_match[] = {
0098     { .compatible = "fsl,ls1012a-pcie", },
0099     { .compatible = "fsl,ls1021a-pcie", },
0100     { .compatible = "fsl,ls1028a-pcie", },
0101     { .compatible = "fsl,ls1043a-pcie", },
0102     { .compatible = "fsl,ls1046a-pcie", },
0103     { .compatible = "fsl,ls2080a-pcie", },
0104     { .compatible = "fsl,ls2085a-pcie", },
0105     { .compatible = "fsl,ls2088a-pcie", },
0106     { .compatible = "fsl,ls1088a-pcie", },
0107     { },
0108 };
0109
0110 static int ls_pcie_probe(struct platform_device *pdev)
0111 {
0112     struct device *dev = &pdev->dev;
0113     struct dw_pcie *pci;
0114     struct ls_pcie *pcie;
0115     struct resource *dbi_base;
0116
0117     pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
0118     if (!pcie)
0119         return -ENOMEM;
0120
0121     pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
0122     if (!pci)
0123         return -ENOMEM;
0124
0125     pci->dev = dev;
0126     pci->pp.ops = &ls_pcie_host_ops;
0127
0128     pcie->pci = pci;
0129
0130     dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
0131     pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
0132     if (IS_ERR(pci->dbi_base))
0133         return PTR_ERR(pci->dbi_base);
0134
0135     if (!ls_pcie_is_bridge(pcie))
0136         return -ENODEV;
0137
0138     platform_set_drvdata(pdev, pcie);
0139
0140     return dw_pcie_host_init(&pci->pp);
0141 }
0142
0143 static struct platform_driver ls_pcie_driver = {
0144     .probe = ls_pcie_probe,
0145     .driver = {
0146         .name = "layerscape-pcie",
0147         .of_match_table = ls_pcie_of_match,
0148         .suppress_bind_attrs = true,
0149     },
0150 };
0151 builtin_platform_driver(ls_pcie_driver);