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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe host controller driver for Freescale i.MX6 SoCs
0004  *
0005  * Copyright (C) 2013 Kosagi
0006  *      https://www.kosagi.com
0007  *
0008  * Author: Sean Cross <xobs@kosagi.com>
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/gpio.h>
0015 #include <linux/kernel.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
0018 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
0019 #include <linux/module.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/of_device.h>
0022 #include <linux/of_address.h>
0023 #include <linux/pci.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/regmap.h>
0026 #include <linux/regulator/consumer.h>
0027 #include <linux/resource.h>
0028 #include <linux/signal.h>
0029 #include <linux/types.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/reset.h>
0032 #include <linux/phy/phy.h>
0033 #include <linux/pm_domain.h>
0034 #include <linux/pm_runtime.h>
0035 
0036 #include "pcie-designware.h"
0037 
0038 #define IMX8MQ_GPR_PCIE_REF_USE_PAD     BIT(9)
0039 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
0040 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE    BIT(11)
0041 #define IMX8MQ_GPR_PCIE_VREG_BYPASS     BIT(12)
0042 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
0043 #define IMX8MQ_PCIE2_BASE_ADDR          0x33c00000
0044 
0045 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
0046 
0047 enum imx6_pcie_variants {
0048     IMX6Q,
0049     IMX6SX,
0050     IMX6QP,
0051     IMX7D,
0052     IMX8MQ,
0053     IMX8MM,
0054 };
0055 
0056 #define IMX6_PCIE_FLAG_IMX6_PHY         BIT(0)
0057 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE    BIT(1)
0058 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND     BIT(2)
0059 
0060 struct imx6_pcie_drvdata {
0061     enum imx6_pcie_variants variant;
0062     u32 flags;
0063     int dbi_length;
0064 };
0065 
0066 struct imx6_pcie {
0067     struct dw_pcie      *pci;
0068     int         reset_gpio;
0069     bool            gpio_active_high;
0070     bool            link_is_up;
0071     struct clk      *pcie_bus;
0072     struct clk      *pcie_phy;
0073     struct clk      *pcie_inbound_axi;
0074     struct clk      *pcie;
0075     struct clk      *pcie_aux;
0076     struct regmap       *iomuxc_gpr;
0077     u32         controller_id;
0078     struct reset_control    *pciephy_reset;
0079     struct reset_control    *apps_reset;
0080     struct reset_control    *turnoff_reset;
0081     u32         tx_deemph_gen1;
0082     u32         tx_deemph_gen2_3p5db;
0083     u32         tx_deemph_gen2_6db;
0084     u32         tx_swing_full;
0085     u32         tx_swing_low;
0086     struct regulator    *vpcie;
0087     struct regulator    *vph;
0088     void __iomem        *phy_base;
0089 
0090     /* power domain for pcie */
0091     struct device       *pd_pcie;
0092     /* power domain for pcie phy */
0093     struct device       *pd_pcie_phy;
0094     struct phy      *phy;
0095     const struct imx6_pcie_drvdata *drvdata;
0096 };
0097 
0098 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
0099 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX    200
0100 #define PHY_PLL_LOCK_WAIT_TIMEOUT   (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
0101 
0102 /* PCIe Port Logic registers (memory-mapped) */
0103 #define PL_OFFSET 0x700
0104 
0105 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
0106 #define PCIE_PHY_CTRL_DATA(x)       FIELD_PREP(GENMASK(15, 0), (x))
0107 #define PCIE_PHY_CTRL_CAP_ADR       BIT(16)
0108 #define PCIE_PHY_CTRL_CAP_DAT       BIT(17)
0109 #define PCIE_PHY_CTRL_WR        BIT(18)
0110 #define PCIE_PHY_CTRL_RD        BIT(19)
0111 
0112 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
0113 #define PCIE_PHY_STAT_ACK       BIT(16)
0114 
0115 /* PHY registers (not memory-mapped) */
0116 #define PCIE_PHY_ATEOVRD            0x10
0117 #define  PCIE_PHY_ATEOVRD_EN            BIT(2)
0118 #define  PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT  0
0119 #define  PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK   0x1
0120 
0121 #define PCIE_PHY_MPLL_OVRD_IN_LO        0x11
0122 #define  PCIE_PHY_MPLL_MULTIPLIER_SHIFT     2
0123 #define  PCIE_PHY_MPLL_MULTIPLIER_MASK      0x7f
0124 #define  PCIE_PHY_MPLL_MULTIPLIER_OVRD      BIT(9)
0125 
0126 #define PCIE_PHY_RX_ASIC_OUT 0x100D
0127 #define PCIE_PHY_RX_ASIC_OUT_VALID  (1 << 0)
0128 
0129 /* iMX7 PCIe PHY registers */
0130 #define PCIE_PHY_CMN_REG4       0x14
0131 /* These are probably the bits that *aren't* DCC_FB_EN */
0132 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
0133 
0134 #define PCIE_PHY_CMN_REG15          0x54
0135 #define PCIE_PHY_CMN_REG15_DLY_4    BIT(2)
0136 #define PCIE_PHY_CMN_REG15_PLL_PD   BIT(5)
0137 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD  BIT(7)
0138 
0139 #define PCIE_PHY_CMN_REG24      0x90
0140 #define PCIE_PHY_CMN_REG24_RX_EQ    BIT(6)
0141 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL    BIT(3)
0142 
0143 #define PCIE_PHY_CMN_REG26      0x98
0144 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
0145 
0146 #define PHY_RX_OVRD_IN_LO 0x1005
0147 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN        BIT(5)
0148 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN     BIT(3)
0149 
0150 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
0151 {
0152     WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
0153         imx6_pcie->drvdata->variant != IMX8MM);
0154     return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
0155 }
0156 
0157 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
0158 {
0159     unsigned int mask, val;
0160 
0161     if (imx6_pcie->drvdata->variant == IMX8MQ &&
0162         imx6_pcie->controller_id == 1) {
0163         mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
0164         val  = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
0165                   PCI_EXP_TYPE_ROOT_PORT);
0166     } else {
0167         mask = IMX6Q_GPR12_DEVICE_TYPE;
0168         val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
0169                   PCI_EXP_TYPE_ROOT_PORT);
0170     }
0171 
0172     regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
0173 }
0174 
0175 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
0176 {
0177     struct dw_pcie *pci = imx6_pcie->pci;
0178     bool val;
0179     u32 max_iterations = 10;
0180     u32 wait_counter = 0;
0181 
0182     do {
0183         val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
0184             PCIE_PHY_STAT_ACK;
0185         wait_counter++;
0186 
0187         if (val == exp_val)
0188             return 0;
0189 
0190         udelay(1);
0191     } while (wait_counter < max_iterations);
0192 
0193     return -ETIMEDOUT;
0194 }
0195 
0196 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
0197 {
0198     struct dw_pcie *pci = imx6_pcie->pci;
0199     u32 val;
0200     int ret;
0201 
0202     val = PCIE_PHY_CTRL_DATA(addr);
0203     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
0204 
0205     val |= PCIE_PHY_CTRL_CAP_ADR;
0206     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
0207 
0208     ret = pcie_phy_poll_ack(imx6_pcie, true);
0209     if (ret)
0210         return ret;
0211 
0212     val = PCIE_PHY_CTRL_DATA(addr);
0213     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
0214 
0215     return pcie_phy_poll_ack(imx6_pcie, false);
0216 }
0217 
0218 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
0219 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
0220 {
0221     struct dw_pcie *pci = imx6_pcie->pci;
0222     u32 phy_ctl;
0223     int ret;
0224 
0225     ret = pcie_phy_wait_ack(imx6_pcie, addr);
0226     if (ret)
0227         return ret;
0228 
0229     /* assert Read signal */
0230     phy_ctl = PCIE_PHY_CTRL_RD;
0231     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
0232 
0233     ret = pcie_phy_poll_ack(imx6_pcie, true);
0234     if (ret)
0235         return ret;
0236 
0237     *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
0238 
0239     /* deassert Read signal */
0240     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
0241 
0242     return pcie_phy_poll_ack(imx6_pcie, false);
0243 }
0244 
0245 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
0246 {
0247     struct dw_pcie *pci = imx6_pcie->pci;
0248     u32 var;
0249     int ret;
0250 
0251     /* write addr */
0252     /* cap addr */
0253     ret = pcie_phy_wait_ack(imx6_pcie, addr);
0254     if (ret)
0255         return ret;
0256 
0257     var = PCIE_PHY_CTRL_DATA(data);
0258     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
0259 
0260     /* capture data */
0261     var |= PCIE_PHY_CTRL_CAP_DAT;
0262     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
0263 
0264     ret = pcie_phy_poll_ack(imx6_pcie, true);
0265     if (ret)
0266         return ret;
0267 
0268     /* deassert cap data */
0269     var = PCIE_PHY_CTRL_DATA(data);
0270     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
0271 
0272     /* wait for ack de-assertion */
0273     ret = pcie_phy_poll_ack(imx6_pcie, false);
0274     if (ret)
0275         return ret;
0276 
0277     /* assert wr signal */
0278     var = PCIE_PHY_CTRL_WR;
0279     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
0280 
0281     /* wait for ack */
0282     ret = pcie_phy_poll_ack(imx6_pcie, true);
0283     if (ret)
0284         return ret;
0285 
0286     /* deassert wr signal */
0287     var = PCIE_PHY_CTRL_DATA(data);
0288     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
0289 
0290     /* wait for ack de-assertion */
0291     ret = pcie_phy_poll_ack(imx6_pcie, false);
0292     if (ret)
0293         return ret;
0294 
0295     dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
0296 
0297     return 0;
0298 }
0299 
0300 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
0301 {
0302     switch (imx6_pcie->drvdata->variant) {
0303     case IMX8MM:
0304         /*
0305          * The PHY initialization had been done in the PHY
0306          * driver, break here directly.
0307          */
0308         break;
0309     case IMX8MQ:
0310         /*
0311          * TODO: Currently this code assumes external
0312          * oscillator is being used
0313          */
0314         regmap_update_bits(imx6_pcie->iomuxc_gpr,
0315                    imx6_pcie_grp_offset(imx6_pcie),
0316                    IMX8MQ_GPR_PCIE_REF_USE_PAD,
0317                    IMX8MQ_GPR_PCIE_REF_USE_PAD);
0318         /*
0319          * Regarding the datasheet, the PCIE_VPH is suggested
0320          * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
0321          * VREG_BYPASS should be cleared to zero.
0322          */
0323         if (imx6_pcie->vph &&
0324             regulator_get_voltage(imx6_pcie->vph) > 3000000)
0325             regmap_update_bits(imx6_pcie->iomuxc_gpr,
0326                        imx6_pcie_grp_offset(imx6_pcie),
0327                        IMX8MQ_GPR_PCIE_VREG_BYPASS,
0328                        0);
0329         break;
0330     case IMX7D:
0331         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0332                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
0333         break;
0334     case IMX6SX:
0335         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0336                    IMX6SX_GPR12_PCIE_RX_EQ_MASK,
0337                    IMX6SX_GPR12_PCIE_RX_EQ_2);
0338         fallthrough;
0339     default:
0340         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0341                    IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
0342 
0343         /* configure constant input signal to the pcie ctrl and phy */
0344         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0345                    IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
0346 
0347         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
0348                    IMX6Q_GPR8_TX_DEEMPH_GEN1,
0349                    imx6_pcie->tx_deemph_gen1 << 0);
0350         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
0351                    IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
0352                    imx6_pcie->tx_deemph_gen2_3p5db << 6);
0353         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
0354                    IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
0355                    imx6_pcie->tx_deemph_gen2_6db << 12);
0356         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
0357                    IMX6Q_GPR8_TX_SWING_FULL,
0358                    imx6_pcie->tx_swing_full << 18);
0359         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
0360                    IMX6Q_GPR8_TX_SWING_LOW,
0361                    imx6_pcie->tx_swing_low << 25);
0362         break;
0363     }
0364 
0365     imx6_pcie_configure_type(imx6_pcie);
0366 }
0367 
0368 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
0369 {
0370     u32 val;
0371     struct device *dev = imx6_pcie->pci->dev;
0372 
0373     if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
0374                      IOMUXC_GPR22, val,
0375                      val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
0376                      PHY_PLL_LOCK_WAIT_USLEEP_MAX,
0377                      PHY_PLL_LOCK_WAIT_TIMEOUT))
0378         dev_err(dev, "PCIe PLL lock timeout\n");
0379 }
0380 
0381 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
0382 {
0383     unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
0384     int mult, div;
0385     u16 val;
0386 
0387     if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
0388         return 0;
0389 
0390     switch (phy_rate) {
0391     case 125000000:
0392         /*
0393          * The default settings of the MPLL are for a 125MHz input
0394          * clock, so no need to reconfigure anything in that case.
0395          */
0396         return 0;
0397     case 100000000:
0398         mult = 25;
0399         div = 0;
0400         break;
0401     case 200000000:
0402         mult = 25;
0403         div = 1;
0404         break;
0405     default:
0406         dev_err(imx6_pcie->pci->dev,
0407             "Unsupported PHY reference clock rate %lu\n", phy_rate);
0408         return -EINVAL;
0409     }
0410 
0411     pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
0412     val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
0413          PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
0414     val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
0415     val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
0416     pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
0417 
0418     pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
0419     val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
0420          PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
0421     val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
0422     val |= PCIE_PHY_ATEOVRD_EN;
0423     pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
0424 
0425     return 0;
0426 }
0427 
0428 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
0429 {
0430     u16 tmp;
0431 
0432     if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
0433         return;
0434 
0435     pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
0436     tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
0437         PHY_RX_OVRD_IN_LO_RX_PLL_EN);
0438     pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
0439 
0440     usleep_range(2000, 3000);
0441 
0442     pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
0443     tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
0444           PHY_RX_OVRD_IN_LO_RX_PLL_EN);
0445     pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
0446 }
0447 
0448 #ifdef CONFIG_ARM
0449 /*  Added for PCI abort handling */
0450 static int imx6q_pcie_abort_handler(unsigned long addr,
0451         unsigned int fsr, struct pt_regs *regs)
0452 {
0453     unsigned long pc = instruction_pointer(regs);
0454     unsigned long instr = *(unsigned long *)pc;
0455     int reg = (instr >> 12) & 15;
0456 
0457     /*
0458      * If the instruction being executed was a read,
0459      * make it look like it read all-ones.
0460      */
0461     if ((instr & 0x0c100000) == 0x04100000) {
0462         unsigned long val;
0463 
0464         if (instr & 0x00400000)
0465             val = 255;
0466         else
0467             val = -1;
0468 
0469         regs->uregs[reg] = val;
0470         regs->ARM_pc += 4;
0471         return 0;
0472     }
0473 
0474     if ((instr & 0x0e100090) == 0x00100090) {
0475         regs->uregs[reg] = -1;
0476         regs->ARM_pc += 4;
0477         return 0;
0478     }
0479 
0480     return 1;
0481 }
0482 #endif
0483 
0484 static int imx6_pcie_attach_pd(struct device *dev)
0485 {
0486     struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
0487     struct device_link *link;
0488 
0489     /* Do nothing when in a single power domain */
0490     if (dev->pm_domain)
0491         return 0;
0492 
0493     imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
0494     if (IS_ERR(imx6_pcie->pd_pcie))
0495         return PTR_ERR(imx6_pcie->pd_pcie);
0496     /* Do nothing when power domain missing */
0497     if (!imx6_pcie->pd_pcie)
0498         return 0;
0499     link = device_link_add(dev, imx6_pcie->pd_pcie,
0500             DL_FLAG_STATELESS |
0501             DL_FLAG_PM_RUNTIME |
0502             DL_FLAG_RPM_ACTIVE);
0503     if (!link) {
0504         dev_err(dev, "Failed to add device_link to pcie pd.\n");
0505         return -EINVAL;
0506     }
0507 
0508     imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
0509     if (IS_ERR(imx6_pcie->pd_pcie_phy))
0510         return PTR_ERR(imx6_pcie->pd_pcie_phy);
0511 
0512     link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
0513             DL_FLAG_STATELESS |
0514             DL_FLAG_PM_RUNTIME |
0515             DL_FLAG_RPM_ACTIVE);
0516     if (!link) {
0517         dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
0518         return -EINVAL;
0519     }
0520 
0521     return 0;
0522 }
0523 
0524 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
0525 {
0526     struct dw_pcie *pci = imx6_pcie->pci;
0527     struct device *dev = pci->dev;
0528     unsigned int offset;
0529     int ret = 0;
0530 
0531     switch (imx6_pcie->drvdata->variant) {
0532     case IMX6SX:
0533         ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
0534         if (ret) {
0535             dev_err(dev, "unable to enable pcie_axi clock\n");
0536             break;
0537         }
0538 
0539         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0540                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
0541         break;
0542     case IMX6QP:
0543     case IMX6Q:
0544         /* power up core phy and enable ref clock */
0545         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0546                    IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
0547         /*
0548          * the async reset input need ref clock to sync internally,
0549          * when the ref clock comes after reset, internal synced
0550          * reset time is too short, cannot meet the requirement.
0551          * add one ~10us delay here.
0552          */
0553         usleep_range(10, 100);
0554         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0555                    IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
0556         break;
0557     case IMX7D:
0558         break;
0559     case IMX8MM:
0560     case IMX8MQ:
0561         ret = clk_prepare_enable(imx6_pcie->pcie_aux);
0562         if (ret) {
0563             dev_err(dev, "unable to enable pcie_aux clock\n");
0564             break;
0565         }
0566 
0567         offset = imx6_pcie_grp_offset(imx6_pcie);
0568         /*
0569          * Set the over ride low and enabled
0570          * make sure that REF_CLK is turned on.
0571          */
0572         regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
0573                    IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
0574                    0);
0575         regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
0576                    IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
0577                    IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
0578         break;
0579     }
0580 
0581     return ret;
0582 }
0583 
0584 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
0585 {
0586     switch (imx6_pcie->drvdata->variant) {
0587     case IMX6SX:
0588         clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
0589         break;
0590     case IMX6QP:
0591     case IMX6Q:
0592         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0593                 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
0594         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0595                 IMX6Q_GPR1_PCIE_TEST_PD,
0596                 IMX6Q_GPR1_PCIE_TEST_PD);
0597         break;
0598     case IMX7D:
0599         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0600                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
0601                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
0602         break;
0603     case IMX8MM:
0604     case IMX8MQ:
0605         clk_disable_unprepare(imx6_pcie->pcie_aux);
0606         break;
0607     default:
0608         break;
0609     }
0610 }
0611 
0612 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
0613 {
0614     struct dw_pcie *pci = imx6_pcie->pci;
0615     struct device *dev = pci->dev;
0616     int ret;
0617 
0618     ret = clk_prepare_enable(imx6_pcie->pcie_phy);
0619     if (ret) {
0620         dev_err(dev, "unable to enable pcie_phy clock\n");
0621         return ret;
0622     }
0623 
0624     ret = clk_prepare_enable(imx6_pcie->pcie_bus);
0625     if (ret) {
0626         dev_err(dev, "unable to enable pcie_bus clock\n");
0627         goto err_pcie_bus;
0628     }
0629 
0630     ret = clk_prepare_enable(imx6_pcie->pcie);
0631     if (ret) {
0632         dev_err(dev, "unable to enable pcie clock\n");
0633         goto err_pcie;
0634     }
0635 
0636     ret = imx6_pcie_enable_ref_clk(imx6_pcie);
0637     if (ret) {
0638         dev_err(dev, "unable to enable pcie ref clock\n");
0639         goto err_ref_clk;
0640     }
0641 
0642     /* allow the clocks to stabilize */
0643     usleep_range(200, 500);
0644     return 0;
0645 
0646 err_ref_clk:
0647     clk_disable_unprepare(imx6_pcie->pcie);
0648 err_pcie:
0649     clk_disable_unprepare(imx6_pcie->pcie_bus);
0650 err_pcie_bus:
0651     clk_disable_unprepare(imx6_pcie->pcie_phy);
0652 
0653     return ret;
0654 }
0655 
0656 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
0657 {
0658     imx6_pcie_disable_ref_clk(imx6_pcie);
0659     clk_disable_unprepare(imx6_pcie->pcie);
0660     clk_disable_unprepare(imx6_pcie->pcie_bus);
0661     clk_disable_unprepare(imx6_pcie->pcie_phy);
0662 }
0663 
0664 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
0665 {
0666     switch (imx6_pcie->drvdata->variant) {
0667     case IMX7D:
0668     case IMX8MQ:
0669         reset_control_assert(imx6_pcie->pciephy_reset);
0670         fallthrough;
0671     case IMX8MM:
0672         reset_control_assert(imx6_pcie->apps_reset);
0673         break;
0674     case IMX6SX:
0675         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0676                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
0677                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
0678         /* Force PCIe PHY reset */
0679         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
0680                    IMX6SX_GPR5_PCIE_BTNRST_RESET,
0681                    IMX6SX_GPR5_PCIE_BTNRST_RESET);
0682         break;
0683     case IMX6QP:
0684         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0685                    IMX6Q_GPR1_PCIE_SW_RST,
0686                    IMX6Q_GPR1_PCIE_SW_RST);
0687         break;
0688     case IMX6Q:
0689         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0690                    IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
0691         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0692                    IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
0693         break;
0694     }
0695 
0696     /* Some boards don't have PCIe reset GPIO. */
0697     if (gpio_is_valid(imx6_pcie->reset_gpio))
0698         gpio_set_value_cansleep(imx6_pcie->reset_gpio,
0699                     imx6_pcie->gpio_active_high);
0700 }
0701 
0702 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
0703 {
0704     struct dw_pcie *pci = imx6_pcie->pci;
0705     struct device *dev = pci->dev;
0706 
0707     switch (imx6_pcie->drvdata->variant) {
0708     case IMX8MQ:
0709         reset_control_deassert(imx6_pcie->pciephy_reset);
0710         break;
0711     case IMX7D:
0712         reset_control_deassert(imx6_pcie->pciephy_reset);
0713 
0714         /* Workaround for ERR010728, failure of PCI-e PLL VCO to
0715          * oscillate, especially when cold.  This turns off "Duty-cycle
0716          * Corrector" and other mysterious undocumented things.
0717          */
0718         if (likely(imx6_pcie->phy_base)) {
0719             /* De-assert DCC_FB_EN */
0720             writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
0721                    imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
0722             /* Assert RX_EQS and RX_EQS_SEL */
0723             writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
0724                 | PCIE_PHY_CMN_REG24_RX_EQ,
0725                    imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
0726             /* Assert ATT_MODE */
0727             writel(PCIE_PHY_CMN_REG26_ATT_MODE,
0728                    imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
0729         } else {
0730             dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
0731         }
0732 
0733         imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
0734         break;
0735     case IMX6SX:
0736         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
0737                    IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
0738         break;
0739     case IMX6QP:
0740         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
0741                    IMX6Q_GPR1_PCIE_SW_RST, 0);
0742 
0743         usleep_range(200, 500);
0744         break;
0745     case IMX6Q:     /* Nothing to do */
0746     case IMX8MM:
0747         break;
0748     }
0749 
0750     /* Some boards don't have PCIe reset GPIO. */
0751     if (gpio_is_valid(imx6_pcie->reset_gpio)) {
0752         msleep(100);
0753         gpio_set_value_cansleep(imx6_pcie->reset_gpio,
0754                     !imx6_pcie->gpio_active_high);
0755         /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
0756         msleep(100);
0757     }
0758 
0759     return 0;
0760 }
0761 
0762 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
0763 {
0764     struct dw_pcie *pci = imx6_pcie->pci;
0765     struct device *dev = pci->dev;
0766     u32 tmp;
0767     unsigned int retries;
0768 
0769     for (retries = 0; retries < 200; retries++) {
0770         tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
0771         /* Test if the speed change finished. */
0772         if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
0773             return 0;
0774         usleep_range(100, 1000);
0775     }
0776 
0777     dev_err(dev, "Speed change timeout\n");
0778     return -ETIMEDOUT;
0779 }
0780 
0781 static void imx6_pcie_ltssm_enable(struct device *dev)
0782 {
0783     struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
0784 
0785     switch (imx6_pcie->drvdata->variant) {
0786     case IMX6Q:
0787     case IMX6SX:
0788     case IMX6QP:
0789         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0790                    IMX6Q_GPR12_PCIE_CTL_2,
0791                    IMX6Q_GPR12_PCIE_CTL_2);
0792         break;
0793     case IMX7D:
0794     case IMX8MQ:
0795     case IMX8MM:
0796         reset_control_deassert(imx6_pcie->apps_reset);
0797         break;
0798     }
0799 }
0800 
0801 static void imx6_pcie_ltssm_disable(struct device *dev)
0802 {
0803     struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
0804 
0805     switch (imx6_pcie->drvdata->variant) {
0806     case IMX6Q:
0807     case IMX6SX:
0808     case IMX6QP:
0809         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
0810                    IMX6Q_GPR12_PCIE_CTL_2, 0);
0811         break;
0812     case IMX7D:
0813     case IMX8MQ:
0814     case IMX8MM:
0815         reset_control_assert(imx6_pcie->apps_reset);
0816         break;
0817     }
0818 }
0819 
0820 static int imx6_pcie_start_link(struct dw_pcie *pci)
0821 {
0822     struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
0823     struct device *dev = pci->dev;
0824     u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
0825     u32 tmp;
0826     int ret;
0827 
0828     /*
0829      * Force Gen1 operation when starting the link.  In case the link is
0830      * started in Gen2 mode, there is a possibility the devices on the
0831      * bus will not be detected at all.  This happens with PCIe switches.
0832      */
0833     dw_pcie_dbi_ro_wr_en(pci);
0834     tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
0835     tmp &= ~PCI_EXP_LNKCAP_SLS;
0836     tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
0837     dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
0838     dw_pcie_dbi_ro_wr_dis(pci);
0839 
0840     /* Start LTSSM. */
0841     imx6_pcie_ltssm_enable(dev);
0842 
0843     ret = dw_pcie_wait_for_link(pci);
0844     if (ret)
0845         goto err_reset_phy;
0846 
0847     if (pci->link_gen > 1) {
0848         /* Allow faster modes after the link is up */
0849         dw_pcie_dbi_ro_wr_en(pci);
0850         tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
0851         tmp &= ~PCI_EXP_LNKCAP_SLS;
0852         tmp |= pci->link_gen;
0853         dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
0854 
0855         /*
0856          * Start Directed Speed Change so the best possible
0857          * speed both link partners support can be negotiated.
0858          */
0859         tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
0860         tmp |= PORT_LOGIC_SPEED_CHANGE;
0861         dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
0862         dw_pcie_dbi_ro_wr_dis(pci);
0863 
0864         if (imx6_pcie->drvdata->flags &
0865             IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
0866             /*
0867              * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
0868              * from i.MX6 family when no link speed transition
0869              * occurs and we go Gen1 -> yep, Gen1. The difference
0870              * is that, in such case, it will not be cleared by HW
0871              * which will cause the following code to report false
0872              * failure.
0873              */
0874 
0875             ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
0876             if (ret) {
0877                 dev_err(dev, "Failed to bring link up!\n");
0878                 goto err_reset_phy;
0879             }
0880         }
0881 
0882         /* Make sure link training is finished as well! */
0883         ret = dw_pcie_wait_for_link(pci);
0884         if (ret)
0885             goto err_reset_phy;
0886     } else {
0887         dev_info(dev, "Link: Only Gen1 is enabled\n");
0888     }
0889 
0890     imx6_pcie->link_is_up = true;
0891     tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
0892     dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
0893     return 0;
0894 
0895 err_reset_phy:
0896     imx6_pcie->link_is_up = false;
0897     dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
0898         dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
0899         dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
0900     imx6_pcie_reset_phy(imx6_pcie);
0901     return 0;
0902 }
0903 
0904 static void imx6_pcie_stop_link(struct dw_pcie *pci)
0905 {
0906     struct device *dev = pci->dev;
0907 
0908     /* Turn off PCIe LTSSM */
0909     imx6_pcie_ltssm_disable(dev);
0910 }
0911 
0912 static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
0913 {
0914     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0915     struct device *dev = pci->dev;
0916     struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
0917     int ret;
0918 
0919     if (imx6_pcie->vpcie) {
0920         ret = regulator_enable(imx6_pcie->vpcie);
0921         if (ret) {
0922             dev_err(dev, "failed to enable vpcie regulator: %d\n",
0923                 ret);
0924             return ret;
0925         }
0926     }
0927 
0928     imx6_pcie_assert_core_reset(imx6_pcie);
0929     imx6_pcie_init_phy(imx6_pcie);
0930 
0931     ret = imx6_pcie_clk_enable(imx6_pcie);
0932     if (ret) {
0933         dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
0934         goto err_reg_disable;
0935     }
0936 
0937     if (imx6_pcie->phy) {
0938         ret = phy_power_on(imx6_pcie->phy);
0939         if (ret) {
0940             dev_err(dev, "pcie PHY power up failed\n");
0941             goto err_clk_disable;
0942         }
0943     }
0944 
0945     ret = imx6_pcie_deassert_core_reset(imx6_pcie);
0946     if (ret < 0) {
0947         dev_err(dev, "pcie deassert core reset failed: %d\n", ret);
0948         goto err_phy_off;
0949     }
0950 
0951     if (imx6_pcie->phy) {
0952         ret = phy_init(imx6_pcie->phy);
0953         if (ret) {
0954             dev_err(dev, "waiting for PHY ready timeout!\n");
0955             goto err_phy_off;
0956         }
0957     }
0958     imx6_setup_phy_mpll(imx6_pcie);
0959 
0960     return 0;
0961 
0962 err_phy_off:
0963     if (imx6_pcie->phy)
0964         phy_power_off(imx6_pcie->phy);
0965 err_clk_disable:
0966     imx6_pcie_clk_disable(imx6_pcie);
0967 err_reg_disable:
0968     if (imx6_pcie->vpcie)
0969         regulator_disable(imx6_pcie->vpcie);
0970     return ret;
0971 }
0972 
0973 static void imx6_pcie_host_exit(struct dw_pcie_rp *pp)
0974 {
0975     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0976     struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
0977 
0978     if (imx6_pcie->phy) {
0979         if (phy_power_off(imx6_pcie->phy))
0980             dev_err(pci->dev, "unable to power off PHY\n");
0981         phy_exit(imx6_pcie->phy);
0982     }
0983     imx6_pcie_clk_disable(imx6_pcie);
0984 
0985     if (imx6_pcie->vpcie)
0986         regulator_disable(imx6_pcie->vpcie);
0987 }
0988 
0989 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
0990     .host_init = imx6_pcie_host_init,
0991 };
0992 
0993 static const struct dw_pcie_ops dw_pcie_ops = {
0994     .start_link = imx6_pcie_start_link,
0995 };
0996 
0997 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
0998 {
0999     struct device *dev = imx6_pcie->pci->dev;
1000 
1001     /* Some variants have a turnoff reset in DT */
1002     if (imx6_pcie->turnoff_reset) {
1003         reset_control_assert(imx6_pcie->turnoff_reset);
1004         reset_control_deassert(imx6_pcie->turnoff_reset);
1005         goto pm_turnoff_sleep;
1006     }
1007 
1008     /* Others poke directly at IOMUXC registers */
1009     switch (imx6_pcie->drvdata->variant) {
1010     case IMX6SX:
1011     case IMX6QP:
1012         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
1013                 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
1014                 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
1015         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
1016                 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
1017         break;
1018     default:
1019         dev_err(dev, "PME_Turn_Off not implemented\n");
1020         return;
1021     }
1022 
1023     /*
1024      * Components with an upstream port must respond to
1025      * PME_Turn_Off with PME_TO_Ack but we can't check.
1026      *
1027      * The standard recommends a 1-10ms timeout after which to
1028      * proceed anyway as if acks were received.
1029      */
1030 pm_turnoff_sleep:
1031     usleep_range(1000, 10000);
1032 }
1033 
1034 static int imx6_pcie_suspend_noirq(struct device *dev)
1035 {
1036     struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
1037     struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
1038 
1039     if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
1040         return 0;
1041 
1042     imx6_pcie_pm_turnoff(imx6_pcie);
1043     imx6_pcie_stop_link(imx6_pcie->pci);
1044     imx6_pcie_host_exit(pp);
1045 
1046     return 0;
1047 }
1048 
1049 static int imx6_pcie_resume_noirq(struct device *dev)
1050 {
1051     int ret;
1052     struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
1053     struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
1054 
1055     if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
1056         return 0;
1057 
1058     ret = imx6_pcie_host_init(pp);
1059     if (ret)
1060         return ret;
1061     dw_pcie_setup_rc(pp);
1062 
1063     if (imx6_pcie->link_is_up)
1064         imx6_pcie_start_link(imx6_pcie->pci);
1065 
1066     return 0;
1067 }
1068 
1069 static const struct dev_pm_ops imx6_pcie_pm_ops = {
1070     NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
1071                   imx6_pcie_resume_noirq)
1072 };
1073 
1074 static int imx6_pcie_probe(struct platform_device *pdev)
1075 {
1076     struct device *dev = &pdev->dev;
1077     struct dw_pcie *pci;
1078     struct imx6_pcie *imx6_pcie;
1079     struct device_node *np;
1080     struct resource *dbi_base;
1081     struct device_node *node = dev->of_node;
1082     int ret;
1083     u16 val;
1084 
1085     imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
1086     if (!imx6_pcie)
1087         return -ENOMEM;
1088 
1089     pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1090     if (!pci)
1091         return -ENOMEM;
1092 
1093     pci->dev = dev;
1094     pci->ops = &dw_pcie_ops;
1095     pci->pp.ops = &imx6_pcie_host_ops;
1096 
1097     imx6_pcie->pci = pci;
1098     imx6_pcie->drvdata = of_device_get_match_data(dev);
1099 
1100     /* Find the PHY if one is defined, only imx7d uses it */
1101     np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1102     if (np) {
1103         struct resource res;
1104 
1105         ret = of_address_to_resource(np, 0, &res);
1106         if (ret) {
1107             dev_err(dev, "Unable to map PCIe PHY\n");
1108             return ret;
1109         }
1110         imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1111         if (IS_ERR(imx6_pcie->phy_base))
1112             return PTR_ERR(imx6_pcie->phy_base);
1113     }
1114 
1115     dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1116     pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1117     if (IS_ERR(pci->dbi_base))
1118         return PTR_ERR(pci->dbi_base);
1119 
1120     /* Fetch GPIOs */
1121     imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1122     imx6_pcie->gpio_active_high = of_property_read_bool(node,
1123                         "reset-gpio-active-high");
1124     if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1125         ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1126                 imx6_pcie->gpio_active_high ?
1127                     GPIOF_OUT_INIT_HIGH :
1128                     GPIOF_OUT_INIT_LOW,
1129                 "PCIe reset");
1130         if (ret) {
1131             dev_err(dev, "unable to get reset gpio\n");
1132             return ret;
1133         }
1134     } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1135         return imx6_pcie->reset_gpio;
1136     }
1137 
1138     /* Fetch clocks */
1139     imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1140     if (IS_ERR(imx6_pcie->pcie_bus))
1141         return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1142                      "pcie_bus clock source missing or invalid\n");
1143 
1144     imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1145     if (IS_ERR(imx6_pcie->pcie))
1146         return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1147                      "pcie clock source missing or invalid\n");
1148 
1149     switch (imx6_pcie->drvdata->variant) {
1150     case IMX6SX:
1151         imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1152                                "pcie_inbound_axi");
1153         if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1154             return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1155                          "pcie_inbound_axi clock missing or invalid\n");
1156         break;
1157     case IMX8MQ:
1158         imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1159         if (IS_ERR(imx6_pcie->pcie_aux))
1160             return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1161                          "pcie_aux clock source missing or invalid\n");
1162         fallthrough;
1163     case IMX7D:
1164         if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1165             imx6_pcie->controller_id = 1;
1166 
1167         imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1168                                         "pciephy");
1169         if (IS_ERR(imx6_pcie->pciephy_reset)) {
1170             dev_err(dev, "Failed to get PCIEPHY reset control\n");
1171             return PTR_ERR(imx6_pcie->pciephy_reset);
1172         }
1173 
1174         imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1175                                      "apps");
1176         if (IS_ERR(imx6_pcie->apps_reset)) {
1177             dev_err(dev, "Failed to get PCIE APPS reset control\n");
1178             return PTR_ERR(imx6_pcie->apps_reset);
1179         }
1180         break;
1181     case IMX8MM:
1182         imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1183         if (IS_ERR(imx6_pcie->pcie_aux))
1184             return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1185                          "pcie_aux clock source missing or invalid\n");
1186         imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1187                                      "apps");
1188         if (IS_ERR(imx6_pcie->apps_reset))
1189             return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
1190                          "failed to get pcie apps reset control\n");
1191 
1192         imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
1193         if (IS_ERR(imx6_pcie->phy))
1194             return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
1195                          "failed to get pcie phy\n");
1196 
1197         break;
1198     default:
1199         break;
1200     }
1201     /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */
1202     if (imx6_pcie->phy == NULL) {
1203         imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1204         if (IS_ERR(imx6_pcie->pcie_phy))
1205             return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1206                          "pcie_phy clock source missing or invalid\n");
1207     }
1208 
1209 
1210     /* Grab turnoff reset */
1211     imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1212     if (IS_ERR(imx6_pcie->turnoff_reset)) {
1213         dev_err(dev, "Failed to get TURNOFF reset control\n");
1214         return PTR_ERR(imx6_pcie->turnoff_reset);
1215     }
1216 
1217     /* Grab GPR config register range */
1218     imx6_pcie->iomuxc_gpr =
1219          syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1220     if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1221         dev_err(dev, "unable to find iomuxc registers\n");
1222         return PTR_ERR(imx6_pcie->iomuxc_gpr);
1223     }
1224 
1225     /* Grab PCIe PHY Tx Settings */
1226     if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1227                  &imx6_pcie->tx_deemph_gen1))
1228         imx6_pcie->tx_deemph_gen1 = 0;
1229 
1230     if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1231                  &imx6_pcie->tx_deemph_gen2_3p5db))
1232         imx6_pcie->tx_deemph_gen2_3p5db = 0;
1233 
1234     if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1235                  &imx6_pcie->tx_deemph_gen2_6db))
1236         imx6_pcie->tx_deemph_gen2_6db = 20;
1237 
1238     if (of_property_read_u32(node, "fsl,tx-swing-full",
1239                  &imx6_pcie->tx_swing_full))
1240         imx6_pcie->tx_swing_full = 127;
1241 
1242     if (of_property_read_u32(node, "fsl,tx-swing-low",
1243                  &imx6_pcie->tx_swing_low))
1244         imx6_pcie->tx_swing_low = 127;
1245 
1246     /* Limit link speed */
1247     pci->link_gen = 1;
1248     of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
1249 
1250     imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1251     if (IS_ERR(imx6_pcie->vpcie)) {
1252         if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1253             return PTR_ERR(imx6_pcie->vpcie);
1254         imx6_pcie->vpcie = NULL;
1255     }
1256 
1257     imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
1258     if (IS_ERR(imx6_pcie->vph)) {
1259         if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
1260             return PTR_ERR(imx6_pcie->vph);
1261         imx6_pcie->vph = NULL;
1262     }
1263 
1264     platform_set_drvdata(pdev, imx6_pcie);
1265 
1266     ret = imx6_pcie_attach_pd(dev);
1267     if (ret)
1268         return ret;
1269 
1270     ret = dw_pcie_host_init(&pci->pp);
1271     if (ret < 0)
1272         return ret;
1273 
1274     if (pci_msi_enabled()) {
1275         u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1276         val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1277         val |= PCI_MSI_FLAGS_ENABLE;
1278         dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1279     }
1280 
1281     return 0;
1282 }
1283 
1284 static void imx6_pcie_shutdown(struct platform_device *pdev)
1285 {
1286     struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1287 
1288     /* bring down link, so bootloader gets clean state in case of reboot */
1289     imx6_pcie_assert_core_reset(imx6_pcie);
1290 }
1291 
1292 static const struct imx6_pcie_drvdata drvdata[] = {
1293     [IMX6Q] = {
1294         .variant = IMX6Q,
1295         .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1296              IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1297         .dbi_length = 0x200,
1298     },
1299     [IMX6SX] = {
1300         .variant = IMX6SX,
1301         .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1302              IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1303              IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1304     },
1305     [IMX6QP] = {
1306         .variant = IMX6QP,
1307         .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1308              IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1309              IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1310         .dbi_length = 0x200,
1311     },
1312     [IMX7D] = {
1313         .variant = IMX7D,
1314         .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1315     },
1316     [IMX8MQ] = {
1317         .variant = IMX8MQ,
1318     },
1319     [IMX8MM] = {
1320         .variant = IMX8MM,
1321         .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1322     },
1323 };
1324 
1325 static const struct of_device_id imx6_pcie_of_match[] = {
1326     { .compatible = "fsl,imx6q-pcie",  .data = &drvdata[IMX6Q],  },
1327     { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1328     { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1329     { .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
1330     { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1331     { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1332     {},
1333 };
1334 
1335 static struct platform_driver imx6_pcie_driver = {
1336     .driver = {
1337         .name   = "imx6q-pcie",
1338         .of_match_table = imx6_pcie_of_match,
1339         .suppress_bind_attrs = true,
1340         .pm = &imx6_pcie_pm_ops,
1341         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1342     },
1343     .probe    = imx6_pcie_probe,
1344     .shutdown = imx6_pcie_shutdown,
1345 };
1346 
1347 static void imx6_pcie_quirk(struct pci_dev *dev)
1348 {
1349     struct pci_bus *bus = dev->bus;
1350     struct dw_pcie_rp *pp = bus->sysdata;
1351 
1352     /* Bus parent is the PCI bridge, its parent is this platform driver */
1353     if (!bus->dev.parent || !bus->dev.parent->parent)
1354         return;
1355 
1356     /* Make sure we only quirk devices associated with this driver */
1357     if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
1358         return;
1359 
1360     if (pci_is_root_bus(bus)) {
1361         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1362         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1363 
1364         /*
1365          * Limit config length to avoid the kernel reading beyond
1366          * the register set and causing an abort on i.MX 6Quad
1367          */
1368         if (imx6_pcie->drvdata->dbi_length) {
1369             dev->cfg_size = imx6_pcie->drvdata->dbi_length;
1370             dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1371                     dev->cfg_size);
1372         }
1373     }
1374 }
1375 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1376             PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
1377 
1378 static int __init imx6_pcie_init(void)
1379 {
1380 #ifdef CONFIG_ARM
1381     /*
1382      * Since probe() can be deferred we need to make sure that
1383      * hook_fault_code is not called after __init memory is freed
1384      * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1385      * we can install the handler here without risking it
1386      * accessing some uninitialized driver state.
1387      */
1388     hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1389             "external abort on non-linefetch");
1390 #endif
1391 
1392     return platform_driver_register(&imx6_pcie_driver);
1393 }
1394 device_initcall(imx6_pcie_init);
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