controller/dwc/pci-dra7xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
0004  *
0005  * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
0006  *
0007  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/err.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/of_pci.h>
0022 #include <linux/pci.h>
0023 #include <linux/phy/phy.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/pm_runtime.h>
0026 #include <linux/resource.h>
0027 #include <linux/types.h>
0028 #include <linux/mfd/syscon.h>
0029 #include <linux/regmap.h>
0030 #include <linux/gpio/consumer.h>
0031
0032 #include "../../pci.h"
0033 #include "pcie-designware.h"
0034
0035 /* PCIe controller wrapper DRA7XX configuration registers */
0036
0037 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN     0x0024
0038 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN     0x0028
0039 #define ERR_SYS                     BIT(0)
0040 #define ERR_FATAL                   BIT(1)
0041 #define ERR_NONFATAL                    BIT(2)
0042 #define ERR_COR                     BIT(3)
0043 #define ERR_AXI                     BIT(4)
0044 #define ERR_ECRC                    BIT(5)
0045 #define PME_TURN_OFF                    BIT(8)
0046 #define PME_TO_ACK                  BIT(9)
0047 #define PM_PME                      BIT(10)
0048 #define LINK_REQ_RST                    BIT(11)
0049 #define LINK_UP_EVT                 BIT(12)
0050 #define CFG_BME_EVT                 BIT(13)
0051 #define CFG_MSE_EVT                 BIT(14)
0052 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
0053             ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
0054             LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
0055
0056 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI      0x0034
0057 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI      0x0038
0058 #define INTA                        BIT(0)
0059 #define INTB                        BIT(1)
0060 #define INTC                        BIT(2)
0061 #define INTD                        BIT(3)
0062 #define MSI                     BIT(4)
0063 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
0064
0065 #define PCIECTRL_TI_CONF_DEVICE_TYPE            0x0100
0066 #define DEVICE_TYPE_EP                  0x0
0067 #define DEVICE_TYPE_LEG_EP              0x1
0068 #define DEVICE_TYPE_RC                  0x4
0069
0070 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD         0x0104
0071 #define LTSSM_EN                    0x1
0072
0073 #define PCIECTRL_DRA7XX_CONF_PHY_CS         0x010C
0074 #define LINK_UP                     BIT(16)
0075 #define DRA7XX_CPU_TO_BUS_ADDR              0x0FFFFFFF
0076
0077 #define PCIECTRL_TI_CONF_INTX_ASSERT            0x0124
0078 #define PCIECTRL_TI_CONF_INTX_DEASSERT          0x0128
0079
0080 #define PCIECTRL_TI_CONF_MSI_XMT            0x012c
0081 #define MSI_REQ_GRANT                   BIT(0)
0082 #define MSI_VECTOR_SHIFT                7
0083
0084 #define PCIE_1LANE_2LANE_SELECTION          BIT(13)
0085 #define PCIE_B1C0_MODE_SEL              BIT(2)
0086 #define PCIE_B0_B1_TSYNCEN              BIT(0)
0087
0088 struct dra7xx_pcie {
0089     struct dw_pcie      *pci;
0090     void __iomem        *base;      /* DT ti_conf */
0091     int         phy_count;  /* DT phy-names count */
0092     struct phy      **phy;
0093     struct irq_domain   *irq_domain;
0094     struct clk              *clk;
0095     enum dw_pcie_device_mode mode;
0096 };
0097
0098 struct dra7xx_pcie_of_data {
0099     enum dw_pcie_device_mode mode;
0100     u32 b1co_mode_sel_mask;
0101 };
0102
0103 #define to_dra7xx_pcie(x)   dev_get_drvdata((x)->dev)
0104
0105 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
0106 {
0107     return readl(pcie->base + offset);
0108 }
0109
0110 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
0111                       u32 value)
0112 {
0113     writel(value, pcie->base + offset);
0114 }
0115
0116 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
0117 {
0118     return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
0119 }
0120
0121 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
0122 {
0123     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0124     u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
0125
0126     return !!(reg & LINK_UP);
0127 }
0128
0129 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
0130 {
0131     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0132     u32 reg;
0133
0134     reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
0135     reg &= ~LTSSM_EN;
0136     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
0137 }
0138
0139 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
0140 {
0141     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0142     struct device *dev = pci->dev;
0143     u32 reg;
0144
0145     if (dw_pcie_link_up(pci)) {
0146         dev_err(dev, "link is already up\n");
0147         return 0;
0148     }
0149
0150     reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
0151     reg |= LTSSM_EN;
0152     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
0153
0154     return 0;
0155 }
0156
0157 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
0158 {
0159     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
0160                LEG_EP_INTERRUPTS | MSI);
0161
0162     dra7xx_pcie_writel(dra7xx,
0163                PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
0164                MSI | LEG_EP_INTERRUPTS);
0165 }
0166
0167 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
0168 {
0169     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
0170                INTERRUPTS);
0171     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
0172                INTERRUPTS);
0173 }
0174
0175 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
0176 {
0177     dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
0178     dra7xx_pcie_enable_msi_interrupts(dra7xx);
0179 }
0180
0181 static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
0182 {
0183     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0184     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0185
0186     dra7xx_pcie_enable_interrupts(dra7xx);
0187
0188     return 0;
0189 }
0190
0191 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
0192                 irq_hw_number_t hwirq)
0193 {
0194     irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
0195     irq_set_chip_data(irq, domain->host_data);
0196
0197     return 0;
0198 }
0199
0200 static const struct irq_domain_ops intx_domain_ops = {
0201     .map = dra7xx_pcie_intx_map,
0202     .xlate = pci_irqd_intx_xlate,
0203 };
0204
0205 static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
0206 {
0207     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0208     unsigned long val;
0209     int pos;
0210
0211     val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
0212                    (index * MSI_REG_CTRL_BLOCK_SIZE));
0213     if (!val)
0214         return 0;
0215
0216     pos = find_first_bit(&val, MAX_MSI_IRQS_PER_CTRL);
0217     while (pos != MAX_MSI_IRQS_PER_CTRL) {
0218         generic_handle_domain_irq(pp->irq_domain,
0219                       (index * MAX_MSI_IRQS_PER_CTRL) + pos);
0220         pos++;
0221         pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
0222     }
0223
0224     return 1;
0225 }
0226
0227 static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
0228 {
0229     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0230     int ret, i, count, num_ctrls;
0231
0232     num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
0233
0234     /**
0235      * Need to make sure all MSI status bits read 0 before exiting.
0236      * Else, new MSI IRQs are not registered by the wrapper. Have an
0237      * upperbound for the loop and exit the IRQ in case of IRQ flood
0238      * to avoid locking up system in interrupt context.
0239      */
0240     count = 0;
0241     do {
0242         ret = 0;
0243
0244         for (i = 0; i < num_ctrls; i++)
0245             ret |= dra7xx_pcie_handle_msi(pp, i);
0246         count++;
0247     } while (ret && count <= 1000);
0248
0249     if (count > 1000)
0250         dev_warn_ratelimited(pci->dev,
0251                      "Too many MSI IRQs to handle\n");
0252 }
0253
0254 static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
0255 {
0256     struct irq_chip *chip = irq_desc_get_chip(desc);
0257     struct dra7xx_pcie *dra7xx;
0258     struct dw_pcie_rp *pp;
0259     struct dw_pcie *pci;
0260     unsigned long reg;
0261     u32 bit;
0262
0263     chained_irq_enter(chip, desc);
0264
0265     pp = irq_desc_get_handler_data(desc);
0266     pci = to_dw_pcie_from_pp(pp);
0267     dra7xx = to_dra7xx_pcie(pci);
0268
0269     reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
0270     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
0271
0272     switch (reg) {
0273     case MSI:
0274         dra7xx_pcie_handle_msi_irq(pp);
0275         break;
0276     case INTA:
0277     case INTB:
0278     case INTC:
0279     case INTD:
0280         for_each_set_bit(bit, &reg, PCI_NUM_INTX)
0281             generic_handle_domain_irq(dra7xx->irq_domain, bit);
0282         break;
0283     }
0284
0285     chained_irq_exit(chip, desc);
0286 }
0287
0288 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
0289 {
0290     struct dra7xx_pcie *dra7xx = arg;
0291     struct dw_pcie *pci = dra7xx->pci;
0292     struct device *dev = pci->dev;
0293     struct dw_pcie_ep *ep = &pci->ep;
0294     u32 reg;
0295
0296     reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
0297
0298     if (reg & ERR_SYS)
0299         dev_dbg(dev, "System Error\n");
0300
0301     if (reg & ERR_FATAL)
0302         dev_dbg(dev, "Fatal Error\n");
0303
0304     if (reg & ERR_NONFATAL)
0305         dev_dbg(dev, "Non Fatal Error\n");
0306
0307     if (reg & ERR_COR)
0308         dev_dbg(dev, "Correctable Error\n");
0309
0310     if (reg & ERR_AXI)
0311         dev_dbg(dev, "AXI tag lookup fatal Error\n");
0312
0313     if (reg & ERR_ECRC)
0314         dev_dbg(dev, "ECRC Error\n");
0315
0316     if (reg & PME_TURN_OFF)
0317         dev_dbg(dev,
0318             "Power Management Event Turn-Off message received\n");
0319
0320     if (reg & PME_TO_ACK)
0321         dev_dbg(dev,
0322             "Power Management Turn-Off Ack message received\n");
0323
0324     if (reg & PM_PME)
0325         dev_dbg(dev, "PM Power Management Event message received\n");
0326
0327     if (reg & LINK_REQ_RST)
0328         dev_dbg(dev, "Link Request Reset\n");
0329
0330     if (reg & LINK_UP_EVT) {
0331         if (dra7xx->mode == DW_PCIE_EP_TYPE)
0332             dw_pcie_ep_linkup(ep);
0333         dev_dbg(dev, "Link-up state change\n");
0334     }
0335
0336     if (reg & CFG_BME_EVT)
0337         dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
0338
0339     if (reg & CFG_MSE_EVT)
0340         dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
0341
0342     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
0343
0344     return IRQ_HANDLED;
0345 }
0346
0347 static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
0348 {
0349     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
0350     struct device *dev = pci->dev;
0351     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0352     struct device_node *node = dev->of_node;
0353     struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
0354
0355     if (!pcie_intc_node) {
0356         dev_err(dev, "No PCIe Intc node found\n");
0357         return -ENODEV;
0358     }
0359
0360     irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
0361                      pp);
0362     dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
0363                            &intx_domain_ops, pp);
0364     of_node_put(pcie_intc_node);
0365     if (!dra7xx->irq_domain) {
0366         dev_err(dev, "Failed to get a INTx IRQ domain\n");
0367         return -ENODEV;
0368     }
0369
0370     return 0;
0371 }
0372
0373 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
0374     .host_init = dra7xx_pcie_host_init,
0375 };
0376
0377 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
0378 {
0379     struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
0380     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0381     enum pci_barno bar;
0382
0383     for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
0384         dw_pcie_ep_reset_bar(pci, bar);
0385
0386     dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
0387 }
0388
0389 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
0390 {
0391     dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
0392     mdelay(1);
0393     dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
0394 }
0395
0396 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
0397                       u8 interrupt_num)
0398 {
0399     u32 reg;
0400
0401     reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
0402     reg |= MSI_REQ_GRANT;
0403     dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
0404 }
0405
0406 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
0407                  enum pci_epc_irq_type type, u16 interrupt_num)
0408 {
0409     struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
0410     struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
0411
0412     switch (type) {
0413     case PCI_EPC_IRQ_LEGACY:
0414         dra7xx_pcie_raise_legacy_irq(dra7xx);
0415         break;
0416     case PCI_EPC_IRQ_MSI:
0417         dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
0418         break;
0419     default:
0420         dev_err(pci->dev, "UNKNOWN IRQ type\n");
0421     }
0422
0423     return 0;
0424 }
0425
0426 static const struct pci_epc_features dra7xx_pcie_epc_features = {
0427     .linkup_notifier = true,
0428     .msi_capable = true,
0429     .msix_capable = false,
0430 };
0431
0432 static const struct pci_epc_features*
0433 dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
0434 {
0435     return &dra7xx_pcie_epc_features;
0436 }
0437
0438 static const struct dw_pcie_ep_ops pcie_ep_ops = {
0439     .ep_init = dra7xx_pcie_ep_init,
0440     .raise_irq = dra7xx_pcie_raise_irq,
0441     .get_features = dra7xx_pcie_get_features,
0442 };
0443
0444 static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
0445                   struct platform_device *pdev)
0446 {
0447     int ret;
0448     struct dw_pcie_ep *ep;
0449     struct device *dev = &pdev->dev;
0450     struct dw_pcie *pci = dra7xx->pci;
0451
0452     ep = &pci->ep;
0453     ep->ops = &pcie_ep_ops;
0454
0455     pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
0456     if (IS_ERR(pci->dbi_base))
0457         return PTR_ERR(pci->dbi_base);
0458
0459     pci->dbi_base2 =
0460         devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
0461     if (IS_ERR(pci->dbi_base2))
0462         return PTR_ERR(pci->dbi_base2);
0463
0464     ret = dw_pcie_ep_init(ep);
0465     if (ret) {
0466         dev_err(dev, "failed to initialize endpoint\n");
0467         return ret;
0468     }
0469
0470     return 0;
0471 }
0472
0473 static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
0474                 struct platform_device *pdev)
0475 {
0476     int ret;
0477     struct dw_pcie *pci = dra7xx->pci;
0478     struct dw_pcie_rp *pp = &pci->pp;
0479     struct device *dev = pci->dev;
0480
0481     pp->irq = platform_get_irq(pdev, 1);
0482     if (pp->irq < 0)
0483         return pp->irq;
0484
0485     /* MSI IRQ is muxed */
0486     pp->msi_irq[0] = -ENODEV;
0487
0488     ret = dra7xx_pcie_init_irq_domain(pp);
0489     if (ret < 0)
0490         return ret;
0491
0492     pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
0493     if (IS_ERR(pci->dbi_base))
0494         return PTR_ERR(pci->dbi_base);
0495
0496     pp->ops = &dra7xx_pcie_host_ops;
0497
0498     ret = dw_pcie_host_init(pp);
0499     if (ret) {
0500         dev_err(dev, "failed to initialize host\n");
0501         return ret;
0502     }
0503
0504     return 0;
0505 }
0506
0507 static const struct dw_pcie_ops dw_pcie_ops = {
0508     .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
0509     .start_link = dra7xx_pcie_establish_link,
0510     .stop_link = dra7xx_pcie_stop_link,
0511     .link_up = dra7xx_pcie_link_up,
0512 };
0513
0514 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
0515 {
0516     int phy_count = dra7xx->phy_count;
0517
0518     while (phy_count--) {
0519         phy_power_off(dra7xx->phy[phy_count]);
0520         phy_exit(dra7xx->phy[phy_count]);
0521     }
0522 }
0523
0524 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
0525 {
0526     int phy_count = dra7xx->phy_count;
0527     int ret;
0528     int i;
0529
0530     for (i = 0; i < phy_count; i++) {
0531         ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
0532         if (ret < 0)
0533             goto err_phy;
0534
0535         ret = phy_init(dra7xx->phy[i]);
0536         if (ret < 0)
0537             goto err_phy;
0538
0539         ret = phy_power_on(dra7xx->phy[i]);
0540         if (ret < 0) {
0541             phy_exit(dra7xx->phy[i]);
0542             goto err_phy;
0543         }
0544     }
0545
0546     return 0;
0547
0548 err_phy:
0549     while (--i >= 0) {
0550         phy_power_off(dra7xx->phy[i]);
0551         phy_exit(dra7xx->phy[i]);
0552     }
0553
0554     return ret;
0555 }
0556
0557 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
0558     .mode = DW_PCIE_RC_TYPE,
0559 };
0560
0561 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
0562     .mode = DW_PCIE_EP_TYPE,
0563 };
0564
0565 static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
0566     .b1co_mode_sel_mask = BIT(2),
0567     .mode = DW_PCIE_RC_TYPE,
0568 };
0569
0570 static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
0571     .b1co_mode_sel_mask = GENMASK(3, 2),
0572     .mode = DW_PCIE_RC_TYPE,
0573 };
0574
0575 static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
0576     .b1co_mode_sel_mask = BIT(2),
0577     .mode = DW_PCIE_EP_TYPE,
0578 };
0579
0580 static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
0581     .b1co_mode_sel_mask = GENMASK(3, 2),
0582     .mode = DW_PCIE_EP_TYPE,
0583 };
0584
0585 static const struct of_device_id of_dra7xx_pcie_match[] = {
0586     {
0587         .compatible = "ti,dra7-pcie",
0588         .data = &dra7xx_pcie_rc_of_data,
0589     },
0590     {
0591         .compatible = "ti,dra7-pcie-ep",
0592         .data = &dra7xx_pcie_ep_of_data,
0593     },
0594     {
0595         .compatible = "ti,dra746-pcie-rc",
0596         .data = &dra746_pcie_rc_of_data,
0597     },
0598     {
0599         .compatible = "ti,dra726-pcie-rc",
0600         .data = &dra726_pcie_rc_of_data,
0601     },
0602     {
0603         .compatible = "ti,dra746-pcie-ep",
0604         .data = &dra746_pcie_ep_of_data,
0605     },
0606     {
0607         .compatible = "ti,dra726-pcie-ep",
0608         .data = &dra726_pcie_ep_of_data,
0609     },
0610     {},
0611 };
0612 MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match);
0613
0614 /*
0615  * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
0616  * @dra7xx: the dra7xx device where the workaround should be applied
0617  *
0618  * Access to the PCIe slave port that are not 32-bit aligned will result
0619  * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
0620  * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
0621  * 0x3.
0622  *
0623  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
0624  */
0625 static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
0626 {
0627     int ret;
0628     struct device_node *np = dev->of_node;
0629     struct of_phandle_args args;
0630     struct regmap *regmap;
0631
0632     regmap = syscon_regmap_lookup_by_phandle(np,
0633                          "ti,syscon-unaligned-access");
0634     if (IS_ERR(regmap)) {
0635         dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
0636         return -EINVAL;
0637     }
0638
0639     ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
0640                            2, 0, &args);
0641     if (ret) {
0642         dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
0643         return ret;
0644     }
0645
0646     ret = regmap_update_bits(regmap, args.args[0], args.args[1],
0647                  args.args[1]);
0648     if (ret)
0649         dev_err(dev, "failed to enable unaligned access\n");
0650
0651     of_node_put(args.np);
0652
0653     return ret;
0654 }
0655
0656 static int dra7xx_pcie_configure_two_lane(struct device *dev,
0657                       u32 b1co_mode_sel_mask)
0658 {
0659     struct device_node *np = dev->of_node;
0660     struct regmap *pcie_syscon;
0661     unsigned int pcie_reg;
0662     u32 mask;
0663     u32 val;
0664
0665     pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
0666     if (IS_ERR(pcie_syscon)) {
0667         dev_err(dev, "unable to get ti,syscon-lane-sel\n");
0668         return -EINVAL;
0669     }
0670
0671     if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
0672                        &pcie_reg)) {
0673         dev_err(dev, "couldn't get lane selection reg offset\n");
0674         return -EINVAL;
0675     }
0676
0677     mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
0678     val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
0679     regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
0680
0681     return 0;
0682 }
0683
0684 static int dra7xx_pcie_probe(struct platform_device *pdev)
0685 {
0686     u32 reg;
0687     int ret;
0688     int irq;
0689     int i;
0690     int phy_count;
0691     struct phy **phy;
0692     struct device_link **link;
0693     void __iomem *base;
0694     struct dw_pcie *pci;
0695     struct dra7xx_pcie *dra7xx;
0696     struct device *dev = &pdev->dev;
0697     struct device_node *np = dev->of_node;
0698     char name[10];
0699     struct gpio_desc *reset;
0700     const struct dra7xx_pcie_of_data *data;
0701     enum dw_pcie_device_mode mode;
0702     u32 b1co_mode_sel_mask;
0703
0704     data = of_device_get_match_data(dev);
0705     if (!data)
0706         return -EINVAL;
0707
0708     mode = (enum dw_pcie_device_mode)data->mode;
0709     b1co_mode_sel_mask = data->b1co_mode_sel_mask;
0710
0711     dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
0712     if (!dra7xx)
0713         return -ENOMEM;
0714
0715     pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
0716     if (!pci)
0717         return -ENOMEM;
0718
0719     pci->dev = dev;
0720     pci->ops = &dw_pcie_ops;
0721
0722     irq = platform_get_irq(pdev, 0);
0723     if (irq < 0)
0724         return irq;
0725
0726     base = devm_platform_ioremap_resource_byname(pdev, "ti_conf");
0727     if (IS_ERR(base))
0728         return PTR_ERR(base);
0729
0730     phy_count = of_property_count_strings(np, "phy-names");
0731     if (phy_count < 0) {
0732         dev_err(dev, "unable to find the strings\n");
0733         return phy_count;
0734     }
0735
0736     phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
0737     if (!phy)
0738         return -ENOMEM;
0739
0740     link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
0741     if (!link)
0742         return -ENOMEM;
0743
0744     dra7xx->clk = devm_clk_get_optional(dev, NULL);
0745     if (IS_ERR(dra7xx->clk))
0746         return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
0747                      "clock request failed");
0748
0749     ret = clk_prepare_enable(dra7xx->clk);
0750     if (ret)
0751         return ret;
0752
0753     for (i = 0; i < phy_count; i++) {
0754         snprintf(name, sizeof(name), "pcie-phy%d", i);
0755         phy[i] = devm_phy_get(dev, name);
0756         if (IS_ERR(phy[i]))
0757             return PTR_ERR(phy[i]);
0758
0759         link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
0760         if (!link[i]) {
0761             ret = -EINVAL;
0762             goto err_link;
0763         }
0764     }
0765
0766     dra7xx->base = base;
0767     dra7xx->phy = phy;
0768     dra7xx->pci = pci;
0769     dra7xx->phy_count = phy_count;
0770
0771     if (phy_count == 2) {
0772         ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
0773         if (ret < 0)
0774             dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
0775     }
0776
0777     ret = dra7xx_pcie_enable_phy(dra7xx);
0778     if (ret) {
0779         dev_err(dev, "failed to enable phy\n");
0780         return ret;
0781     }
0782
0783     platform_set_drvdata(pdev, dra7xx);
0784
0785     pm_runtime_enable(dev);
0786     ret = pm_runtime_get_sync(dev);
0787     if (ret < 0) {
0788         dev_err(dev, "pm_runtime_get_sync failed\n");
0789         goto err_get_sync;
0790     }
0791
0792     reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
0793     if (IS_ERR(reset)) {
0794         ret = PTR_ERR(reset);
0795         dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
0796         goto err_gpio;
0797     }
0798
0799     reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
0800     reg &= ~LTSSM_EN;
0801     dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
0802
0803     switch (mode) {
0804     case DW_PCIE_RC_TYPE:
0805         if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
0806             ret = -ENODEV;
0807             goto err_gpio;
0808         }
0809
0810         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
0811                    DEVICE_TYPE_RC);
0812
0813         ret = dra7xx_pcie_unaligned_memaccess(dev);
0814         if (ret)
0815             dev_err(dev, "WA for Errata i870 not applied\n");
0816
0817         ret = dra7xx_add_pcie_port(dra7xx, pdev);
0818         if (ret < 0)
0819             goto err_gpio;
0820         break;
0821     case DW_PCIE_EP_TYPE:
0822         if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
0823             ret = -ENODEV;
0824             goto err_gpio;
0825         }
0826
0827         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
0828                    DEVICE_TYPE_EP);
0829
0830         ret = dra7xx_pcie_unaligned_memaccess(dev);
0831         if (ret)
0832             goto err_gpio;
0833
0834         ret = dra7xx_add_pcie_ep(dra7xx, pdev);
0835         if (ret < 0)
0836             goto err_gpio;
0837         break;
0838     default:
0839         dev_err(dev, "INVALID device type %d\n", mode);
0840     }
0841     dra7xx->mode = mode;
0842
0843     ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
0844                    IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
0845     if (ret) {
0846         dev_err(dev, "failed to request irq\n");
0847         goto err_gpio;
0848     }
0849
0850     return 0;
0851
0852 err_gpio:
0853 err_get_sync:
0854     pm_runtime_put(dev);
0855     pm_runtime_disable(dev);
0856     dra7xx_pcie_disable_phy(dra7xx);
0857
0858 err_link:
0859     while (--i >= 0)
0860         device_link_del(link[i]);
0861
0862     return ret;
0863 }
0864
0865 static int dra7xx_pcie_suspend(struct device *dev)
0866 {
0867     struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
0868     struct dw_pcie *pci = dra7xx->pci;
0869     u32 val;
0870
0871     if (dra7xx->mode != DW_PCIE_RC_TYPE)
0872         return 0;
0873
0874     /* clear MSE */
0875     val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
0876     val &= ~PCI_COMMAND_MEMORY;
0877     dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
0878
0879     return 0;
0880 }
0881
0882 static int dra7xx_pcie_resume(struct device *dev)
0883 {
0884     struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
0885     struct dw_pcie *pci = dra7xx->pci;
0886     u32 val;
0887
0888     if (dra7xx->mode != DW_PCIE_RC_TYPE)
0889         return 0;
0890
0891     /* set MSE */
0892     val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
0893     val |= PCI_COMMAND_MEMORY;
0894     dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
0895
0896     return 0;
0897 }
0898
0899 static int dra7xx_pcie_suspend_noirq(struct device *dev)
0900 {
0901     struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
0902
0903     dra7xx_pcie_disable_phy(dra7xx);
0904
0905     return 0;
0906 }
0907
0908 static int dra7xx_pcie_resume_noirq(struct device *dev)
0909 {
0910     struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
0911     int ret;
0912
0913     ret = dra7xx_pcie_enable_phy(dra7xx);
0914     if (ret) {
0915         dev_err(dev, "failed to enable phy\n");
0916         return ret;
0917     }
0918
0919     return 0;
0920 }
0921
0922 static void dra7xx_pcie_shutdown(struct platform_device *pdev)
0923 {
0924     struct device *dev = &pdev->dev;
0925     struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
0926     int ret;
0927
0928     dra7xx_pcie_stop_link(dra7xx->pci);
0929
0930     ret = pm_runtime_put_sync(dev);
0931     if (ret < 0)
0932         dev_dbg(dev, "pm_runtime_put_sync failed\n");
0933
0934     pm_runtime_disable(dev);
0935     dra7xx_pcie_disable_phy(dra7xx);
0936
0937     clk_disable_unprepare(dra7xx->clk);
0938 }
0939
0940 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
0941     SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
0942     NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
0943                   dra7xx_pcie_resume_noirq)
0944 };
0945
0946 static struct platform_driver dra7xx_pcie_driver = {
0947     .probe = dra7xx_pcie_probe,
0948     .driver = {
0949         .name   = "dra7-pcie",
0950         .of_match_table = of_dra7xx_pcie_match,
0951         .suppress_bind_attrs = true,
0952         .pm = &dra7xx_pcie_pm_ops,
0953     },
0954     .shutdown = dra7xx_pcie_shutdown,
0955 };
0956 module_platform_driver(dra7xx_pcie_driver);
0957
0958 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
0959 MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");
0960 MODULE_LICENSE("GPL v2");