controller/cadence/pcie-cadence.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2017 Cadence
0003 // Cadence PCIe controller driver.
0004 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
0005
0006 #include <linux/kernel.h>
0007
0008 #include "pcie-cadence.h"
0009
0010 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
0011 {
0012     u32 delay = 0x3;
0013     u32 ltssm_control_cap;
0014
0015     /*
0016      * Set the LTSSM Detect Quiet state min. delay to 2ms.
0017      */
0018     ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP);
0019     ltssm_control_cap = ((ltssm_control_cap &
0020                 ~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) |
0021                 CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay));
0022
0023     cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap);
0024 }
0025
0026 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
0027                    u32 r, bool is_io,
0028                    u64 cpu_addr, u64 pci_addr, size_t size)
0029 {
0030     /*
0031      * roundup_pow_of_two() returns an unsigned long, which is not suited
0032      * for 64bit values.
0033      */
0034     u64 sz = 1ULL << fls64(size - 1);
0035     int nbits = ilog2(sz);
0036     u32 addr0, addr1, desc0, desc1;
0037
0038     if (nbits < 8)
0039         nbits = 8;
0040
0041     /* Set the PCI address */
0042     addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
0043         (lower_32_bits(pci_addr) & GENMASK(31, 8));
0044     addr1 = upper_32_bits(pci_addr);
0045
0046     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
0047     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
0048
0049     /* Set the PCIe header descriptor */
0050     if (is_io)
0051         desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
0052     else
0053         desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
0054     desc1 = 0;
0055
0056     /*
0057      * Whatever Bit [23] is set or not inside DESC0 register of the outbound
0058      * PCIe descriptor, the PCI function number must be set into
0059      * Bits [26:24] of DESC0 anyway.
0060      *
0061      * In Root Complex mode, the function number is always 0 but in Endpoint
0062      * mode, the PCIe controller may support more than one function. This
0063      * function number needs to be set properly into the outbound PCIe
0064      * descriptor.
0065      *
0066      * Besides, setting Bit [23] is mandatory when in Root Complex mode:
0067      * then the driver must provide the bus, resp. device, number in
0068      * Bits [7:0] of DESC1, resp. Bits[31:27] of DESC0. Like the function
0069      * number, the device number is always 0 in Root Complex mode.
0070      *
0071      * However when in Endpoint mode, we can clear Bit [23] of DESC0, hence
0072      * the PCIe controller will use the captured values for the bus and
0073      * device numbers.
0074      */
0075     if (pcie->is_rc) {
0076         /* The device and function numbers are always 0. */
0077         desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
0078              CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
0079         desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
0080     } else {
0081         /*
0082          * Use captured values for bus and device numbers but still
0083          * need to set the function number.
0084          */
0085         desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
0086     }
0087
0088     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
0089     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
0090
0091     /* Set the CPU address */
0092     if (pcie->ops->cpu_addr_fixup)
0093         cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
0094
0095     addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
0096         (lower_32_bits(cpu_addr) & GENMASK(31, 8));
0097     addr1 = upper_32_bits(cpu_addr);
0098
0099     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
0100     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
0101 }
0102
0103 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
0104                           u8 busnr, u8 fn,
0105                           u32 r, u64 cpu_addr)
0106 {
0107     u32 addr0, addr1, desc0, desc1;
0108
0109     desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG;
0110     desc1 = 0;
0111
0112     /* See cdns_pcie_set_outbound_region() comments above. */
0113     if (pcie->is_rc) {
0114         desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
0115              CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
0116         desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
0117     } else {
0118         desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
0119     }
0120
0121     /* Set the CPU address */
0122     if (pcie->ops->cpu_addr_fixup)
0123         cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
0124
0125     addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
0126         (lower_32_bits(cpu_addr) & GENMASK(31, 8));
0127     addr1 = upper_32_bits(cpu_addr);
0128
0129     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
0130     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
0131     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
0132     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
0133     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
0134     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
0135 }
0136
0137 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
0138 {
0139     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
0140     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
0141
0142     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), 0);
0143     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), 0);
0144
0145     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
0146     cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
0147 }
0148
0149 void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
0150 {
0151     int i = pcie->phy_count;
0152
0153     while (i--) {
0154         phy_power_off(pcie->phy[i]);
0155         phy_exit(pcie->phy[i]);
0156     }
0157 }
0158
0159 int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
0160 {
0161     int ret;
0162     int i;
0163
0164     for (i = 0; i < pcie->phy_count; i++) {
0165         ret = phy_init(pcie->phy[i]);
0166         if (ret < 0)
0167             goto err_phy;
0168
0169         ret = phy_power_on(pcie->phy[i]);
0170         if (ret < 0) {
0171             phy_exit(pcie->phy[i]);
0172             goto err_phy;
0173         }
0174     }
0175
0176     return 0;
0177
0178 err_phy:
0179     while (--i >= 0) {
0180         phy_power_off(pcie->phy[i]);
0181         phy_exit(pcie->phy[i]);
0182     }
0183
0184     return ret;
0185 }
0186
0187 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
0188 {
0189     struct device_node *np = dev->of_node;
0190     int phy_count;
0191     struct phy **phy;
0192     struct device_link **link;
0193     int i;
0194     int ret;
0195     const char *name;
0196
0197     phy_count = of_property_count_strings(np, "phy-names");
0198     if (phy_count < 1) {
0199         dev_err(dev, "no phy-names.  PHY will not be initialized\n");
0200         pcie->phy_count = 0;
0201         return 0;
0202     }
0203
0204     phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
0205     if (!phy)
0206         return -ENOMEM;
0207
0208     link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
0209     if (!link)
0210         return -ENOMEM;
0211
0212     for (i = 0; i < phy_count; i++) {
0213         of_property_read_string_index(np, "phy-names", i, &name);
0214         phy[i] = devm_phy_get(dev, name);
0215         if (IS_ERR(phy[i])) {
0216             ret = PTR_ERR(phy[i]);
0217             goto err_phy;
0218         }
0219         link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
0220         if (!link[i]) {
0221             devm_phy_put(dev, phy[i]);
0222             ret = -EINVAL;
0223             goto err_phy;
0224         }
0225     }
0226
0227     pcie->phy_count = phy_count;
0228     pcie->phy = phy;
0229     pcie->link = link;
0230
0231     ret =  cdns_pcie_enable_phy(pcie);
0232     if (ret)
0233         goto err_phy;
0234
0235     return 0;
0236
0237 err_phy:
0238     while (--i >= 0) {
0239         device_link_del(link[i]);
0240         devm_phy_put(dev, phy[i]);
0241     }
0242
0243     return ret;
0244 }
0245
0246 static int cdns_pcie_suspend_noirq(struct device *dev)
0247 {
0248     struct cdns_pcie *pcie = dev_get_drvdata(dev);
0249
0250     cdns_pcie_disable_phy(pcie);
0251
0252     return 0;
0253 }
0254
0255 static int cdns_pcie_resume_noirq(struct device *dev)
0256 {
0257     struct cdns_pcie *pcie = dev_get_drvdata(dev);
0258     int ret;
0259
0260     ret = cdns_pcie_enable_phy(pcie);
0261     if (ret) {
0262         dev_err(dev, "failed to enable phy\n");
0263         return ret;
0264     }
0265
0266     return 0;
0267 }
0268
0269 const struct dev_pm_ops cdns_pcie_pm_ops = {
0270     NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
0271                   cdns_pcie_resume_noirq)
0272 };