drivers/pci/access.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/pci.h>
0003 #include <linux/module.h>
0004 #include <linux/slab.h>
0005 #include <linux/ioport.h>
0006 #include <linux/wait.h>
0007
0008 #include "pci.h"
0009
0010 /*
0011  * This interrupt-safe spinlock protects all accesses to PCI
0012  * configuration space.
0013  */
0014
0015 DEFINE_RAW_SPINLOCK(pci_lock);
0016
0017 /*
0018  * Wrappers for all PCI configuration access functions.  They just check
0019  * alignment, do locking and call the low-level functions pointed to
0020  * by pci_dev->ops.
0021  */
0022
0023 #define PCI_byte_BAD 0
0024 #define PCI_word_BAD (pos & 1)
0025 #define PCI_dword_BAD (pos & 3)
0026
0027 #ifdef CONFIG_PCI_LOCKLESS_CONFIG
0028 # define pci_lock_config(f) do { (void)(f); } while (0)
0029 # define pci_unlock_config(f)   do { (void)(f); } while (0)
0030 #else
0031 # define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
0032 # define pci_unlock_config(f)   raw_spin_unlock_irqrestore(&pci_lock, f)
0033 #endif
0034
0035 #define PCI_OP_READ(size, type, len) \
0036 int noinline pci_bus_read_config_##size \
0037     (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
0038 {                                   \
0039     int res;                            \
0040     unsigned long flags;                        \
0041     u32 data = 0;                           \
0042     if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;   \
0043     pci_lock_config(flags);                     \
0044     res = bus->ops->read(bus, devfn, pos, len, &data);      \
0045     if (res)                            \
0046         PCI_SET_ERROR_RESPONSE(value);              \
0047     else                                \
0048         *value = (type)data;                    \
0049     pci_unlock_config(flags);                   \
0050     return res;                         \
0051 }
0052
0053 #define PCI_OP_WRITE(size, type, len) \
0054 int noinline pci_bus_write_config_##size \
0055     (struct pci_bus *bus, unsigned int devfn, int pos, type value)  \
0056 {                                   \
0057     int res;                            \
0058     unsigned long flags;                        \
0059     if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;   \
0060     pci_lock_config(flags);                     \
0061     res = bus->ops->write(bus, devfn, pos, len, value);     \
0062     pci_unlock_config(flags);                   \
0063     return res;                         \
0064 }
0065
0066 PCI_OP_READ(byte, u8, 1)
0067 PCI_OP_READ(word, u16, 2)
0068 PCI_OP_READ(dword, u32, 4)
0069 PCI_OP_WRITE(byte, u8, 1)
0070 PCI_OP_WRITE(word, u16, 2)
0071 PCI_OP_WRITE(dword, u32, 4)
0072
0073 EXPORT_SYMBOL(pci_bus_read_config_byte);
0074 EXPORT_SYMBOL(pci_bus_read_config_word);
0075 EXPORT_SYMBOL(pci_bus_read_config_dword);
0076 EXPORT_SYMBOL(pci_bus_write_config_byte);
0077 EXPORT_SYMBOL(pci_bus_write_config_word);
0078 EXPORT_SYMBOL(pci_bus_write_config_dword);
0079
0080 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
0081                 int where, int size, u32 *val)
0082 {
0083     void __iomem *addr;
0084
0085     addr = bus->ops->map_bus(bus, devfn, where);
0086     if (!addr)
0087         return PCIBIOS_DEVICE_NOT_FOUND;
0088
0089     if (size == 1)
0090         *val = readb(addr);
0091     else if (size == 2)
0092         *val = readw(addr);
0093     else
0094         *val = readl(addr);
0095
0096     return PCIBIOS_SUCCESSFUL;
0097 }
0098 EXPORT_SYMBOL_GPL(pci_generic_config_read);
0099
0100 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
0101                  int where, int size, u32 val)
0102 {
0103     void __iomem *addr;
0104
0105     addr = bus->ops->map_bus(bus, devfn, where);
0106     if (!addr)
0107         return PCIBIOS_DEVICE_NOT_FOUND;
0108
0109     if (size == 1)
0110         writeb(val, addr);
0111     else if (size == 2)
0112         writew(val, addr);
0113     else
0114         writel(val, addr);
0115
0116     return PCIBIOS_SUCCESSFUL;
0117 }
0118 EXPORT_SYMBOL_GPL(pci_generic_config_write);
0119
0120 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
0121                   int where, int size, u32 *val)
0122 {
0123     void __iomem *addr;
0124
0125     addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
0126     if (!addr)
0127         return PCIBIOS_DEVICE_NOT_FOUND;
0128
0129     *val = readl(addr);
0130
0131     if (size <= 2)
0132         *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
0133
0134     return PCIBIOS_SUCCESSFUL;
0135 }
0136 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
0137
0138 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
0139                    int where, int size, u32 val)
0140 {
0141     void __iomem *addr;
0142     u32 mask, tmp;
0143
0144     addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
0145     if (!addr)
0146         return PCIBIOS_DEVICE_NOT_FOUND;
0147
0148     if (size == 4) {
0149         writel(val, addr);
0150         return PCIBIOS_SUCCESSFUL;
0151     }
0152
0153     /*
0154      * In general, hardware that supports only 32-bit writes on PCI is
0155      * not spec-compliant.  For example, software may perform a 16-bit
0156      * write.  If the hardware only supports 32-bit accesses, we must
0157      * do a 32-bit read, merge in the 16 bits we intend to write,
0158      * followed by a 32-bit write.  If the 16 bits we *don't* intend to
0159      * write happen to have any RW1C (write-one-to-clear) bits set, we
0160      * just inadvertently cleared something we shouldn't have.
0161      */
0162     if (!bus->unsafe_warn) {
0163         dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
0164              size, pci_domain_nr(bus), bus->number,
0165              PCI_SLOT(devfn), PCI_FUNC(devfn), where);
0166         bus->unsafe_warn = 1;
0167     }
0168
0169     mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
0170     tmp = readl(addr) & mask;
0171     tmp |= val << ((where & 0x3) * 8);
0172     writel(tmp, addr);
0173
0174     return PCIBIOS_SUCCESSFUL;
0175 }
0176 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
0177
0178 /**
0179  * pci_bus_set_ops - Set raw operations of pci bus
0180  * @bus:    pci bus struct
0181  * @ops:    new raw operations
0182  *
0183  * Return previous raw operations
0184  */
0185 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
0186 {
0187     struct pci_ops *old_ops;
0188     unsigned long flags;
0189
0190     raw_spin_lock_irqsave(&pci_lock, flags);
0191     old_ops = bus->ops;
0192     bus->ops = ops;
0193     raw_spin_unlock_irqrestore(&pci_lock, flags);
0194     return old_ops;
0195 }
0196 EXPORT_SYMBOL(pci_bus_set_ops);
0197
0198 /*
0199  * The following routines are to prevent the user from accessing PCI config
0200  * space when it's unsafe to do so.  Some devices require this during BIST and
0201  * we're required to prevent it during D-state transitions.
0202  *
0203  * We have a bit per device to indicate it's blocked and a global wait queue
0204  * for callers to sleep on until devices are unblocked.
0205  */
0206 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
0207
0208 static noinline void pci_wait_cfg(struct pci_dev *dev)
0209     __must_hold(&pci_lock)
0210 {
0211     do {
0212         raw_spin_unlock_irq(&pci_lock);
0213         wait_event(pci_cfg_wait, !dev->block_cfg_access);
0214         raw_spin_lock_irq(&pci_lock);
0215     } while (dev->block_cfg_access);
0216 }
0217
0218 /* Returns 0 on success, negative values indicate error. */
0219 #define PCI_USER_READ_CONFIG(size, type)                    \
0220 int pci_user_read_config_##size                     \
0221     (struct pci_dev *dev, int pos, type *val)           \
0222 {                                   \
0223     int ret = PCIBIOS_SUCCESSFUL;                   \
0224     u32 data = -1;                          \
0225     if (PCI_##size##_BAD)                       \
0226         return -EINVAL;                     \
0227     raw_spin_lock_irq(&pci_lock);               \
0228     if (unlikely(dev->block_cfg_access))                \
0229         pci_wait_cfg(dev);                  \
0230     ret = dev->bus->ops->read(dev->bus, dev->devfn,         \
0231                     pos, sizeof(type), &data);  \
0232     raw_spin_unlock_irq(&pci_lock);             \
0233     if (ret)                            \
0234         PCI_SET_ERROR_RESPONSE(val);                \
0235     else                                \
0236         *val = (type)data;                  \
0237     return pcibios_err_to_errno(ret);               \
0238 }                                   \
0239 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
0240
0241 /* Returns 0 on success, negative values indicate error. */
0242 #define PCI_USER_WRITE_CONFIG(size, type)               \
0243 int pci_user_write_config_##size                    \
0244     (struct pci_dev *dev, int pos, type val)            \
0245 {                                   \
0246     int ret = PCIBIOS_SUCCESSFUL;                   \
0247     if (PCI_##size##_BAD)                       \
0248         return -EINVAL;                     \
0249     raw_spin_lock_irq(&pci_lock);               \
0250     if (unlikely(dev->block_cfg_access))                \
0251         pci_wait_cfg(dev);                  \
0252     ret = dev->bus->ops->write(dev->bus, dev->devfn,        \
0253                     pos, sizeof(type), val);    \
0254     raw_spin_unlock_irq(&pci_lock);             \
0255     return pcibios_err_to_errno(ret);               \
0256 }                                   \
0257 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
0258
0259 PCI_USER_READ_CONFIG(byte, u8)
0260 PCI_USER_READ_CONFIG(word, u16)
0261 PCI_USER_READ_CONFIG(dword, u32)
0262 PCI_USER_WRITE_CONFIG(byte, u8)
0263 PCI_USER_WRITE_CONFIG(word, u16)
0264 PCI_USER_WRITE_CONFIG(dword, u32)
0265
0266 /**
0267  * pci_cfg_access_lock - Lock PCI config reads/writes
0268  * @dev:    pci device struct
0269  *
0270  * When access is locked, any userspace reads or writes to config
0271  * space and concurrent lock requests will sleep until access is
0272  * allowed via pci_cfg_access_unlock() again.
0273  */
0274 void pci_cfg_access_lock(struct pci_dev *dev)
0275 {
0276     might_sleep();
0277
0278     raw_spin_lock_irq(&pci_lock);
0279     if (dev->block_cfg_access)
0280         pci_wait_cfg(dev);
0281     dev->block_cfg_access = 1;
0282     raw_spin_unlock_irq(&pci_lock);
0283 }
0284 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
0285
0286 /**
0287  * pci_cfg_access_trylock - try to lock PCI config reads/writes
0288  * @dev:    pci device struct
0289  *
0290  * Same as pci_cfg_access_lock, but will return 0 if access is
0291  * already locked, 1 otherwise. This function can be used from
0292  * atomic contexts.
0293  */
0294 bool pci_cfg_access_trylock(struct pci_dev *dev)
0295 {
0296     unsigned long flags;
0297     bool locked = true;
0298
0299     raw_spin_lock_irqsave(&pci_lock, flags);
0300     if (dev->block_cfg_access)
0301         locked = false;
0302     else
0303         dev->block_cfg_access = 1;
0304     raw_spin_unlock_irqrestore(&pci_lock, flags);
0305
0306     return locked;
0307 }
0308 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
0309
0310 /**
0311  * pci_cfg_access_unlock - Unlock PCI config reads/writes
0312  * @dev:    pci device struct
0313  *
0314  * This function allows PCI config accesses to resume.
0315  */
0316 void pci_cfg_access_unlock(struct pci_dev *dev)
0317 {
0318     unsigned long flags;
0319
0320     raw_spin_lock_irqsave(&pci_lock, flags);
0321
0322     /*
0323      * This indicates a problem in the caller, but we don't need
0324      * to kill them, unlike a double-block above.
0325      */
0326     WARN_ON(!dev->block_cfg_access);
0327
0328     dev->block_cfg_access = 0;
0329     raw_spin_unlock_irqrestore(&pci_lock, flags);
0330
0331     wake_up_all(&pci_cfg_wait);
0332 }
0333 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
0334
0335 static inline int pcie_cap_version(const struct pci_dev *dev)
0336 {
0337     return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
0338 }
0339
0340 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
0341 {
0342     int type = pci_pcie_type(dev);
0343
0344     return type == PCI_EXP_TYPE_ENDPOINT ||
0345            type == PCI_EXP_TYPE_LEG_END ||
0346            type == PCI_EXP_TYPE_ROOT_PORT ||
0347            type == PCI_EXP_TYPE_UPSTREAM ||
0348            type == PCI_EXP_TYPE_DOWNSTREAM ||
0349            type == PCI_EXP_TYPE_PCI_BRIDGE ||
0350            type == PCI_EXP_TYPE_PCIE_BRIDGE;
0351 }
0352
0353 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
0354 {
0355     return pcie_downstream_port(dev) &&
0356            pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
0357 }
0358
0359 bool pcie_cap_has_rtctl(const struct pci_dev *dev)
0360 {
0361     int type = pci_pcie_type(dev);
0362
0363     return type == PCI_EXP_TYPE_ROOT_PORT ||
0364            type == PCI_EXP_TYPE_RC_EC;
0365 }
0366
0367 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
0368 {
0369     if (!pci_is_pcie(dev))
0370         return false;
0371
0372     switch (pos) {
0373     case PCI_EXP_FLAGS:
0374         return true;
0375     case PCI_EXP_DEVCAP:
0376     case PCI_EXP_DEVCTL:
0377     case PCI_EXP_DEVSTA:
0378         return true;
0379     case PCI_EXP_LNKCAP:
0380     case PCI_EXP_LNKCTL:
0381     case PCI_EXP_LNKSTA:
0382         return pcie_cap_has_lnkctl(dev);
0383     case PCI_EXP_SLTCAP:
0384     case PCI_EXP_SLTCTL:
0385     case PCI_EXP_SLTSTA:
0386         return pcie_cap_has_sltctl(dev);
0387     case PCI_EXP_RTCTL:
0388     case PCI_EXP_RTCAP:
0389     case PCI_EXP_RTSTA:
0390         return pcie_cap_has_rtctl(dev);
0391     case PCI_EXP_DEVCAP2:
0392     case PCI_EXP_DEVCTL2:
0393     case PCI_EXP_LNKCAP2:
0394     case PCI_EXP_LNKCTL2:
0395     case PCI_EXP_LNKSTA2:
0396         return pcie_cap_version(dev) > 1;
0397     default:
0398         return false;
0399     }
0400 }
0401
0402 /*
0403  * Note that these accessor functions are only for the "PCI Express
0404  * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
0405  * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
0406  */
0407 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
0408 {
0409     int ret;
0410
0411     *val = 0;
0412     if (pos & 1)
0413         return PCIBIOS_BAD_REGISTER_NUMBER;
0414
0415     if (pcie_capability_reg_implemented(dev, pos)) {
0416         ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
0417         /*
0418          * Reset *val to 0 if pci_read_config_word() fails; it may
0419          * have been written as 0xFFFF (PCI_ERROR_RESPONSE) if the
0420          * config read failed on PCI.
0421          */
0422         if (ret)
0423             *val = 0;
0424         return ret;
0425     }
0426
0427     /*
0428      * For Functions that do not implement the Slot Capabilities,
0429      * Slot Status, and Slot Control registers, these spaces must
0430      * be hardwired to 0b, with the exception of the Presence Detect
0431      * State bit in the Slot Status register of Downstream Ports,
0432      * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
0433      */
0434     if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
0435         pos == PCI_EXP_SLTSTA)
0436         *val = PCI_EXP_SLTSTA_PDS;
0437
0438     return 0;
0439 }
0440 EXPORT_SYMBOL(pcie_capability_read_word);
0441
0442 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
0443 {
0444     int ret;
0445
0446     *val = 0;
0447     if (pos & 3)
0448         return PCIBIOS_BAD_REGISTER_NUMBER;
0449
0450     if (pcie_capability_reg_implemented(dev, pos)) {
0451         ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
0452         /*
0453          * Reset *val to 0 if pci_read_config_dword() fails; it may
0454          * have been written as 0xFFFFFFFF (PCI_ERROR_RESPONSE) if
0455          * the config read failed on PCI.
0456          */
0457         if (ret)
0458             *val = 0;
0459         return ret;
0460     }
0461
0462     if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
0463         pos == PCI_EXP_SLTSTA)
0464         *val = PCI_EXP_SLTSTA_PDS;
0465
0466     return 0;
0467 }
0468 EXPORT_SYMBOL(pcie_capability_read_dword);
0469
0470 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
0471 {
0472     if (pos & 1)
0473         return PCIBIOS_BAD_REGISTER_NUMBER;
0474
0475     if (!pcie_capability_reg_implemented(dev, pos))
0476         return 0;
0477
0478     return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
0479 }
0480 EXPORT_SYMBOL(pcie_capability_write_word);
0481
0482 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
0483 {
0484     if (pos & 3)
0485         return PCIBIOS_BAD_REGISTER_NUMBER;
0486
0487     if (!pcie_capability_reg_implemented(dev, pos))
0488         return 0;
0489
0490     return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
0491 }
0492 EXPORT_SYMBOL(pcie_capability_write_dword);
0493
0494 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
0495                        u16 clear, u16 set)
0496 {
0497     int ret;
0498     u16 val;
0499
0500     ret = pcie_capability_read_word(dev, pos, &val);
0501     if (!ret) {
0502         val &= ~clear;
0503         val |= set;
0504         ret = pcie_capability_write_word(dev, pos, val);
0505     }
0506
0507     return ret;
0508 }
0509 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
0510
0511 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
0512                     u32 clear, u32 set)
0513 {
0514     int ret;
0515     u32 val;
0516
0517     ret = pcie_capability_read_dword(dev, pos, &val);
0518     if (!ret) {
0519         val &= ~clear;
0520         val |= set;
0521         ret = pcie_capability_write_dword(dev, pos, val);
0522     }
0523
0524     return ret;
0525 }
0526 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
0527
0528 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
0529 {
0530     if (pci_dev_is_disconnected(dev)) {
0531         PCI_SET_ERROR_RESPONSE(val);
0532         return PCIBIOS_DEVICE_NOT_FOUND;
0533     }
0534     return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
0535 }
0536 EXPORT_SYMBOL(pci_read_config_byte);
0537
0538 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
0539 {
0540     if (pci_dev_is_disconnected(dev)) {
0541         PCI_SET_ERROR_RESPONSE(val);
0542         return PCIBIOS_DEVICE_NOT_FOUND;
0543     }
0544     return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
0545 }
0546 EXPORT_SYMBOL(pci_read_config_word);
0547
0548 int pci_read_config_dword(const struct pci_dev *dev, int where,
0549                     u32 *val)
0550 {
0551     if (pci_dev_is_disconnected(dev)) {
0552         PCI_SET_ERROR_RESPONSE(val);
0553         return PCIBIOS_DEVICE_NOT_FOUND;
0554     }
0555     return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
0556 }
0557 EXPORT_SYMBOL(pci_read_config_dword);
0558
0559 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
0560 {
0561     if (pci_dev_is_disconnected(dev))
0562         return PCIBIOS_DEVICE_NOT_FOUND;
0563     return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
0564 }
0565 EXPORT_SYMBOL(pci_write_config_byte);
0566
0567 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
0568 {
0569     if (pci_dev_is_disconnected(dev))
0570         return PCIBIOS_DEVICE_NOT_FOUND;
0571     return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
0572 }
0573 EXPORT_SYMBOL(pci_write_config_word);
0574
0575 int pci_write_config_dword(const struct pci_dev *dev, int where,
0576                      u32 val)
0577 {
0578     if (pci_dev_is_disconnected(dev))
0579         return PCIBIOS_DEVICE_NOT_FOUND;
0580     return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
0581 }
0582 EXPORT_SYMBOL(pci_write_config_dword);