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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 **
0004 **  PCI Lower Bus Adapter (LBA) manager
0005 **
0006 **  (c) Copyright 1999,2000 Grant Grundler
0007 **  (c) Copyright 1999,2000 Hewlett-Packard Company
0008 **
0009 **
0010 **
0011 ** This module primarily provides access to PCI bus (config/IOport
0012 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
0013 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
0014 **
0015 ** LBA driver isn't as simple as the Dino driver because:
0016 **   (a) this chip has substantial bug fixes between revisions
0017 **       (Only one Dino bug has a software workaround :^(  )
0018 **   (b) has more options which we don't (yet) support (DMA hints, OLARD)
0019 **   (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
0020 **   (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
0021 **       (dino only deals with "Legacy" PDC)
0022 **
0023 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
0024 ** (I/O SAPIC is integratd in the LBA chip).
0025 **
0026 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
0027 ** FIXME: Add support for PCI card hot-plug (OLARD).
0028 */
0029 
0030 #include <linux/delay.h>
0031 #include <linux/types.h>
0032 #include <linux/kernel.h>
0033 #include <linux/spinlock.h>
0034 #include <linux/init.h>     /* for __init */
0035 #include <linux/pci.h>
0036 #include <linux/ioport.h>
0037 #include <linux/slab.h>
0038 
0039 #include <asm/byteorder.h>
0040 #include <asm/pdc.h>
0041 #include <asm/pdcpat.h>
0042 #include <asm/page.h>
0043 
0044 #include <asm/ropes.h>
0045 #include <asm/hardware.h>   /* for register_parisc_driver() stuff */
0046 #include <asm/parisc-device.h>
0047 #include <asm/io.h>     /* read/write stuff */
0048 
0049 #include "iommu.h"
0050 
0051 #undef DEBUG_LBA    /* general stuff */
0052 #undef DEBUG_LBA_PORT   /* debug I/O Port access */
0053 #undef DEBUG_LBA_CFG    /* debug Config Space Access (ie PCI Bus walk) */
0054 #undef DEBUG_LBA_PAT    /* debug PCI Resource Mgt code - PDC PAT only */
0055 
0056 #undef FBB_SUPPORT  /* Fast Back-Back xfers - NOT READY YET */
0057 
0058 
0059 #ifdef DEBUG_LBA
0060 #define DBG(x...)   printk(x)
0061 #else
0062 #define DBG(x...)
0063 #endif
0064 
0065 #ifdef DEBUG_LBA_PORT
0066 #define DBG_PORT(x...)  printk(x)
0067 #else
0068 #define DBG_PORT(x...)
0069 #endif
0070 
0071 #ifdef DEBUG_LBA_CFG
0072 #define DBG_CFG(x...)   printk(x)
0073 #else
0074 #define DBG_CFG(x...)
0075 #endif
0076 
0077 #ifdef DEBUG_LBA_PAT
0078 #define DBG_PAT(x...)   printk(x)
0079 #else
0080 #define DBG_PAT(x...)
0081 #endif
0082 
0083 
0084 /*
0085 ** Config accessor functions only pass in the 8-bit bus number and not
0086 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
0087 ** number based on what firmware wrote into the scratch register.
0088 **
0089 ** The "secondary" bus number is set to this before calling
0090 ** pci_register_ops(). If any PPB's are present, the scan will
0091 ** discover them and update the "secondary" and "subordinate"
0092 ** fields in the pci_bus structure.
0093 **
0094 ** Changes in the configuration *may* result in a different
0095 ** bus number for each LBA depending on what firmware does.
0096 */
0097 
0098 #define MODULE_NAME "LBA"
0099 
0100 /* non-postable I/O port space, densely packed */
0101 #define LBA_PORT_BASE   (PCI_F_EXTEND | 0xfee00000UL)
0102 static void __iomem *astro_iop_base __read_mostly;
0103 
0104 static u32 lba_t32;
0105 
0106 /* lba flags */
0107 #define LBA_FLAG_SKIP_PROBE 0x10
0108 
0109 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
0110 
0111 static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba)
0112 {
0113     return container_of(hba, struct lba_device, hba);
0114 }
0115 
0116 /*
0117 ** Only allow 8 subsidiary busses per LBA
0118 ** Problem is the PCI bus numbering is globally shared.
0119 */
0120 #define LBA_MAX_NUM_BUSES 8
0121 
0122 /************************************
0123  * LBA register read and write support
0124  *
0125  * BE WARNED: register writes are posted.
0126  *  (ie follow writes which must reach HW with a read)
0127  */
0128 #define READ_U8(addr)  __raw_readb(addr)
0129 #define READ_U16(addr) __raw_readw(addr)
0130 #define READ_U32(addr) __raw_readl(addr)
0131 #define WRITE_U8(value, addr)  __raw_writeb(value, addr)
0132 #define WRITE_U16(value, addr) __raw_writew(value, addr)
0133 #define WRITE_U32(value, addr) __raw_writel(value, addr)
0134 
0135 #define READ_REG8(addr)  readb(addr)
0136 #define READ_REG16(addr) readw(addr)
0137 #define READ_REG32(addr) readl(addr)
0138 #define READ_REG64(addr) readq(addr)
0139 #define WRITE_REG8(value, addr)  writeb(value, addr)
0140 #define WRITE_REG16(value, addr) writew(value, addr)
0141 #define WRITE_REG32(value, addr) writel(value, addr)
0142 
0143 
0144 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
0145 #define LBA_CFG_BUS(tok)  ((u8) ((tok)>>16))
0146 #define LBA_CFG_DEV(tok)  ((u8) ((tok)>>11) & 0x1f)
0147 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
0148 
0149 
0150 /*
0151 ** Extract LBA (Rope) number from HPA
0152 ** REVISIT: 16 ropes for Stretch/Ike?
0153 */
0154 #define ROPES_PER_IOC   8
0155 #define LBA_NUM(x)    ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
0156 
0157 
0158 static void
0159 lba_dump_res(struct resource *r, int d)
0160 {
0161     int i;
0162 
0163     if (NULL == r)
0164         return;
0165 
0166     printk(KERN_DEBUG "(%p)", r->parent);
0167     for (i = d; i ; --i) printk(" ");
0168     printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
0169         (long)r->start, (long)r->end, r->flags);
0170     lba_dump_res(r->child, d+2);
0171     lba_dump_res(r->sibling, d);
0172 }
0173 
0174 
0175 /*
0176 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
0177 ** workaround for cfg cycles:
0178 **  -- preserve  LBA state
0179 **  -- prevent any DMA from occurring
0180 **  -- turn on smart mode
0181 **  -- probe with config writes before doing config reads
0182 **  -- check ERROR_STATUS
0183 **  -- clear ERROR_STATUS
0184 **  -- restore LBA state
0185 **
0186 ** The workaround is only used for device discovery.
0187 */
0188 
0189 static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
0190 {
0191     u8 first_bus = d->hba.hba_bus->busn_res.start;
0192     u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
0193 
0194     if ((bus < first_bus) ||
0195         (bus > last_sub_bus) ||
0196         ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
0197         return 0;
0198     }
0199 
0200     return 1;
0201 }
0202 
0203 
0204 
0205 #define LBA_CFG_SETUP(d, tok) {             \
0206     /* Save contents of error config register.  */          \
0207     error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);     \
0208 \
0209     /* Save contents of status control register.  */            \
0210     status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);       \
0211 \
0212     /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA      \
0213     ** arbitration for full bus walks.                  \
0214     */                                  \
0215     /* Save contents of arb mask register. */           \
0216     arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);     \
0217 \
0218     /*                              \
0219      * Turn off all device arbitration bits (i.e. everything    \
0220      * except arbitration enable bit).              \
0221      */                             \
0222     WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK);      \
0223 \
0224     /*                                  \
0225      * Set the smart mode bit so that master aborts don't cause     \
0226      * LBA to go into PCI fatal mode (required).            \
0227      */                                 \
0228     WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG);    \
0229 }
0230 
0231 
0232 #define LBA_CFG_PROBE(d, tok) {             \
0233     /*                                  \
0234      * Setup Vendor ID write and read back the address register     \
0235      * to make sure that LBA is the bus master.             \
0236      */                                 \
0237     WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
0238     /*                                  \
0239      * Read address register to ensure that LBA is the bus master,  \
0240      * which implies that DMA traffic has stopped when DMA arb is off.  \
0241      */                                 \
0242     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);    \
0243     /*                                  \
0244      * Generate a cfg write cycle (will have no affect on       \
0245      * Vendor ID register since read-only).             \
0246      */                                 \
0247     WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA);     \
0248     /*                                  \
0249      * Make sure write has completed before proceeding further,     \
0250      * i.e. before setting clear enable.                \
0251      */                                 \
0252     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);    \
0253 }
0254 
0255 
0256 /*
0257  * HPREVISIT:
0258  *   -- Can't tell if config cycle got the error.
0259  *
0260  *      OV bit is broken until rev 4.0, so can't use OV bit and
0261  *      LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
0262  *
0263  *      As of rev 4.0, no longer need the error check.
0264  *
0265  *   -- Even if we could tell, we still want to return -1
0266  *  for **ANY** error (not just master abort).
0267  *
0268  *   -- Only clear non-fatal errors (we don't want to bring
0269  *  LBA out of pci-fatal mode).
0270  *
0271  *      Actually, there is still a race in which
0272  *      we could be clearing a fatal error.  We will
0273  *      live with this during our initial bus walk
0274  *      until rev 4.0 (no driver activity during
0275  *      initial bus walk).  The initial bus walk
0276  *      has race conditions concerning the use of
0277  *      smart mode as well.
0278  */
0279 
0280 #define LBA_MASTER_ABORT_ERROR 0xc
0281 #define LBA_FATAL_ERROR 0x10
0282 
0283 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) {       \
0284     u32 error_status = 0;                       \
0285     /*                                  \
0286      * Set clear enable (CE) bit. Unset by HW when new          \
0287      * errors are logged -- LBA HW ERS section 14.3.3).     \
0288      */                                 \
0289     WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
0290     error_status = READ_REG32(base + LBA_ERROR_STATUS);     \
0291     if ((error_status & 0x1f) != 0) {                   \
0292     /*                              \
0293      * Fail the config read request.                \
0294      */                             \
0295     error = 1;                          \
0296     if ((error_status & LBA_FATAL_ERROR) == 0) {            \
0297         /*                              \
0298          * Clear error status (if fatal bit not set) by setting \
0299          * clear error log bit (CL).                \
0300          */                             \
0301         WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
0302     }                               \
0303     }                                   \
0304 }
0305 
0306 #define LBA_CFG_TR4_ADDR_SETUP(d, addr)                 \
0307     WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
0308 
0309 #define LBA_CFG_ADDR_SETUP(d, addr) {                   \
0310     WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);  \
0311     /*                                  \
0312      * Read address register to ensure that LBA is the bus master,  \
0313      * which implies that DMA traffic has stopped when DMA arb is off.  \
0314      */                                 \
0315     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);    \
0316 }
0317 
0318 
0319 #define LBA_CFG_RESTORE(d, base) {                  \
0320     /*                                  \
0321      * Restore status control register (turn off clear enable).     \
0322      */                                 \
0323     WRITE_REG32(status_control, base + LBA_STAT_CTL);           \
0324     /*                                  \
0325      * Restore error config register (turn off smart mode).     \
0326      */                                 \
0327     WRITE_REG32(error_config, base + LBA_ERROR_CONFIG);         \
0328     /*                              \
0329      * Restore arb mask register (reenables DMA arbitration).   \
0330      */                             \
0331     WRITE_REG32(arb_mask, base + LBA_ARB_MASK);         \
0332 }
0333 
0334 
0335 
0336 static unsigned int
0337 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
0338 {
0339     u32 data = ~0U;
0340     int error = 0;
0341     u32 arb_mask = 0;   /* used by LBA_CFG_SETUP/RESTORE */
0342     u32 error_config = 0;   /* used by LBA_CFG_SETUP/RESTORE */
0343     u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
0344 
0345     LBA_CFG_SETUP(d, tok);
0346     LBA_CFG_PROBE(d, tok);
0347     LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
0348     if (!error) {
0349         void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
0350 
0351         LBA_CFG_ADDR_SETUP(d, tok | reg);
0352         switch (size) {
0353         case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
0354         case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
0355         case 4: data = READ_REG32(data_reg); break;
0356         }
0357     }
0358     LBA_CFG_RESTORE(d, d->hba.base_addr);
0359     return(data);
0360 }
0361 
0362 
0363 static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
0364 {
0365     struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
0366     u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
0367     u32 tok = LBA_CFG_TOK(local_bus, devfn);
0368     void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
0369 
0370     if ((pos > 255) || (devfn > 255))
0371         return -EINVAL;
0372 
0373 /* FIXME: B2K/C3600 workaround is always use old method... */
0374     /* if (!LBA_SKIP_PROBE(d)) */ {
0375         /* original - Generate config cycle on broken elroy
0376           with risk we will miss PCI bus errors. */
0377         *data = lba_rd_cfg(d, tok, pos, size);
0378         DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
0379         return 0;
0380     }
0381 
0382     if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
0383         DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
0384         /* either don't want to look or know device isn't present. */
0385         *data = ~0U;
0386         return(0);
0387     }
0388 
0389     /* Basic Algorithm
0390     ** Should only get here on fully working LBA rev.
0391     ** This is how simple the code should have been.
0392     */
0393     LBA_CFG_ADDR_SETUP(d, tok | pos);
0394     switch(size) {
0395     case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
0396     case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
0397     case 4: *data = READ_REG32(data_reg); break;
0398     }
0399     DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
0400     return 0;
0401 }
0402 
0403 
0404 static void
0405 lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
0406 {
0407     int error = 0;
0408     u32 arb_mask = 0;
0409     u32 error_config = 0;
0410     u32 status_control = 0;
0411     void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
0412 
0413     LBA_CFG_SETUP(d, tok);
0414     LBA_CFG_ADDR_SETUP(d, tok | reg);
0415     switch (size) {
0416     case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
0417     case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
0418     case 4: WRITE_REG32(data, data_reg);             break;
0419     }
0420     LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
0421     LBA_CFG_RESTORE(d, d->hba.base_addr);
0422 }
0423 
0424 
0425 /*
0426  * LBA 4.0 config write code implements non-postable semantics
0427  * by doing a read of CONFIG ADDR after the write.
0428  */
0429 
0430 static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
0431 {
0432     struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
0433     u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
0434     u32 tok = LBA_CFG_TOK(local_bus,devfn);
0435 
0436     if ((pos > 255) || (devfn > 255))
0437         return -EINVAL;
0438 
0439     if (!LBA_SKIP_PROBE(d)) {
0440         /* Original Workaround */
0441         lba_wr_cfg(d, tok, pos, (u32) data, size);
0442         DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data);
0443         return 0;
0444     }
0445 
0446     if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
0447         DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
0448         return 1; /* New Workaround */
0449     }
0450 
0451     DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data);
0452 
0453     /* Basic Algorithm */
0454     LBA_CFG_ADDR_SETUP(d, tok | pos);
0455     switch(size) {
0456     case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
0457            break;
0458     case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
0459            break;
0460     case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
0461            break;
0462     }
0463     /* flush posted write */
0464     lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
0465     return 0;
0466 }
0467 
0468 
0469 static struct pci_ops elroy_cfg_ops = {
0470     .read =     elroy_cfg_read,
0471     .write =    elroy_cfg_write,
0472 };
0473 
0474 /*
0475  * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
0476  * TR4.0 as no additional bugs were found in this areea between Elroy and
0477  * Mercury
0478  */
0479 
0480 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
0481 {
0482     struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
0483     u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
0484     u32 tok = LBA_CFG_TOK(local_bus, devfn);
0485     void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
0486 
0487     if ((pos > 255) || (devfn > 255))
0488         return -EINVAL;
0489 
0490     LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
0491     switch(size) {
0492     case 1:
0493         *data = READ_REG8(data_reg + (pos & 3));
0494         break;
0495     case 2:
0496         *data = READ_REG16(data_reg + (pos & 2));
0497         break;
0498     case 4:
0499         *data = READ_REG32(data_reg);             break;
0500         break;
0501     }
0502 
0503     DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
0504     return 0;
0505 }
0506 
0507 /*
0508  * LBA 4.0 config write code implements non-postable semantics
0509  * by doing a read of CONFIG ADDR after the write.
0510  */
0511 
0512 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
0513 {
0514     struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
0515     void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
0516     u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
0517     u32 tok = LBA_CFG_TOK(local_bus,devfn);
0518 
0519     if ((pos > 255) || (devfn > 255))
0520         return -EINVAL;
0521 
0522     DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data);
0523 
0524     LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
0525     switch(size) {
0526     case 1:
0527         WRITE_REG8 (data, data_reg + (pos & 3));
0528         break;
0529     case 2:
0530         WRITE_REG16(data, data_reg + (pos & 2));
0531         break;
0532     case 4:
0533         WRITE_REG32(data, data_reg);
0534         break;
0535     }
0536 
0537     /* flush posted write */
0538     lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
0539     return 0;
0540 }
0541 
0542 static struct pci_ops mercury_cfg_ops = {
0543     .read =     mercury_cfg_read,
0544     .write =    mercury_cfg_write,
0545 };
0546 
0547 
0548 static void
0549 lba_bios_init(void)
0550 {
0551     DBG(MODULE_NAME ": lba_bios_init\n");
0552 }
0553 
0554 
0555 #ifdef CONFIG_64BIT
0556 
0557 /*
0558  * truncate_pat_collision:  Deal with overlaps or outright collisions
0559  *          between PAT PDC reported ranges.
0560  *
0561  *   Broken PA8800 firmware will report lmmio range that
0562  *   overlaps with CPU HPA. Just truncate the lmmio range.
0563  *
0564  *   BEWARE: conflicts with this lmmio range may be an
0565  *   elmmio range which is pointing down another rope.
0566  *
0567  *  FIXME: only deals with one collision per range...theoretically we
0568  *  could have several. Supporting more than one collision will get messy.
0569  */
0570 static unsigned long
0571 truncate_pat_collision(struct resource *root, struct resource *new)
0572 {
0573     unsigned long start = new->start;
0574     unsigned long end = new->end;
0575     struct resource *tmp = root->child;
0576 
0577     if (end <= start || start < root->start || !tmp)
0578         return 0;
0579 
0580     /* find first overlap */
0581     while (tmp && tmp->end < start)
0582         tmp = tmp->sibling;
0583 
0584     /* no entries overlap */
0585     if (!tmp)  return 0;
0586 
0587     /* found one that starts behind the new one
0588     ** Don't need to do anything.
0589     */
0590     if (tmp->start >= end) return 0;
0591 
0592     if (tmp->start <= start) {
0593         /* "front" of new one overlaps */
0594         new->start = tmp->end + 1;
0595 
0596         if (tmp->end >= end) {
0597             /* AACCKK! totally overlaps! drop this range. */
0598             return 1;
0599         }
0600     } 
0601 
0602     if (tmp->end < end ) {
0603         /* "end" of new one overlaps */
0604         new->end = tmp->start - 1;
0605     }
0606 
0607     printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
0608                     "to [%lx,%lx]\n",
0609             start, end,
0610             (long)new->start, (long)new->end );
0611 
0612     return 0;   /* truncation successful */
0613 }
0614 
0615 /*
0616  * extend_lmmio_len: extend lmmio range to maximum length
0617  *
0618  * This is needed at least on C8000 systems to get the ATI FireGL card
0619  * working. On other systems we will currently not extend the lmmio space.
0620  */
0621 static unsigned long
0622 extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
0623 {
0624     struct resource *tmp;
0625 
0626     /* exit if not a C8000 */
0627     if (boot_cpu_data.cpu_type < mako)
0628         return end;
0629 
0630     pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
0631         end - start, lba_len);
0632 
0633     lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
0634 
0635     pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
0636 
0637 
0638     end += lba_len;
0639     if (end < start) /* fix overflow */
0640         end = -1ULL;
0641 
0642     pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
0643 
0644     /* first overlap */
0645     for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
0646         pr_debug("LBA: testing %pR\n", tmp);
0647         if (tmp->start == start)
0648             continue; /* ignore ourself */
0649         if (tmp->end < start)
0650             continue;
0651         if (tmp->start > end)
0652             continue;
0653         if (end >= tmp->start)
0654             end = tmp->start - 1;
0655     }
0656 
0657     pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
0658 
0659     /* return new end */
0660     return end;
0661 }
0662 
0663 #else
0664 #define truncate_pat_collision(r,n)  (0)
0665 #endif
0666 
0667 static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
0668 {
0669     int idx;
0670     struct resource *r;
0671 
0672     for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
0673         r = &dev->resource[idx];
0674         if (!r->flags)
0675             continue;
0676         if (r->parent)  /* Already allocated */
0677             continue;
0678         if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
0679             /*
0680              * Something is wrong with the region.
0681              * Invalidate the resource to prevent
0682              * child resource allocations in this
0683              * range.
0684              */
0685             r->start = r->end = 0;
0686             r->flags = 0;
0687         }
0688     }
0689 }
0690 
0691 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
0692 {
0693     struct pci_bus *child;
0694 
0695     /* Depth-First Search on bus tree */
0696     if (bus->self)
0697         pcibios_allocate_bridge_resources(bus->self);
0698     list_for_each_entry(child, &bus->children, node)
0699         pcibios_allocate_bus_resources(child);
0700 }
0701 
0702 
0703 /*
0704 ** The algorithm is generic code.
0705 ** But it needs to access local data structures to get the IRQ base.
0706 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
0707 ** it's worth it.
0708 **
0709 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
0710 ** Resources aren't allocated until recursive buswalk below HBA is completed.
0711 */
0712 static void
0713 lba_fixup_bus(struct pci_bus *bus)
0714 {
0715     struct pci_dev *dev;
0716 #ifdef FBB_SUPPORT
0717     u16 status;
0718 #endif
0719     struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
0720 
0721     DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
0722         bus, (int)bus->busn_res.start, bus->bridge->platform_data);
0723 
0724     /*
0725     ** Properly Setup MMIO resources for this bus.
0726     ** pci_alloc_primary_bus() mangles this.
0727     */
0728     if (bus->parent) {
0729         /* PCI-PCI Bridge */
0730         pci_read_bridge_bases(bus);
0731 
0732         /* check and allocate bridge resources */
0733         pcibios_allocate_bus_resources(bus);
0734     } else {
0735         /* Host-PCI Bridge */
0736         int err;
0737 
0738         DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
0739             ldev->hba.io_space.name,
0740             ldev->hba.io_space.start, ldev->hba.io_space.end,
0741             ldev->hba.io_space.flags);
0742         DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
0743             ldev->hba.lmmio_space.name,
0744             ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
0745             ldev->hba.lmmio_space.flags);
0746 
0747         err = request_resource(&ioport_resource, &(ldev->hba.io_space));
0748         if (err < 0) {
0749             lba_dump_res(&ioport_resource, 2);
0750             BUG();
0751         }
0752 
0753         if (ldev->hba.elmmio_space.flags) {
0754             err = request_resource(&iomem_resource,
0755                     &(ldev->hba.elmmio_space));
0756             if (err < 0) {
0757 
0758                 printk("FAILED: lba_fixup_bus() request for "
0759                         "elmmio_space [%lx/%lx]\n",
0760                         (long)ldev->hba.elmmio_space.start,
0761                         (long)ldev->hba.elmmio_space.end);
0762 
0763                 /* lba_dump_res(&iomem_resource, 2); */
0764                 /* BUG(); */
0765             }
0766         }
0767 
0768         if (ldev->hba.lmmio_space.flags) {
0769             err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
0770             if (err < 0) {
0771                 printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
0772                     "lmmio_space [%lx/%lx]\n",
0773                     (long)ldev->hba.lmmio_space.start,
0774                     (long)ldev->hba.lmmio_space.end);
0775             }
0776         }
0777 
0778 #ifdef CONFIG_64BIT
0779         /* GMMIO is  distributed range. Every LBA/Rope gets part it. */
0780         if (ldev->hba.gmmio_space.flags) {
0781             err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
0782             if (err < 0) {
0783                 printk("FAILED: lba_fixup_bus() request for "
0784                     "gmmio_space [%lx/%lx]\n",
0785                     (long)ldev->hba.gmmio_space.start,
0786                     (long)ldev->hba.gmmio_space.end);
0787                 lba_dump_res(&iomem_resource, 2);
0788                 BUG();
0789             }
0790         }
0791 #endif
0792 
0793     }
0794 
0795     list_for_each_entry(dev, &bus->devices, bus_list) {
0796         int i;
0797 
0798         DBG("lba_fixup_bus() %s\n", pci_name(dev));
0799 
0800         /* Virtualize Device/Bridge Resources. */
0801         for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
0802             struct resource *res = &dev->resource[i];
0803 
0804             /* If resource not allocated - skip it */
0805             if (!res->start)
0806                 continue;
0807 
0808             /*
0809             ** FIXME: this will result in whinging for devices
0810             ** that share expansion ROMs (think quad tulip), but
0811             ** isn't harmful.
0812             */
0813             pci_claim_resource(dev, i);
0814         }
0815 
0816 #ifdef FBB_SUPPORT
0817         /*
0818         ** If one device does not support FBB transfers,
0819         ** No one on the bus can be allowed to use them.
0820         */
0821         (void) pci_read_config_word(dev, PCI_STATUS, &status);
0822         bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
0823 #endif
0824 
0825                 /*
0826         ** P2PB's have no IRQs. ignore them.
0827         */
0828         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
0829             pcibios_init_bridge(dev);
0830             continue;
0831         }
0832 
0833         /* Adjust INTERRUPT_LINE for this dev */
0834         iosapic_fixup_irq(ldev->iosapic_obj, dev);
0835     }
0836 
0837 #ifdef FBB_SUPPORT
0838 /* FIXME/REVISIT - finish figuring out to set FBB on both
0839 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
0840 ** Can't fixup here anyway....garr...
0841 */
0842     if (fbb_enable) {
0843         if (bus->parent) {
0844             u8 control;
0845             /* enable on PPB */
0846             (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
0847             (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
0848 
0849         } else {
0850             /* enable on LBA */
0851         }
0852         fbb_enable = PCI_COMMAND_FAST_BACK;
0853     }
0854 
0855     /* Lastly enable FBB/PERR/SERR on all devices too */
0856     list_for_each_entry(dev, &bus->devices, bus_list) {
0857         (void) pci_read_config_word(dev, PCI_COMMAND, &status);
0858         status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
0859         (void) pci_write_config_word(dev, PCI_COMMAND, status);
0860     }
0861 #endif
0862 }
0863 
0864 
0865 static struct pci_bios_ops lba_bios_ops = {
0866     .init =     lba_bios_init,
0867     .fixup_bus =    lba_fixup_bus,
0868 };
0869 
0870 
0871 
0872 
0873 /*******************************************************
0874 **
0875 ** LBA Sprockets "I/O Port" Space Accessor Functions
0876 **
0877 ** This set of accessor functions is intended for use with
0878 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
0879 **
0880 ** Many PCI devices don't require use of I/O port space (eg Tulip,
0881 ** NCR720) since they export the same registers to both MMIO and
0882 ** I/O port space. In general I/O port space is slower than
0883 ** MMIO since drivers are designed so PIO writes can be posted.
0884 **
0885 ********************************************************/
0886 
0887 #define LBA_PORT_IN(size, mask) \
0888 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
0889 { \
0890     u##size t; \
0891     t = READ_REG##size(astro_iop_base + addr); \
0892     DBG_PORT(" 0x%x\n", t); \
0893     return (t); \
0894 }
0895 
0896 LBA_PORT_IN( 8, 3)
0897 LBA_PORT_IN(16, 2)
0898 LBA_PORT_IN(32, 0)
0899 
0900 
0901 
0902 /*
0903 ** BUG X4107:  Ordering broken - DMA RD return can bypass PIO WR
0904 **
0905 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
0906 ** guarantee non-postable completion semantics - not avoid X4107.
0907 ** The READ_U32 only guarantees the write data gets to elroy but
0908 ** out to the PCI bus. We can't read stuff from I/O port space
0909 ** since we don't know what has side-effects. Attempting to read
0910 ** from configuration space would be suicidal given the number of
0911 ** bugs in that elroy functionality.
0912 **
0913 **      Description:
0914 **          DMA read results can improperly pass PIO writes (X4107).  The
0915 **          result of this bug is that if a processor modifies a location in
0916 **          memory after having issued PIO writes, the PIO writes are not
0917 **          guaranteed to be completed before a PCI device is allowed to see
0918 **          the modified data in a DMA read.
0919 **
0920 **          Note that IKE bug X3719 in TR1 IKEs will result in the same
0921 **          symptom.
0922 **
0923 **      Workaround:
0924 **          The workaround for this bug is to always follow a PIO write with
0925 **          a PIO read to the same bus before starting DMA on that PCI bus.
0926 **
0927 */
0928 #define LBA_PORT_OUT(size, mask) \
0929 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
0930 { \
0931     DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
0932     WRITE_REG##size(val, astro_iop_base + addr); \
0933     if (LBA_DEV(d)->hw_rev < 3) \
0934         lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
0935 }
0936 
0937 LBA_PORT_OUT( 8, 3)
0938 LBA_PORT_OUT(16, 2)
0939 LBA_PORT_OUT(32, 0)
0940 
0941 
0942 static struct pci_port_ops lba_astro_port_ops = {
0943     .inb =  lba_astro_in8,
0944     .inw =  lba_astro_in16,
0945     .inl =  lba_astro_in32,
0946     .outb = lba_astro_out8,
0947     .outw = lba_astro_out16,
0948     .outl = lba_astro_out32
0949 };
0950 
0951 
0952 #ifdef CONFIG_64BIT
0953 #define PIOP_TO_GMMIO(lba, addr) \
0954     ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
0955 
0956 /*******************************************************
0957 **
0958 ** LBA PAT "I/O Port" Space Accessor Functions
0959 **
0960 ** This set of accessor functions is intended for use with
0961 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
0962 **
0963 ** This uses the PIOP space located in the first 64MB of GMMIO.
0964 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
0965 ** bits 1:0 stay the same.  bits 15:2 become 25:12.
0966 ** Then add the base and we can generate an I/O Port cycle.
0967 ********************************************************/
0968 #undef LBA_PORT_IN
0969 #define LBA_PORT_IN(size, mask) \
0970 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
0971 { \
0972     u##size t; \
0973     DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
0974     t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
0975     DBG_PORT(" 0x%x\n", t); \
0976     return (t); \
0977 }
0978 
0979 LBA_PORT_IN( 8, 3)
0980 LBA_PORT_IN(16, 2)
0981 LBA_PORT_IN(32, 0)
0982 
0983 
0984 #undef LBA_PORT_OUT
0985 #define LBA_PORT_OUT(size, mask) \
0986 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
0987 { \
0988     void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
0989     DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
0990     WRITE_REG##size(val, where); \
0991     /* flush the I/O down to the elroy at least */ \
0992     lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
0993 }
0994 
0995 LBA_PORT_OUT( 8, 3)
0996 LBA_PORT_OUT(16, 2)
0997 LBA_PORT_OUT(32, 0)
0998 
0999 
1000 static struct pci_port_ops lba_pat_port_ops = {
1001     .inb =  lba_pat_in8,
1002     .inw =  lba_pat_in16,
1003     .inl =  lba_pat_in32,
1004     .outb = lba_pat_out8,
1005     .outw = lba_pat_out16,
1006     .outl = lba_pat_out32
1007 };
1008 
1009 
1010 
1011 /*
1012 ** make range information from PDC available to PCI subsystem.
1013 ** We make the PDC call here in order to get the PCI bus range
1014 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
1015 ** We don't have a struct pci_bus assigned to us yet.
1016 */
1017 static void
1018 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1019 {
1020     unsigned long bytecnt;
1021     long io_count;
1022     long status;    /* PDC return status */
1023     long pa_count;
1024     pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell;    /* PA_VIEW */
1025     pdc_pat_cell_mod_maddr_block_t *io_pdc_cell;    /* IO_VIEW */
1026     int i;
1027 
1028     pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
1029     if (!pa_pdc_cell)
1030         return;
1031 
1032     io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
1033     if (!io_pdc_cell) {
1034         kfree(pa_pdc_cell);
1035         return;
1036     }
1037 
1038     /* return cell module (IO view) */
1039     status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1040                 PA_VIEW, pa_pdc_cell);
1041     pa_count = pa_pdc_cell->mod[1];
1042 
1043     status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1044                 IO_VIEW, io_pdc_cell);
1045     io_count = io_pdc_cell->mod[1];
1046 
1047     /* We've already done this once for device discovery...*/
1048     if (status != PDC_OK) {
1049         panic("pdc_pat_cell_module() call failed for LBA!\n");
1050     }
1051 
1052     if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) {
1053         panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1054     }
1055 
1056     /*
1057     ** Inspect the resources PAT tells us about
1058     */
1059     for (i = 0; i < pa_count; i++) {
1060         struct {
1061             unsigned long type;
1062             unsigned long start;
1063             unsigned long end;  /* aka finish */
1064         } *p, *io;
1065         struct resource *r;
1066 
1067         p = (void *) &(pa_pdc_cell->mod[2+i*3]);
1068         io = (void *) &(io_pdc_cell->mod[2+i*3]);
1069 
1070         /* Convert the PAT range data to PCI "struct resource" */
1071         switch(p->type & 0xff) {
1072         case PAT_PBNUM:
1073             lba_dev->hba.bus_num.start = p->start;
1074             lba_dev->hba.bus_num.end   = p->end;
1075             lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
1076             break;
1077 
1078         case PAT_LMMIO:
1079             /* used to fix up pre-initialized MEM BARs */
1080             if (!lba_dev->hba.lmmio_space.flags) {
1081                 unsigned long lba_len;
1082 
1083                 lba_len = ~READ_REG32(lba_dev->hba.base_addr
1084                         + LBA_LMMIO_MASK);
1085                 if ((p->end - p->start) != lba_len)
1086                     p->end = extend_lmmio_len(p->start,
1087                         p->end, lba_len);
1088 
1089                 sprintf(lba_dev->hba.lmmio_name,
1090                         "PCI%02x LMMIO",
1091                         (int)lba_dev->hba.bus_num.start);
1092                 lba_dev->hba.lmmio_space_offset = p->start -
1093                     io->start;
1094                 r = &lba_dev->hba.lmmio_space;
1095                 r->name = lba_dev->hba.lmmio_name;
1096             } else if (!lba_dev->hba.elmmio_space.flags) {
1097                 sprintf(lba_dev->hba.elmmio_name,
1098                         "PCI%02x ELMMIO",
1099                         (int)lba_dev->hba.bus_num.start);
1100                 r = &lba_dev->hba.elmmio_space;
1101                 r->name = lba_dev->hba.elmmio_name;
1102             } else {
1103                 printk(KERN_WARNING MODULE_NAME
1104                     " only supports 2 LMMIO resources!\n");
1105                 break;
1106             }
1107 
1108             r->start  = p->start;
1109             r->end    = p->end;
1110             r->flags  = IORESOURCE_MEM;
1111             r->parent = r->sibling = r->child = NULL;
1112             break;
1113 
1114         case PAT_GMMIO:
1115             /* MMIO space > 4GB phys addr; for 64-bit BAR */
1116             sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1117                     (int)lba_dev->hba.bus_num.start);
1118             r = &lba_dev->hba.gmmio_space;
1119             r->name  = lba_dev->hba.gmmio_name;
1120             r->start  = p->start;
1121             r->end    = p->end;
1122             r->flags  = IORESOURCE_MEM;
1123             r->parent = r->sibling = r->child = NULL;
1124             break;
1125 
1126         case PAT_NPIOP:
1127             printk(KERN_WARNING MODULE_NAME
1128                 " range[%d] : ignoring NPIOP (0x%lx)\n",
1129                 i, p->start);
1130             break;
1131 
1132         case PAT_PIOP:
1133             /*
1134             ** Postable I/O port space is per PCI host adapter.
1135             ** base of 64MB PIOP region
1136             */
1137             lba_dev->iop_base = ioremap(p->start, 64 * 1024 * 1024);
1138 
1139             sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1140                     (int)lba_dev->hba.bus_num.start);
1141             r = &lba_dev->hba.io_space;
1142             r->name  = lba_dev->hba.io_name;
1143             r->start  = HBA_PORT_BASE(lba_dev->hba.hba_num);
1144             r->end    = r->start + HBA_PORT_SPACE_SIZE - 1;
1145             r->flags  = IORESOURCE_IO;
1146             r->parent = r->sibling = r->child = NULL;
1147             break;
1148 
1149         default:
1150             printk(KERN_WARNING MODULE_NAME
1151                 " range[%d] : unknown pat range type (0x%lx)\n",
1152                 i, p->type & 0xff);
1153             break;
1154         }
1155     }
1156 
1157     kfree(pa_pdc_cell);
1158     kfree(io_pdc_cell);
1159 }
1160 #else
1161 /* keep compiler from complaining about missing declarations */
1162 #define lba_pat_port_ops lba_astro_port_ops
1163 #define lba_pat_resources(pa_dev, lba_dev)
1164 #endif  /* CONFIG_64BIT */
1165 
1166 
1167 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1168 extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1169 
1170 
1171 static void
1172 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1173 {
1174     struct resource *r;
1175     int lba_num;
1176 
1177     lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1178 
1179     /*
1180     ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1181     ** represents bus->secondary and the second byte represents
1182     ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1183     ** PCI bus walk *should* end up with the same result.
1184     ** FIXME: But we don't have sanity checks in PCI or LBA.
1185     */
1186     lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1187     r = &(lba_dev->hba.bus_num);
1188     r->name = "LBA PCI Busses";
1189     r->start = lba_num & 0xff;
1190     r->end = (lba_num>>8) & 0xff;
1191     r->flags = IORESOURCE_BUS;
1192 
1193     /* Set up local PCI Bus resources - we don't need them for
1194     ** Legacy boxes but it's nice to see in /proc/iomem.
1195     */
1196     r = &(lba_dev->hba.lmmio_space);
1197     sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1198                     (int)lba_dev->hba.bus_num.start);
1199     r->name  = lba_dev->hba.lmmio_name;
1200 
1201 #if 1
1202     /* We want the CPU -> IO routing of addresses.
1203      * The SBA BASE/MASK registers control CPU -> IO routing.
1204      * Ask SBA what is routed to this rope/LBA.
1205      */
1206     sba_distributed_lmmio(pa_dev, r);
1207 #else
1208     /*
1209      * The LBA BASE/MASK registers control IO -> System routing.
1210      *
1211      * The following code works but doesn't get us what we want.
1212      * Well, only because firmware (v5.0) on C3000 doesn't program
1213      * the LBA BASE/MASE registers to be the exact inverse of 
1214      * the corresponding SBA registers. Other Astro/Pluto
1215      * based platform firmware may do it right.
1216      *
1217      * Should someone want to mess with MSI, they may need to
1218      * reprogram LBA BASE/MASK registers. Thus preserve the code
1219      * below until MSI is known to work on C3000/A500/N4000/RP3440.
1220      *
1221      * Using the code below, /proc/iomem shows:
1222      * ...
1223      * f0000000-f0ffffff : PCI00 LMMIO
1224      *   f05d0000-f05d0000 : lcd_data
1225      *   f05d0008-f05d0008 : lcd_cmd
1226      * f1000000-f1ffffff : PCI01 LMMIO
1227      * f4000000-f4ffffff : PCI02 LMMIO
1228      *   f4000000-f4001fff : sym53c8xx
1229      *   f4002000-f4003fff : sym53c8xx
1230      *   f4004000-f40043ff : sym53c8xx
1231      *   f4005000-f40053ff : sym53c8xx
1232      *   f4007000-f4007fff : ohci_hcd
1233      *   f4008000-f40083ff : tulip
1234      * f6000000-f6ffffff : PCI03 LMMIO
1235      * f8000000-fbffffff : PCI00 ELMMIO
1236      *   fa100000-fa4fffff : stifb mmio
1237      *   fb000000-fb1fffff : stifb fb
1238      *
1239      * But everything listed under PCI02 actually lives under PCI00.
1240      * This is clearly wrong.
1241      *
1242      * Asking SBA how things are routed tells the correct story:
1243      * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1244      * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1245      * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1246      * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1247      * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1248      *
1249      * Which looks like this in /proc/iomem:
1250      * f4000000-f47fffff : PCI00 LMMIO
1251      *   f4000000-f4001fff : sym53c8xx
1252      *   ...[deteled core devices - same as above]...
1253      *   f4008000-f40083ff : tulip
1254      * f4800000-f4ffffff : PCI01 LMMIO
1255      * f6000000-f67fffff : PCI02 LMMIO
1256      * f7000000-f77fffff : PCI03 LMMIO
1257      * f9000000-f9ffffff : PCI02 ELMMIO
1258      * fa000000-fbffffff : PCI03 ELMMIO
1259      *   fa100000-fa4fffff : stifb mmio
1260      *   fb000000-fb1fffff : stifb fb
1261      *
1262      * ie all Built-in core are under now correctly under PCI00.
1263      * The "PCI02 ELMMIO" directed range is for:
1264      *  +-[02]---03.0  3Dfx Interactive, Inc. Voodoo 2
1265      *
1266      * All is well now.
1267      */
1268     r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1269     if (r->start & 1) {
1270         unsigned long rsize;
1271 
1272         r->flags = IORESOURCE_MEM;
1273         /* mmio_mask also clears Enable bit */
1274         r->start &= mmio_mask;
1275         r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
1276         rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1277 
1278         /*
1279         ** Each rope only gets part of the distributed range.
1280         ** Adjust "window" for this rope.
1281         */
1282         rsize /= ROPES_PER_IOC;
1283         r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
1284         r->end = r->start + rsize;
1285     } else {
1286         r->end = r->start = 0;  /* Not enabled. */
1287     }
1288 #endif
1289 
1290     /*
1291     ** "Directed" ranges are used when the "distributed range" isn't
1292     ** sufficient for all devices below a given LBA.  Typically devices
1293     ** like graphics cards or X25 may need a directed range when the
1294     ** bus has multiple slots (ie multiple devices) or the device
1295     ** needs more than the typical 4 or 8MB a distributed range offers.
1296     **
1297     ** The main reason for ignoring it now frigging complications.
1298     ** Directed ranges may overlap (and have precedence) over
1299     ** distributed ranges. Or a distributed range assigned to a unused
1300     ** rope may be used by a directed range on a different rope.
1301     ** Support for graphics devices may require fixing this
1302     ** since they may be assigned a directed range which overlaps
1303     ** an existing (but unused portion of) distributed range.
1304     */
1305     r = &(lba_dev->hba.elmmio_space);
1306     sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1307                     (int)lba_dev->hba.bus_num.start);
1308     r->name  = lba_dev->hba.elmmio_name;
1309 
1310 #if 1
1311     /* See comment which precedes call to sba_directed_lmmio() */
1312     sba_directed_lmmio(pa_dev, r);
1313 #else
1314     r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1315 
1316     if (r->start & 1) {
1317         unsigned long rsize;
1318         r->flags = IORESOURCE_MEM;
1319         /* mmio_mask also clears Enable bit */
1320         r->start &= mmio_mask;
1321         r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
1322         rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1323         r->end = r->start + ~rsize;
1324     }
1325 #endif
1326 
1327     r = &(lba_dev->hba.io_space);
1328     sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1329                     (int)lba_dev->hba.bus_num.start);
1330     r->name  = lba_dev->hba.io_name;
1331     r->flags = IORESOURCE_IO;
1332     r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1333     r->end   = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1334 
1335     /* Virtualize the I/O Port space ranges */
1336     lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1337     r->start |= lba_num;
1338     r->end   |= lba_num;
1339 }
1340 
1341 
1342 /**************************************************************************
1343 **
1344 **   LBA initialization code (HW and SW)
1345 **
1346 **   o identify LBA chip itself
1347 **   o initialize LBA chip modes (HardFail)
1348 **   o FIXME: initialize DMA hints for reasonable defaults
1349 **   o enable configuration functions
1350 **   o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1351 **
1352 **************************************************************************/
1353 
1354 static int __init
1355 lba_hw_init(struct lba_device *d)
1356 {
1357     u32 stat;
1358     u32 bus_reset;  /* PDC_PAT_BUG */
1359 
1360 #if 0
1361     printk(KERN_DEBUG "LBA %lx  STAT_CTL %Lx  ERROR_CFG %Lx  STATUS %Lx DMA_CTL %Lx\n",
1362         d->hba.base_addr,
1363         READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1364         READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1365         READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1366         READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1367     printk(KERN_DEBUG " ARB mask %Lx  pri %Lx  mode %Lx  mtlt %Lx\n",
1368         READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1369         READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1370         READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1371         READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1372     printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1373         READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1374     printk(KERN_DEBUG " HINT reg ");
1375     { int i;
1376     for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1377         printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1378     }
1379     printk("\n");
1380 #endif  /* DEBUG_LBA_PAT */
1381 
1382 #ifdef CONFIG_64BIT
1383 /*
1384  * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1385  * Only N-Class and up can really make use of Get slot status.
1386  * maybe L-class too but I've never played with it there.
1387  */
1388 #endif
1389 
1390     /* PDC_PAT_BUG: exhibited in rev 40.48  on L2000 */
1391     bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1392     if (bus_reset) {
1393         printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1394     }
1395 
1396     stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1397     if (stat & LBA_SMART_MODE) {
1398         printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1399         stat &= ~LBA_SMART_MODE;
1400         WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1401     }
1402 
1403 
1404     /*
1405      * Hard Fail vs. Soft Fail on PCI "Master Abort".
1406      *
1407      * "Master Abort" means the MMIO transaction timed out - usually due to
1408      * the device not responding to an MMIO read. We would like HF to be
1409      * enabled to find driver problems, though it means the system will
1410      * crash with a HPMC.
1411      *
1412      * In SoftFail mode "~0L" is returned as a result of a timeout on the
1413      * pci bus. This is like how PCI busses on x86 and most other
1414      * architectures behave.  In order to increase compatibility with
1415      * existing (x86) PCI hardware and existing Linux drivers we enable
1416      * Soft Faul mode on PA-RISC now too.
1417      */
1418         stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1419 #if defined(ENABLE_HARDFAIL)
1420     WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1421 #else
1422     WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1423 #endif
1424 
1425     /*
1426     ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1427     ** if it's not already set. If we just cleared the PCI Bus Reset
1428     ** signal, wait a bit for the PCI devices to recover and setup.
1429     */
1430     if (bus_reset)
1431         mdelay(pci_post_reset_delay);
1432 
1433     if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1434         /*
1435         ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1436         ** B2000/C3600/J6000 also have this problem?
1437         ** 
1438         ** Elroys with hot pluggable slots don't get configured
1439         ** correctly if the slot is empty.  ARB_MASK is set to 0
1440         ** and we can't master transactions on the bus if it's
1441         ** not at least one. 0x3 enables elroy and first slot.
1442         */
1443         printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1444         WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1445     }
1446 
1447     /*
1448     ** FIXME: Hint registers are programmed with default hint
1449     ** values by firmware. Hints should be sane even if we
1450     ** can't reprogram them the way drivers want.
1451     */
1452     return 0;
1453 }
1454 
1455 /*
1456  * Unfortunately, when firmware numbers busses, it doesn't take into account
1457  * Cardbus bridges.  So we have to renumber the busses to suit ourselves.
1458  * Elroy/Mercury don't actually know what bus number they're attached to;
1459  * we use bus 0 to indicate the directly attached bus and any other bus
1460  * number will be taken care of by the PCI-PCI bridge.
1461  */
1462 static unsigned int lba_next_bus = 0;
1463 
1464 /*
1465  * Determine if lba should claim this chip (return 0) or not (return 1).
1466  * If so, initialize the chip and tell other partners in crime they
1467  * have work to do.
1468  */
1469 static int __init
1470 lba_driver_probe(struct parisc_device *dev)
1471 {
1472     struct lba_device *lba_dev;
1473     LIST_HEAD(resources);
1474     struct pci_bus *lba_bus;
1475     struct pci_ops *cfg_ops;
1476     u32 func_class;
1477     void *tmp_obj;
1478     char *version;
1479     void __iomem *addr;
1480     int max;
1481 
1482     addr = ioremap(dev->hpa.start, 4096);
1483     if (addr == NULL)
1484         return -ENOMEM;
1485 
1486     /* Read HW Rev First */
1487     func_class = READ_REG32(addr + LBA_FCLASS);
1488 
1489     if (IS_ELROY(dev)) {    
1490         func_class &= 0xf;
1491         switch (func_class) {
1492         case 0: version = "TR1.0"; break;
1493         case 1: version = "TR2.0"; break;
1494         case 2: version = "TR2.1"; break;
1495         case 3: version = "TR2.2"; break;
1496         case 4: version = "TR3.0"; break;
1497         case 5: version = "TR4.0"; break;
1498         default: version = "TR4+";
1499         }
1500 
1501         printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
1502                version, func_class & 0xf, (long)dev->hpa.start);
1503 
1504         if (func_class < 2) {
1505             printk(KERN_WARNING "Can't support LBA older than "
1506                 "TR2.1 - continuing under adversity.\n");
1507         }
1508 
1509 #if 0
1510 /* Elroy TR4.0 should work with simple algorithm.
1511    But it doesn't.  Still missing something. *sigh*
1512 */
1513         if (func_class > 4) {
1514             cfg_ops = &mercury_cfg_ops;
1515         } else
1516 #endif
1517         {
1518             cfg_ops = &elroy_cfg_ops;
1519         }
1520 
1521     } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1522         int major, minor;
1523 
1524         func_class &= 0xff;
1525         major = func_class >> 4, minor = func_class & 0xf;
1526 
1527         /* We could use one printk for both Elroy and Mercury,
1528                  * but for the mask for func_class.
1529                  */ 
1530         printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
1531                IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
1532                minor, func_class, (long)dev->hpa.start);
1533 
1534         cfg_ops = &mercury_cfg_ops;
1535     } else {
1536         printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
1537             (long)dev->hpa.start);
1538         return -ENODEV;
1539     }
1540 
1541     /* Tell I/O SAPIC driver we have a IRQ handler/region. */
1542     tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
1543 
1544     /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1545     **  have an IRT entry will get NULL back from iosapic code.
1546     */
1547     
1548     lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
1549     if (!lba_dev) {
1550         printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1551         return(1);
1552     }
1553 
1554 
1555     /* ---------- First : initialize data we already have --------- */
1556 
1557     lba_dev->hw_rev = func_class;
1558     lba_dev->hba.base_addr = addr;
1559     lba_dev->hba.dev = dev;
1560     lba_dev->iosapic_obj = tmp_obj;  /* save interrupt handle */
1561     lba_dev->hba.iommu = sba_get_iommu(dev);  /* get iommu data */
1562     parisc_set_drvdata(dev, lba_dev);
1563 
1564     /* ------------ Second : initialize common stuff ---------- */
1565     pci_bios = &lba_bios_ops;
1566     pcibios_register_hba(&lba_dev->hba);
1567     spin_lock_init(&lba_dev->lba_lock);
1568 
1569     if (lba_hw_init(lba_dev))
1570         return(1);
1571 
1572     /* ---------- Third : setup I/O Port and MMIO resources  --------- */
1573 
1574     if (is_pdc_pat()) {
1575         /* PDC PAT firmware uses PIOP region of GMMIO space. */
1576         pci_port = &lba_pat_port_ops;
1577         /* Go ask PDC PAT what resources this LBA has */
1578         lba_pat_resources(dev, lba_dev);
1579     } else {
1580         if (!astro_iop_base) {
1581             /* Sprockets PDC uses NPIOP region */
1582             astro_iop_base = ioremap(LBA_PORT_BASE, 64 * 1024);
1583             pci_port = &lba_astro_port_ops;
1584         }
1585 
1586         /* Poke the chip a bit for /proc output */
1587         lba_legacy_resources(dev, lba_dev);
1588     }
1589 
1590     if (lba_dev->hba.bus_num.start < lba_next_bus)
1591         lba_dev->hba.bus_num.start = lba_next_bus;
1592 
1593     /*   Overlaps with elmmio can (and should) fail here.
1594      *   We will prune (or ignore) the distributed range.
1595      *
1596      *   FIXME: SBA code should register all elmmio ranges first.
1597      *      that would take care of elmmio ranges routed
1598      *  to a different rope (already discovered) from
1599      *  getting registered *after* LBA code has already
1600      *  registered it's distributed lmmio range.
1601      */
1602     if (truncate_pat_collision(&iomem_resource,
1603                    &(lba_dev->hba.lmmio_space))) {
1604         printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
1605                 (long)lba_dev->hba.lmmio_space.start,
1606                 (long)lba_dev->hba.lmmio_space.end);
1607         lba_dev->hba.lmmio_space.flags = 0;
1608     }
1609 
1610     pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
1611                 HBA_PORT_BASE(lba_dev->hba.hba_num));
1612     if (lba_dev->hba.elmmio_space.flags)
1613         pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
1614                     lba_dev->hba.lmmio_space_offset);
1615     if (lba_dev->hba.lmmio_space.flags)
1616         pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
1617                     lba_dev->hba.lmmio_space_offset);
1618     if (lba_dev->hba.gmmio_space.flags) {
1619         /* Not registering GMMIO space - according to docs it's not
1620          * even used on HP-UX. */
1621         /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */
1622     }
1623 
1624     pci_add_resource(&resources, &lba_dev->hba.bus_num);
1625 
1626     dev->dev.platform_data = lba_dev;
1627     lba_bus = lba_dev->hba.hba_bus =
1628         pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
1629                     cfg_ops, NULL, &resources);
1630     if (!lba_bus) {
1631         pci_free_resource_list(&resources);
1632         return 0;
1633     }
1634 
1635     max = pci_scan_child_bus(lba_bus);
1636 
1637     /* This is in lieu of calling pci_assign_unassigned_resources() */
1638     if (is_pdc_pat()) {
1639         /* assign resources to un-initialized devices */
1640 
1641         DBG_PAT("LBA pci_bus_size_bridges()\n");
1642         pci_bus_size_bridges(lba_bus);
1643 
1644         DBG_PAT("LBA pci_bus_assign_resources()\n");
1645         pci_bus_assign_resources(lba_bus);
1646 
1647 #ifdef DEBUG_LBA_PAT
1648         DBG_PAT("\nLBA PIOP resource tree\n");
1649         lba_dump_res(&lba_dev->hba.io_space, 2);
1650         DBG_PAT("\nLBA LMMIO resource tree\n");
1651         lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1652 #endif
1653     }
1654 
1655     /*
1656     ** Once PCI register ops has walked the bus, access to config
1657     ** space is restricted. Avoids master aborts on config cycles.
1658     ** Early LBA revs go fatal on *any* master abort.
1659     */
1660     if (cfg_ops == &elroy_cfg_ops) {
1661         lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1662     }
1663 
1664     lba_next_bus = max + 1;
1665     pci_bus_add_devices(lba_bus);
1666 
1667     /* Whew! Finally done! Tell services we got this one covered. */
1668     return 0;
1669 }
1670 
1671 static const struct parisc_device_id lba_tbl[] __initconst = {
1672     { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1673     { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1674     { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1675     { 0, }
1676 };
1677 
1678 static struct parisc_driver lba_driver __refdata = {
1679     .name =     MODULE_NAME,
1680     .id_table = lba_tbl,
1681     .probe =    lba_driver_probe,
1682 };
1683 
1684 /*
1685 ** One time initialization to let the world know the LBA was found.
1686 ** Must be called exactly once before pci_init().
1687 */
1688 void __init lba_init(void)
1689 {
1690     register_parisc_driver(&lba_driver);
1691 }
1692 
1693 /*
1694 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1695 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1696 ** sba_iommu is responsible for locking (none needed at init time).
1697 */
1698 void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1699 {
1700     void __iomem * base_addr = ioremap(lba->hpa.start, 4096);
1701 
1702     imask <<= 2;    /* adjust for hints - 2 more bits */
1703 
1704     /* Make sure we aren't trying to set bits that aren't writeable. */
1705     WARN_ON((ibase & 0x001fffff) != 0);
1706     WARN_ON((imask & 0x001fffff) != 0);
1707     
1708     DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask);
1709     WRITE_REG32( imask, base_addr + LBA_IMASK);
1710     WRITE_REG32( ibase, base_addr + LBA_IBASE);
1711     iounmap(base_addr);
1712 }
1713 
1714 
1715 /*
1716  * The design of the Diva management card in rp34x0 machines (rp3410, rp3440)
1717  * seems rushed, so that many built-in components simply don't work.
1718  * The following quirks disable the serial AUX port and the built-in ATI RV100
1719  * Radeon 7000 graphics card which both don't have any external connectors and
1720  * thus are useless, and even worse, e.g. the AUX port occupies ttyS0 and as
1721  * such makes those machines the only PARISC machines on which we can't use
1722  * ttyS0 as boot console.
1723  */
1724 static void quirk_diva_ati_card(struct pci_dev *dev)
1725 {
1726     if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
1727         dev->subsystem_device != 0x1292)
1728         return;
1729 
1730     dev_info(&dev->dev, "Hiding Diva built-in ATI card");
1731     dev->device = 0;
1732 }
1733 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY,
1734     quirk_diva_ati_card);
1735 
1736 static void quirk_diva_aux_disable(struct pci_dev *dev)
1737 {
1738     if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
1739         dev->subsystem_device != 0x1291)
1740         return;
1741 
1742     dev_info(&dev->dev, "Hiding Diva built-in AUX serial device");
1743     dev->device = 0;
1744 }
1745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
1746     quirk_diva_aux_disable);
1747 
1748 static void quirk_tosca_aux_disable(struct pci_dev *dev)
1749 {
1750     if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
1751         dev->subsystem_device != 0x104a)
1752         return;
1753 
1754     dev_info(&dev->dev, "Hiding Tosca secondary built-in AUX serial device");
1755     dev->device = 0;
1756 }
1757 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
1758     quirk_tosca_aux_disable);
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