drivers/parisc/iosapic_private.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *    Private structs/constants for PARISC IOSAPIC support
0004  *
0005  *    Copyright (C) 2000 Hewlett Packard (Grant Grundler)
0006  *    Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
0007  *    Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
0008  */
0009
0010 /*
0011 ** This file is private to iosapic driver.
0012 ** If stuff needs to be used by another driver, move it to a common file.
0013 **
0014 ** WARNING: fields most data structures here are ordered to make sure
0015 **          they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
0016 */
0017
0018
0019 /*
0020 ** Interrupt Routing Stuff
0021 ** -----------------------
0022 ** The interrupt routing table consists of entries derived from
0023 ** MP Specification Draft 1.5. There is one interrupt routing
0024 ** table per cell.  N- and L-class consist of a single cell.
0025 */
0026 struct irt_entry {
0027
0028     /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
0029     u8 entry_type;
0030
0031     /* Entry Length 16 indicates entry is 16 bytes long */
0032     u8 entry_length;
0033
0034     /*
0035     ** Interrupt Type of 0 indicates a vectored interrupt,
0036     ** all other values are reserved
0037     */
0038     u8 interrupt_type;
0039
0040     /*
0041     ** PO and EL
0042     ** Polarity of SAPIC I/O input signals:
0043     **    00 = Reserved
0044     **    01 = Active high
0045     **    10 = Reserved
0046     **    11 = Active low
0047     ** Trigger mode of SAPIC I/O input signals:
0048     **    00 = Reserved
0049     **    01 = Edge-triggered
0050     **    10 = Reserved
0051     **    11 = Level-triggered
0052     */
0053     u8 polarity_trigger;
0054
0055     /*
0056     ** IRQ and DEVNO
0057     ** irq identifies PCI interrupt signal where
0058     **    0x0 corresponds to INT_A#,
0059     **    0x1 corresponds to INT_B#,
0060     **    0x2 corresponds to INT_C#
0061     **    0x3 corresponds to INT_D#
0062     ** PCI device number where interrupt originates
0063     */
0064     u8 src_bus_irq_devno;
0065
0066     /* Source Bus ID identifies the bus where interrupt signal comes from */
0067     u8 src_bus_id;
0068
0069     /*
0070     ** Segment ID is unique across a protection domain and
0071     ** identifies a segment of PCI buses (reserved in
0072     ** MP Specification Draft 1.5)
0073     */
0074     u8 src_seg_id;
0075
0076     /*
0077     ** Destination I/O SAPIC INTIN# identifies the INTIN n pin
0078     ** to which the signal is connected
0079     */
0080     u8 dest_iosapic_intin;
0081
0082     /*
0083     ** Destination I/O SAPIC Address identifies the I/O SAPIC
0084     ** to which the signal is connected
0085     */
0086     u64 dest_iosapic_addr;
0087 };
0088
0089 #define IRT_IOSAPIC_TYPE   139
0090 #define IRT_IOSAPIC_LENGTH 16
0091
0092 #define IRT_VECTORED_INTR  0
0093
0094 #define IRT_PO_MASK        0x3
0095 #define IRT_ACTIVE_HI      1
0096 #define IRT_ACTIVE_LO      3
0097
0098 #define IRT_EL_MASK        0x3
0099 #define IRT_EL_SHIFT       2
0100 #define IRT_EDGE_TRIG      1
0101 #define IRT_LEVEL_TRIG     3
0102
0103 #define IRT_IRQ_MASK       0x3
0104 #define IRT_DEV_MASK       0x1f
0105 #define IRT_DEV_SHIFT      2
0106
0107 #define IRT_IRQ_DEVNO_MASK  ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK)
0108
0109 #ifdef SUPPORT_MULTI_CELL
0110 struct iosapic_irt {
0111         struct iosapic_irt *irt_next;  /* next routing table */
0112         struct irt_entry *irt_base;             /* intr routing table address */
0113         size_t  irte_count;            /* number of entries in the table */
0114         size_t  irte_size;             /* size (bytes) of each entry */
0115 };
0116 #endif
0117
0118 struct vector_info {
0119     struct iosapic_info *iosapic;   /* I/O SAPIC this vector is on */
0120     struct irt_entry *irte;     /* IRT entry */
0121     u32 __iomem *eoi_addr;      /* precalculate EOI reg address */
0122     u32 eoi_data;       /* IA64: ?       PA: swapped txn_data */
0123     int txn_irq;        /* virtual IRQ number for processor */
0124     ulong   txn_addr;       /* IA64: id_eid  PA: partial HPA */
0125     u32 txn_data;       /* CPU interrupt bit */
0126     u8  status;         /* status/flags */
0127     u8  irqline;        /* INTINn(IRQ) */
0128 };
0129
0130
0131 struct iosapic_info {
0132     struct iosapic_info *   isi_next;   /* list of I/O SAPIC */
0133     void __iomem *      addr;       /* remapped address */
0134     unsigned long       isi_hpa;    /* physical base address */
0135     struct vector_info *    isi_vector; /* IRdT (IRQ line) array */
0136     int         isi_num_vectors; /* size of IRdT array */
0137     int         isi_status; /* status/flags */
0138     unsigned int        isi_version;    /* DEBUG: data fr version reg */
0139 };
0140
0141
0142
0143 #ifdef __IA64__
0144 /*
0145 ** PA risc does NOT have any local sapics. IA64 does.
0146 ** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC).
0147 **
0148 ** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0
0149 **     Emulate the data on PAT platforms.
0150 */
0151 struct local_sapic_info {
0152     struct local_sapic_info *lsi_next;      /* point to next CPU info */
0153     int                     *lsi_cpu_id;    /* point to logical CPU id */
0154     unsigned long           *lsi_id_eid;    /* point to IA-64 CPU id */
0155     int                     *lsi_status;    /* point to CPU status   */
0156     void                    *lsi_private;   /* point to special info */
0157 };
0158
0159 /*
0160 ** "root" data structure which ties everything together.
0161 ** Should always be able to start with sapic_root and locate
0162 ** the desired information.
0163 */
0164 struct sapic_info {
0165     struct sapic_info   *si_next;   /* info is per cell */
0166     int                     si_cellid;      /* cell id */
0167     unsigned int            si_status;       /* status  */
0168     char                    *si_pib_base;   /* intr blk base address */
0169     local_sapic_info_t      *si_local_info;
0170     io_sapic_info_t         *si_io_info;
0171     extint_info_t           *si_extint_info;/* External Intr info      */
0172 };
0173 #endif
0174