drivers/parisc/eisa.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * eisa.c - provide support for EISA adapters in PA-RISC machines
0004  *
0005  * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
0006  * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
0007  *
0008  * There are two distinct EISA adapters.  Mongoose is found in machines
0009  * before the 712; then the Wax ASIC is used.  To complicate matters, the
0010  * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
0011  * dealt with elsewhere; this file is concerned only with the EISA portions
0012  * of Wax.
0013  *
0014  * HINT:
0015  * -----
0016  * To allow an ISA card to work properly in the EISA slot you need to
0017  * set an edge trigger level. This may be done on the palo command line
0018  * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
0019  * n and n2 as the irq levels you want to use.
0020  *
0021  * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
0022  * irq levels 10 and 11.
0023  */
0024
0025 #include <linux/init.h>
0026 #include <linux/ioport.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/kernel.h>
0029 #include <linux/module.h>
0030 #include <linux/pci.h>
0031 #include <linux/spinlock.h>
0032 #include <linux/eisa.h>
0033
0034 #include <asm/byteorder.h>
0035 #include <asm/io.h>
0036 #include <asm/hardware.h>
0037 #include <asm/processor.h>
0038 #include <asm/parisc-device.h>
0039 #include <asm/delay.h>
0040 #include <asm/eisa_bus.h>
0041 #include <asm/eisa_eeprom.h>
0042
0043 #include "iommu.h"
0044
0045 #if 0
0046 #define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
0047 #else
0048 #define EISA_DBG(msg, arg...)
0049 #endif
0050
0051 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
0052 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
0053
0054 static DEFINE_SPINLOCK(eisa_irq_lock);
0055
0056 void __iomem *eisa_eeprom_addr __read_mostly;
0057
0058 /* We can only have one EISA adapter in the system because neither
0059  * implementation can be flexed.
0060  */
0061 static struct eisa_ba {
0062     struct pci_hba_data hba;
0063     unsigned long eeprom_addr;
0064     struct eisa_root_device root;
0065 } eisa_dev;
0066
0067 /* Port ops */
0068
0069 static inline unsigned long eisa_permute(unsigned short port)
0070 {
0071     if (port & 0x300) {
0072         return 0xfc000000 | ((port & 0xfc00) >> 6)
0073             | ((port & 0x3f8) << 9) | (port & 7);
0074     } else {
0075         return 0xfc000000 | port;
0076     }
0077 }
0078
0079 unsigned char eisa_in8(unsigned short port)
0080 {
0081     if (EISA_bus)
0082         return gsc_readb(eisa_permute(port));
0083     return 0xff;
0084 }
0085
0086 unsigned short eisa_in16(unsigned short port)
0087 {
0088     if (EISA_bus)
0089         return le16_to_cpu(gsc_readw(eisa_permute(port)));
0090     return 0xffff;
0091 }
0092
0093 unsigned int eisa_in32(unsigned short port)
0094 {
0095     if (EISA_bus)
0096         return le32_to_cpu(gsc_readl(eisa_permute(port)));
0097     return 0xffffffff;
0098 }
0099
0100 void eisa_out8(unsigned char data, unsigned short port)
0101 {
0102     if (EISA_bus)
0103         gsc_writeb(data, eisa_permute(port));
0104 }
0105
0106 void eisa_out16(unsigned short data, unsigned short port)
0107 {
0108     if (EISA_bus)
0109         gsc_writew(cpu_to_le16(data), eisa_permute(port));
0110 }
0111
0112 void eisa_out32(unsigned int data, unsigned short port)
0113 {
0114     if (EISA_bus)
0115         gsc_writel(cpu_to_le32(data), eisa_permute(port));
0116 }
0117
0118 #ifndef CONFIG_PCI
0119 /* We call these directly without PCI.  See asm/io.h. */
0120 EXPORT_SYMBOL(eisa_in8);
0121 EXPORT_SYMBOL(eisa_in16);
0122 EXPORT_SYMBOL(eisa_in32);
0123 EXPORT_SYMBOL(eisa_out8);
0124 EXPORT_SYMBOL(eisa_out16);
0125 EXPORT_SYMBOL(eisa_out32);
0126 #endif
0127
0128 /* Interrupt handling */
0129
0130 /* cached interrupt mask registers */
0131 static int master_mask;
0132 static int slave_mask;
0133
0134 /* the trig level can be set with the
0135  * eisa_irq_edge=n,n,n commandline parameter
0136  * We should really read this from the EEPROM
0137  * in the furure.
0138  */
0139 /* irq 13,8,2,1,0 must be edge */
0140 static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
0141
0142
0143 /* called by free irq */
0144 static void eisa_mask_irq(struct irq_data *d)
0145 {
0146     unsigned int irq = d->irq;
0147     unsigned long flags;
0148
0149     EISA_DBG("disable irq %d\n", irq);
0150     /* just mask for now */
0151     spin_lock_irqsave(&eisa_irq_lock, flags);
0152         if (irq & 8) {
0153         slave_mask |= (1 << (irq&7));
0154         eisa_out8(slave_mask, 0xa1);
0155     } else {
0156         master_mask |= (1 << (irq&7));
0157         eisa_out8(master_mask, 0x21);
0158     }
0159     spin_unlock_irqrestore(&eisa_irq_lock, flags);
0160     EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
0161     EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
0162 }
0163
0164 /* called by request irq */
0165 static void eisa_unmask_irq(struct irq_data *d)
0166 {
0167     unsigned int irq = d->irq;
0168     unsigned long flags;
0169     EISA_DBG("enable irq %d\n", irq);
0170
0171     spin_lock_irqsave(&eisa_irq_lock, flags);
0172         if (irq & 8) {
0173         slave_mask &= ~(1 << (irq&7));
0174         eisa_out8(slave_mask, 0xa1);
0175     } else {
0176         master_mask &= ~(1 << (irq&7));
0177         eisa_out8(master_mask, 0x21);
0178     }
0179     spin_unlock_irqrestore(&eisa_irq_lock, flags);
0180     EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
0181     EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
0182 }
0183
0184 static struct irq_chip eisa_interrupt_type = {
0185     .name       =   "EISA",
0186     .irq_unmask =   eisa_unmask_irq,
0187     .irq_mask   =   eisa_mask_irq,
0188 };
0189
0190 static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
0191 {
0192     int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
0193     unsigned long flags;
0194
0195     spin_lock_irqsave(&eisa_irq_lock, flags);
0196     /* read IRR command */
0197     eisa_out8(0x0a, 0x20);
0198     eisa_out8(0x0a, 0xa0);
0199
0200     EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
0201            irq, eisa_in8(0x20), eisa_in8(0xa0));
0202
0203     /* read ISR command */
0204     eisa_out8(0x0a, 0x20);
0205     eisa_out8(0x0a, 0xa0);
0206     EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
0207          eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
0208
0209     irq &= 0xf;
0210
0211     /* mask irq and write eoi */
0212     if (irq & 8) {
0213         slave_mask |= (1 << (irq&7));
0214         eisa_out8(slave_mask, 0xa1);
0215         eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
0216         eisa_out8(0x62, 0x20);  /* 'Specific EOI' to master-IRQ2 */
0217
0218     } else {
0219         master_mask |= (1 << (irq&7));
0220         eisa_out8(master_mask, 0x21);
0221         eisa_out8(0x60|irq, 0x20);  /* 'Specific EOI' to master */
0222     }
0223     spin_unlock_irqrestore(&eisa_irq_lock, flags);
0224
0225     generic_handle_irq(irq);
0226
0227     spin_lock_irqsave(&eisa_irq_lock, flags);
0228     /* unmask */
0229         if (irq & 8) {
0230         slave_mask &= ~(1 << (irq&7));
0231         eisa_out8(slave_mask, 0xa1);
0232     } else {
0233         master_mask &= ~(1 << (irq&7));
0234         eisa_out8(master_mask, 0x21);
0235     }
0236     spin_unlock_irqrestore(&eisa_irq_lock, flags);
0237     return IRQ_HANDLED;
0238 }
0239
0240 static irqreturn_t dummy_irq2_handler(int _, void *dev)
0241 {
0242     printk(KERN_ALERT "eisa: uhh, irq2?\n");
0243     return IRQ_HANDLED;
0244 }
0245
0246 static void init_eisa_pic(void)
0247 {
0248     unsigned long flags;
0249
0250     spin_lock_irqsave(&eisa_irq_lock, flags);
0251
0252     eisa_out8(0xff, 0x21); /* mask during init */
0253     eisa_out8(0xff, 0xa1); /* mask during init */
0254
0255     /* master pic */
0256     eisa_out8(0x11, 0x20); /* ICW1 */
0257     eisa_out8(0x00, 0x21); /* ICW2 */
0258     eisa_out8(0x04, 0x21); /* ICW3 */
0259     eisa_out8(0x01, 0x21); /* ICW4 */
0260     eisa_out8(0x40, 0x20); /* OCW2 */
0261
0262     /* slave pic */
0263     eisa_out8(0x11, 0xa0); /* ICW1 */
0264     eisa_out8(0x08, 0xa1); /* ICW2 */
0265     eisa_out8(0x02, 0xa1); /* ICW3 */
0266     eisa_out8(0x01, 0xa1); /* ICW4 */
0267     eisa_out8(0x40, 0xa0); /* OCW2 */
0268
0269     udelay(100);
0270
0271     slave_mask = 0xff;
0272     master_mask = 0xfb;
0273     eisa_out8(slave_mask, 0xa1); /* OCW1 */
0274     eisa_out8(master_mask, 0x21); /* OCW1 */
0275
0276     /* setup trig level */
0277     EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
0278
0279     eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge  */
0280     eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
0281
0282     EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
0283     EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
0284     EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
0285     EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
0286
0287     spin_unlock_irqrestore(&eisa_irq_lock, flags);
0288 }
0289
0290 /* Device initialisation */
0291
0292 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
0293
0294 static int __init eisa_probe(struct parisc_device *dev)
0295 {
0296     int i, result;
0297
0298     char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
0299
0300     printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
0301         name, (unsigned long)dev->hpa.start);
0302
0303     eisa_dev.hba.dev = dev;
0304     eisa_dev.hba.iommu = ccio_get_iommu(dev);
0305
0306     eisa_dev.hba.lmmio_space.name = "EISA";
0307     eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
0308     eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
0309     eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
0310     result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
0311     if (result < 0) {
0312         printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
0313         return result;
0314     }
0315     eisa_dev.hba.io_space.name = "EISA";
0316     eisa_dev.hba.io_space.start = 0;
0317     eisa_dev.hba.io_space.end = 0xffff;
0318     eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
0319     result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
0320     if (result < 0) {
0321         printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
0322         return result;
0323     }
0324     pcibios_register_hba(&eisa_dev.hba);
0325
0326     result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
0327     if (result) {
0328         printk(KERN_ERR "EISA: request_irq failed!\n");
0329         goto error_release;
0330     }
0331
0332     /* Reserve IRQ2 */
0333     if (request_irq(2, dummy_irq2_handler, 0, "cascade", NULL))
0334         pr_err("Failed to request irq 2 (cascade)\n");
0335     for (i = 0; i < 16; i++) {
0336         irq_set_chip_and_handler(i, &eisa_interrupt_type,
0337                      handle_simple_irq);
0338     }
0339
0340     EISA_bus = 1;
0341
0342     if (dev->num_addrs) {
0343         /* newer firmware hand out the eeprom address */
0344         eisa_dev.eeprom_addr = dev->addr[0];
0345     } else {
0346         /* old firmware, need to figure out the box */
0347         if (is_mongoose(dev)) {
0348             eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
0349         } else {
0350             eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
0351         }
0352     }
0353     eisa_eeprom_addr = ioremap(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
0354     if (!eisa_eeprom_addr) {
0355         result = -ENOMEM;
0356         printk(KERN_ERR "EISA: ioremap failed!\n");
0357         goto error_free_irq;
0358     }
0359     result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
0360             &eisa_dev.hba.lmmio_space);
0361     init_eisa_pic();
0362
0363     if (result >= 0) {
0364         /* FIXME : Don't enumerate the bus twice. */
0365         eisa_dev.root.dev = &dev->dev;
0366         dev_set_drvdata(&dev->dev, &eisa_dev.root);
0367         eisa_dev.root.bus_base_addr = 0;
0368         eisa_dev.root.res = &eisa_dev.hba.io_space;
0369         eisa_dev.root.slots = result;
0370         eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
0371         if (eisa_root_register (&eisa_dev.root)) {
0372             printk(KERN_ERR "EISA: Failed to register EISA root\n");
0373             result = -ENOMEM;
0374             goto error_iounmap;
0375         }
0376     }
0377
0378     return 0;
0379
0380 error_iounmap:
0381     iounmap(eisa_eeprom_addr);
0382 error_free_irq:
0383     free_irq(dev->irq, &eisa_dev);
0384 error_release:
0385     release_resource(&eisa_dev.hba.io_space);
0386     return result;
0387 }
0388
0389 static const struct parisc_device_id eisa_tbl[] __initconst = {
0390     { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
0391     { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
0392     { 0, }
0393 };
0394
0395 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
0396
0397 static struct parisc_driver eisa_driver __refdata = {
0398     .name =     "eisa_ba",
0399     .id_table = eisa_tbl,
0400     .probe =    eisa_probe,
0401 };
0402
0403 void __init eisa_init(void)
0404 {
0405     register_parisc_driver(&eisa_driver);
0406 }
0407
0408
0409 static unsigned int eisa_irq_configured;
0410 void eisa_make_irq_level(int num)
0411 {
0412     if (eisa_irq_configured& (1<<num)) {
0413         printk(KERN_WARNING
0414                "IRQ %d polarity configured twice (last to level)\n",
0415                num);
0416     }
0417     eisa_irq_level |= (1<<num); /* set the corresponding bit */
0418     eisa_irq_configured |= (1<<num); /* set the corresponding bit */
0419 }
0420
0421 void eisa_make_irq_edge(int num)
0422 {
0423     if (eisa_irq_configured& (1<<num)) {
0424         printk(KERN_WARNING
0425                "IRQ %d polarity configured twice (last to edge)\n",
0426                num);
0427     }
0428     eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
0429     eisa_irq_configured |= (1<<num); /* set the corresponding bit */
0430 }
0431
0432 static int __init eisa_irq_setup(char *str)
0433 {
0434     char *cur = str;
0435     int val;
0436
0437     EISA_DBG("IRQ setup\n");
0438     while (cur != NULL) {
0439         char *pe;
0440
0441         val = (int) simple_strtoul(cur, &pe, 0);
0442         if (val > 15 || val < 0) {
0443             printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
0444             continue;
0445         }
0446         if (val == 2) {
0447             val = 9;
0448         }
0449         eisa_make_irq_edge(val); /* clear the corresponding bit */
0450         EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
0451
0452         if ((cur = strchr(cur, ','))) {
0453             cur++;
0454         } else {
0455             break;
0456         }
0457     }
0458     return 1;
0459 }
0460
0461 __setup("eisa_irq_edge=", eisa_irq_setup);
0462