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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 **  DINO manager
0004 **
0005 **  (c) Copyright 1999 Red Hat Software
0006 **  (c) Copyright 1999 SuSE GmbH
0007 **  (c) Copyright 1999,2000 Hewlett-Packard Company
0008 **  (c) Copyright 2000 Grant Grundler
0009 **  (c) Copyright 2006-2019 Helge Deller
0010 **
0011 **
0012 **  This module provides access to Dino PCI bus (config/IOport spaces)
0013 **  and helps manage Dino IRQ lines.
0014 **
0015 **  Dino interrupt handling is a bit complicated.
0016 **  Dino always writes to the broadcast EIR via irr0 for now.
0017 **  (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
0018 **  Only one processor interrupt is used for the 11 IRQ line 
0019 **  inputs to dino.
0020 **
0021 **  The different between Built-in Dino and Card-Mode
0022 **  dino is in chip initialization and pci device initialization.
0023 **
0024 **  Linux drivers can only use Card-Mode Dino if pci devices I/O port
0025 **  BARs are configured and used by the driver. Programming MMIO address 
0026 **  requires substantial knowledge of available Host I/O address ranges
0027 **  is currently not supported.  Port/Config accessor functions are the
0028 **  same. "BIOS" differences are handled within the existing routines.
0029 */
0030 
0031 /*  Changes :
0032 **  2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
0033 **      - added support for the integrated RS232.   
0034 */
0035 
0036 /*
0037 ** TODO: create a virtual address for each Dino HPA.
0038 **       GSC code might be able to do this since IODC data tells us
0039 **       how many pages are used. PCI subsystem could (must?) do this
0040 **       for PCI drivers devices which implement/use MMIO registers.
0041 */
0042 
0043 #include <linux/delay.h>
0044 #include <linux/types.h>
0045 #include <linux/kernel.h>
0046 #include <linux/pci.h>
0047 #include <linux/init.h>
0048 #include <linux/ioport.h>
0049 #include <linux/slab.h>
0050 #include <linux/interrupt.h>    /* for struct irqaction */
0051 #include <linux/spinlock.h> /* for spinlock_t and prototypes */
0052 
0053 #include <asm/pdc.h>
0054 #include <asm/page.h>
0055 #include <asm/io.h>
0056 #include <asm/hardware.h>
0057 
0058 #include "gsc.h"
0059 #include "iommu.h"
0060 
0061 #undef DINO_DEBUG
0062 
0063 #ifdef DINO_DEBUG
0064 #define DBG(x...) printk(x)
0065 #else
0066 #define DBG(x...)
0067 #endif
0068 
0069 /*
0070 ** Config accessor functions only pass in the 8-bit bus number
0071 ** and not the 8-bit "PCI Segment" number. Each Dino will be
0072 ** assigned a PCI bus number based on "when" it's discovered.
0073 **
0074 ** The "secondary" bus number is set to this before calling
0075 ** pci_scan_bus(). If any PPB's are present, the scan will
0076 ** discover them and update the "secondary" and "subordinate"
0077 ** fields in Dino's pci_bus structure.
0078 **
0079 ** Changes in the configuration *will* result in a different
0080 ** bus number for each dino.
0081 */
0082 
0083 #define is_card_dino(id)    ((id)->hw_type == HPHW_A_DMA)
0084 #define is_cujo(id)     ((id)->hversion == 0x682)
0085 
0086 #define DINO_IAR0       0x004
0087 #define DINO_IODC_ADDR      0x008
0088 #define DINO_IODC_DATA_0    0x008
0089 #define DINO_IODC_DATA_1    0x008
0090 #define DINO_IRR0       0x00C
0091 #define DINO_IAR1       0x010
0092 #define DINO_IRR1       0x014
0093 #define DINO_IMR        0x018
0094 #define DINO_IPR        0x01C
0095 #define DINO_TOC_ADDR       0x020
0096 #define DINO_ICR        0x024
0097 #define DINO_ILR        0x028
0098 #define DINO_IO_COMMAND     0x030
0099 #define DINO_IO_STATUS      0x034
0100 #define DINO_IO_CONTROL     0x038
0101 #define DINO_IO_GSC_ERR_RESP    0x040
0102 #define DINO_IO_ERR_INFO    0x044
0103 #define DINO_IO_PCI_ERR_RESP    0x048
0104 #define DINO_IO_FBB_EN      0x05c
0105 #define DINO_IO_ADDR_EN     0x060
0106 #define DINO_PCI_ADDR       0x064
0107 #define DINO_CONFIG_DATA    0x068
0108 #define DINO_IO_DATA        0x06c
0109 #define DINO_MEM_DATA       0x070   /* Dino 3.x only */
0110 #define DINO_GSC2X_CONFIG   0x7b4
0111 #define DINO_GMASK      0x800
0112 #define DINO_PAMR       0x804
0113 #define DINO_PAPR       0x808
0114 #define DINO_DAMODE     0x80c
0115 #define DINO_PCICMD     0x810
0116 #define DINO_PCISTS     0x814
0117 #define DINO_MLTIM      0x81c
0118 #define DINO_BRDG_FEAT      0x820
0119 #define DINO_PCIROR     0x824
0120 #define DINO_PCIWOR     0x828
0121 #define DINO_TLTIM      0x830
0122 
0123 #define DINO_IRQS 11        /* bits 0-10 are architected */
0124 #define DINO_IRR_MASK   0x5ff   /* only 10 bits are implemented */
0125 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
0126 
0127 #define DINO_MASK_IRQ(x)    (1<<(x))
0128 
0129 #define PCIINTA   0x001
0130 #define PCIINTB   0x002
0131 #define PCIINTC   0x004
0132 #define PCIINTD   0x008
0133 #define PCIINTE   0x010
0134 #define PCIINTF   0x020
0135 #define GSCEXTINT 0x040
0136 /* #define xxx       0x080 - bit 7 is "default" */
0137 /* #define xxx    0x100 - bit 8 not used */
0138 /* #define xxx    0x200 - bit 9 not used */
0139 #define RS232INT  0x400
0140 
0141 struct dino_device
0142 {
0143     struct pci_hba_data hba;    /* 'C' inheritance - must be first */
0144     spinlock_t      dinosaur_pen;
0145     u32             imr;      /* IRQ's which are enabled */ 
0146     struct gsc_irq      gsc_irq;
0147     int         global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
0148 #ifdef DINO_DEBUG
0149     unsigned int        dino_irr0; /* save most recent IRQ line stat */
0150 #endif
0151 };
0152 
0153 static inline struct dino_device *DINO_DEV(struct pci_hba_data *hba)
0154 {
0155     return container_of(hba, struct dino_device, hba);
0156 }
0157 
0158 /*
0159  * Dino Configuration Space Accessor Functions
0160  */
0161 
0162 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
0163 
0164 /*
0165  * keep the current highest bus count to assist in allocating busses.  This
0166  * tries to keep a global bus count total so that when we discover an 
0167  * entirely new bus, it can be given a unique bus number.
0168  */
0169 static int dino_current_bus = 0;
0170 
0171 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
0172         int size, u32 *val)
0173 {
0174     struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
0175     u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
0176     u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
0177     void __iomem *base_addr = d->hba.base_addr;
0178     unsigned long flags;
0179 
0180     DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
0181                                     size);
0182     spin_lock_irqsave(&d->dinosaur_pen, flags);
0183 
0184     /* tell HW which CFG address */
0185     __raw_writel(v, base_addr + DINO_PCI_ADDR);
0186 
0187     /* generate cfg read cycle */
0188     if (size == 1) {
0189         *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
0190     } else if (size == 2) {
0191         *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
0192     } else if (size == 4) {
0193         *val = readl(base_addr + DINO_CONFIG_DATA);
0194     }
0195 
0196     spin_unlock_irqrestore(&d->dinosaur_pen, flags);
0197     return 0;
0198 }
0199 
0200 /*
0201  * Dino address stepping "feature":
0202  * When address stepping, Dino attempts to drive the bus one cycle too soon
0203  * even though the type of cycle (config vs. MMIO) might be different. 
0204  * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
0205  */
0206 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
0207     int size, u32 val)
0208 {
0209     struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
0210     u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
0211     u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
0212     void __iomem *base_addr = d->hba.base_addr;
0213     unsigned long flags;
0214 
0215     DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
0216                                     size);
0217     spin_lock_irqsave(&d->dinosaur_pen, flags);
0218 
0219     /* avoid address stepping feature */
0220     __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
0221     __raw_readl(base_addr + DINO_CONFIG_DATA);
0222 
0223     /* tell HW which CFG address */
0224     __raw_writel(v, base_addr + DINO_PCI_ADDR);
0225     /* generate cfg read cycle */
0226     if (size == 1) {
0227         writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
0228     } else if (size == 2) {
0229         writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
0230     } else if (size == 4) {
0231         writel(val, base_addr + DINO_CONFIG_DATA);
0232     }
0233 
0234     spin_unlock_irqrestore(&d->dinosaur_pen, flags);
0235     return 0;
0236 }
0237 
0238 static struct pci_ops dino_cfg_ops = {
0239     .read =     dino_cfg_read,
0240     .write =    dino_cfg_write,
0241 };
0242 
0243 
0244 /*
0245  * Dino "I/O Port" Space Accessor Functions
0246  *
0247  * Many PCI devices don't require use of I/O port space (eg Tulip,
0248  * NCR720) since they export the same registers to both MMIO and
0249  * I/O port space.  Performance is going to stink if drivers use
0250  * I/O port instead of MMIO.
0251  */
0252 
0253 #define DINO_PORT_IN(type, size, mask) \
0254 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
0255 { \
0256     u##size v; \
0257     unsigned long flags; \
0258     spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
0259     /* tell HW which IO Port address */ \
0260     __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
0261     /* generate I/O PORT read cycle */ \
0262     v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
0263     spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
0264     return v; \
0265 }
0266 
0267 DINO_PORT_IN(b,  8, 3)
0268 DINO_PORT_IN(w, 16, 2)
0269 DINO_PORT_IN(l, 32, 0)
0270 
0271 #define DINO_PORT_OUT(type, size, mask) \
0272 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
0273 { \
0274     unsigned long flags; \
0275     spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
0276     /* tell HW which IO port address */ \
0277     __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
0278     /* generate cfg write cycle */ \
0279     write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
0280     spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
0281 }
0282 
0283 DINO_PORT_OUT(b,  8, 3)
0284 DINO_PORT_OUT(w, 16, 2)
0285 DINO_PORT_OUT(l, 32, 0)
0286 
0287 static struct pci_port_ops dino_port_ops = {
0288     .inb    = dino_in8,
0289     .inw    = dino_in16,
0290     .inl    = dino_in32,
0291     .outb   = dino_out8,
0292     .outw   = dino_out16,
0293     .outl   = dino_out32
0294 };
0295 
0296 static void dino_mask_irq(struct irq_data *d)
0297 {
0298     struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
0299     int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
0300 
0301     DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
0302 
0303     /* Clear the matching bit in the IMR register */
0304     dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
0305     __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
0306 }
0307 
0308 static void dino_unmask_irq(struct irq_data *d)
0309 {
0310     struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
0311     int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
0312     u32 tmp;
0313 
0314     DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
0315 
0316     /*
0317     ** clear pending IRQ bits
0318     **
0319     ** This does NOT change ILR state!
0320     ** See comment below for ILR usage.
0321     */
0322     __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
0323 
0324     /* set the matching bit in the IMR register */
0325     dino_dev->imr |= DINO_MASK_IRQ(local_irq);  /* used in dino_isr() */
0326     __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
0327 
0328     /* Emulate "Level Triggered" Interrupt
0329     ** Basically, a driver is blowing it if the IRQ line is asserted
0330     ** while the IRQ is disabled.  But tulip.c seems to do that....
0331     ** Give 'em a kluge award and a nice round of applause!
0332     **
0333     ** The gsc_write will generate an interrupt which invokes dino_isr().
0334     ** dino_isr() will read IPR and find nothing. But then catch this
0335     ** when it also checks ILR.
0336     */
0337     tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
0338     if (tmp & DINO_MASK_IRQ(local_irq)) {
0339         DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
0340                 __func__, tmp);
0341         gsc_writel(dino_dev->gsc_irq.txn_data, dino_dev->gsc_irq.txn_addr);
0342     }
0343 }
0344 
0345 #ifdef CONFIG_SMP
0346 static int dino_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
0347                 bool force)
0348 {
0349     struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
0350     struct cpumask tmask;
0351     int cpu_irq;
0352     u32 eim;
0353 
0354     if (!cpumask_and(&tmask, dest, cpu_online_mask))
0355         return -EINVAL;
0356 
0357     cpu_irq = cpu_check_affinity(d, &tmask);
0358     if (cpu_irq < 0)
0359         return cpu_irq;
0360 
0361     dino_dev->gsc_irq.txn_addr = txn_affinity_addr(d->irq, cpu_irq);
0362     eim = ((u32) dino_dev->gsc_irq.txn_addr) | dino_dev->gsc_irq.txn_data;
0363     __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
0364 
0365     irq_data_update_effective_affinity(d, &tmask);
0366 
0367     return IRQ_SET_MASK_OK;
0368 }
0369 #endif
0370 
0371 static struct irq_chip dino_interrupt_type = {
0372     .name       = "GSC-PCI",
0373     .irq_unmask = dino_unmask_irq,
0374     .irq_mask   = dino_mask_irq,
0375 #ifdef CONFIG_SMP
0376     .irq_set_affinity = dino_set_affinity_irq,
0377 #endif
0378 };
0379 
0380 
0381 /*
0382  * Handle a Processor interrupt generated by Dino.
0383  *
0384  * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
0385  * wedging the CPU. Could be removed or made optional at some point.
0386  */
0387 static irqreturn_t dino_isr(int irq, void *intr_dev)
0388 {
0389     struct dino_device *dino_dev = intr_dev;
0390     u32 mask;
0391     int ilr_loop = 100;
0392 
0393     /* read and acknowledge pending interrupts */
0394 #ifdef DINO_DEBUG
0395     dino_dev->dino_irr0 =
0396 #endif
0397     mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
0398 
0399     if (mask == 0)
0400         return IRQ_NONE;
0401 
0402 ilr_again:
0403     do {
0404         int local_irq = __ffs(mask);
0405         int irq = dino_dev->global_irq[local_irq];
0406         DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
0407             __func__, irq, intr_dev, mask);
0408         generic_handle_irq(irq);
0409         mask &= ~DINO_MASK_IRQ(local_irq);
0410     } while (mask);
0411 
0412     /* Support for level triggered IRQ lines.
0413     ** 
0414     ** Dropping this support would make this routine *much* faster.
0415     ** But since PCI requires level triggered IRQ line to share lines...
0416     ** device drivers may assume lines are level triggered (and not
0417     ** edge triggered like EISA/ISA can be).
0418     */
0419     mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
0420     if (mask) {
0421         if (--ilr_loop > 0)
0422             goto ilr_again;
0423         pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n",
0424                dino_dev->hba.base_addr, mask);
0425     }
0426     return IRQ_HANDLED;
0427 }
0428 
0429 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
0430 {
0431     int irq = gsc_assign_irq(&dino_interrupt_type, dino);
0432     if (irq == NO_IRQ)
0433         return;
0434 
0435     *irqp = irq;
0436     dino->global_irq[local_irq] = irq;
0437 }
0438 
0439 static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
0440 {
0441     int irq;
0442     struct dino_device *dino = ctrl;
0443 
0444     switch (dev->id.sversion) {
0445         case 0x00084:   irq =  8; break; /* PS/2 */
0446         case 0x0008c:   irq = 10; break; /* RS232 */
0447         case 0x00096:   irq =  8; break; /* PS/2 */
0448         default:    return;      /* Unknown */
0449     }
0450 
0451     dino_assign_irq(dino, irq, &dev->irq);
0452 }
0453 
0454 
0455 /*
0456  * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
0457  * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
0458  */
0459 static void quirk_cirrus_cardbus(struct pci_dev *dev)
0460 {
0461     u8 new_irq = dev->irq - 1;
0462     printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
0463             pci_name(dev), dev->irq, new_irq);
0464     dev->irq = new_irq;
0465 }
0466 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
0467 
0468 #ifdef CONFIG_TULIP
0469 /* Check if PCI device is behind a Card-mode Dino. */
0470 static int pci_dev_is_behind_card_dino(struct pci_dev *dev)
0471 {
0472     struct dino_device *dino_dev;
0473 
0474     dino_dev = DINO_DEV(parisc_walk_tree(dev->bus->bridge));
0475     return is_card_dino(&dino_dev->hba.dev->id);
0476 }
0477 
0478 static void pci_fixup_tulip(struct pci_dev *dev)
0479 {
0480     if (!pci_dev_is_behind_card_dino(dev))
0481         return;
0482     if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM))
0483         return;
0484     pr_warn("%s: HP HSC-PCI Cards with card-mode Dino not yet supported.\n",
0485         pci_name(dev));
0486     /* Disable this card by zeroing the PCI resources */
0487     memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
0488     memset(&dev->resource[1], 0, sizeof(dev->resource[1]));
0489 }
0490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_DEC, PCI_ANY_ID, pci_fixup_tulip);
0491 #endif /* CONFIG_TULIP */
0492 
0493 static void __init
0494 dino_bios_init(void)
0495 {
0496     DBG("dino_bios_init\n");
0497 }
0498 
0499 /*
0500  * dino_card_setup - Set up the memory space for a Dino in card mode.
0501  * @bus: the bus under this dino
0502  *
0503  * Claim an 8MB chunk of unused IO space and call the generic PCI routines
0504  * to set up the addresses of the devices on this bus.
0505  */
0506 #define _8MB 0x00800000UL
0507 static void __init
0508 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
0509 {
0510     int i;
0511     struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
0512     struct resource *res;
0513     char name[128];
0514     int size;
0515 
0516     res = &dino_dev->hba.lmmio_space;
0517     res->flags = IORESOURCE_MEM;
0518     size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 
0519              dev_name(bus->bridge));
0520     res->name = kmalloc(size+1, GFP_KERNEL);
0521     if(res->name)
0522         strcpy((char *)res->name, name);
0523     else
0524         res->name = dino_dev->hba.lmmio_space.name;
0525     
0526 
0527     if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
0528                 F_EXTEND(0xf0000000UL) | _8MB,
0529                 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
0530         struct pci_dev *dev, *tmp;
0531 
0532         printk(KERN_ERR "Dino: cannot attach bus %s\n",
0533                dev_name(bus->bridge));
0534         /* kill the bus, we can't do anything with it */
0535         list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
0536             list_del(&dev->bus_list);
0537         }
0538             
0539         return;
0540     }
0541     bus->resource[1] = res;
0542     bus->resource[0] = &(dino_dev->hba.io_space);
0543 
0544     /* Now tell dino what range it has */
0545     for (i = 1; i < 31; i++) {
0546         if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
0547             break;
0548     }
0549     DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
0550         i, res->start, base_addr + DINO_IO_ADDR_EN);
0551     __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
0552 }
0553 
0554 static void __init
0555 dino_card_fixup(struct pci_dev *dev)
0556 {
0557     u32 irq_pin;
0558 
0559     /*
0560     ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
0561     **         Not sure they were ever productized.
0562     **         Die here since we'll die later in dino_inb() anyway.
0563     */
0564     if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
0565         panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
0566     }
0567 
0568     /*
0569     ** Set Latency Timer to 0xff (not a shared bus)
0570     ** Set CACHELINE_SIZE.
0571     */
0572     dino_cfg_write(dev->bus, dev->devfn, 
0573                PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 
0574 
0575     /*
0576     ** Program INT_LINE for card-mode devices.
0577     ** The cards are hardwired according to this algorithm.
0578     ** And it doesn't matter if PPB's are present or not since
0579     ** the IRQ lines bypass the PPB.
0580     **
0581     ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
0582     ** The additional "-1" adjusts for skewing the IRQ<->slot.
0583     */
0584     dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 
0585     dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
0586 
0587     /* Shouldn't really need to do this but it's in case someone tries
0588     ** to bypass PCI services and look at the card themselves.
0589     */
0590     dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 
0591 }
0592 
0593 /* The alignment contraints for PCI bridges under dino */
0594 #define DINO_BRIDGE_ALIGN 0x100000
0595 
0596 
0597 static void __init
0598 dino_fixup_bus(struct pci_bus *bus)
0599 {
0600         struct pci_dev *dev;
0601         struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
0602 
0603     DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n",
0604         __func__, bus, bus->busn_res.start,
0605         bus->bridge->platform_data);
0606 
0607     /* Firmware doesn't set up card-mode dino, so we have to */
0608     if (is_card_dino(&dino_dev->hba.dev->id)) {
0609         dino_card_setup(bus, dino_dev->hba.base_addr);
0610     } else if (bus->parent) {
0611         int i;
0612 
0613         pci_read_bridge_bases(bus);
0614 
0615 
0616         for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
0617             if((bus->self->resource[i].flags & 
0618                 (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
0619                 continue;
0620             
0621             if(bus->self->resource[i].flags & IORESOURCE_MEM) {
0622                 /* There's a quirk to alignment of
0623                  * bridge memory resources: the start
0624                  * is the alignment and start-end is
0625                  * the size.  However, firmware will
0626                  * have assigned start and end, so we
0627                  * need to take this into account */
0628                 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
0629                 bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
0630                 
0631             }
0632                     
0633             DBG("DEBUG %s assigning %d [%pR]\n",
0634                 dev_name(&bus->self->dev), i,
0635                 &bus->self->resource[i]);
0636             WARN_ON(pci_assign_resource(bus->self, i));
0637             DBG("DEBUG %s after assign %d [%pR]\n",
0638                 dev_name(&bus->self->dev), i,
0639                 &bus->self->resource[i]);
0640         }
0641     }
0642 
0643 
0644     list_for_each_entry(dev, &bus->devices, bus_list) {
0645         if (is_card_dino(&dino_dev->hba.dev->id))
0646             dino_card_fixup(dev);
0647 
0648         /*
0649         ** P2PB's only have 2 BARs, no IRQs.
0650         ** I'd like to just ignore them for now.
0651         */
0652         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)  {
0653             pcibios_init_bridge(dev);
0654             continue;
0655         }
0656 
0657         /* null out the ROM resource if there is one (we don't
0658          * care about an expansion rom on parisc, since it
0659          * usually contains (x86) bios code) */
0660         dev->resource[PCI_ROM_RESOURCE].flags = 0;
0661                 
0662         if(dev->irq == 255) {
0663 
0664 #define DINO_FIX_UNASSIGNED_INTERRUPTS
0665 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
0666 
0667             /* This code tries to assign an unassigned
0668              * interrupt.  Leave it disabled unless you
0669              * *really* know what you're doing since the
0670              * pin<->interrupt line mapping varies by bus
0671              * and machine */
0672 
0673             u32 irq_pin;
0674             
0675             dino_cfg_read(dev->bus, dev->devfn, 
0676                       PCI_INTERRUPT_PIN, 1, &irq_pin);
0677             irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
0678             printk(KERN_WARNING "Device %s has undefined IRQ, "
0679                     "setting to %d\n", pci_name(dev), irq_pin);
0680             dino_cfg_write(dev->bus, dev->devfn, 
0681                        PCI_INTERRUPT_LINE, 1, irq_pin);
0682             dino_assign_irq(dino_dev, irq_pin, &dev->irq);
0683 #else
0684             dev->irq = 65535;
0685             printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
0686 #endif
0687         } else {
0688             /* Adjust INT_LINE for that busses region */
0689             dino_assign_irq(dino_dev, dev->irq, &dev->irq);
0690         }
0691     }
0692 }
0693 
0694 
0695 static struct pci_bios_ops dino_bios_ops = {
0696     .init       = dino_bios_init,
0697     .fixup_bus  = dino_fixup_bus
0698 };
0699 
0700 
0701 /*
0702  *  Initialise a DINO controller chip
0703  */
0704 static void __init
0705 dino_card_init(struct dino_device *dino_dev)
0706 {
0707     u32 brdg_feat = 0x00784e05;
0708     unsigned long status;
0709 
0710     status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
0711     if (status & 0x0000ff80) {
0712         __raw_writel(0x00000005,
0713                 dino_dev->hba.base_addr+DINO_IO_COMMAND);
0714         udelay(1);
0715     }
0716 
0717     __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
0718     __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
0719     __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
0720 
0721 #if 1
0722 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
0723     /*
0724     ** PCX-L processors don't support XQL like Dino wants it.
0725     ** PCX-L2 ignore XQL signal and it doesn't matter.
0726     */
0727     brdg_feat &= ~0x4;  /* UXQL */
0728 #endif
0729     __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
0730 
0731     /*
0732     ** Don't enable address decoding until we know which I/O range
0733     ** currently is available from the host. Only affects MMIO
0734     ** and not I/O port space.
0735     */
0736     __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
0737 
0738     __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
0739     __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
0740     __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
0741 
0742     __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
0743     __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
0744     __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
0745 
0746     /* Disable PAMR before writing PAPR */
0747     __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
0748     __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
0749     __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
0750 
0751     /*
0752     ** Dino ERS encourages enabling FBB (0x6f).
0753     ** We can't until we know *all* devices below us can support it.
0754     ** (Something in device configuration header tells us).
0755     */
0756     __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
0757 
0758     /* Somewhere, the PCI spec says give devices 1 second
0759     ** to recover from the #RESET being de-asserted.
0760     ** Experience shows most devices only need 10ms.
0761     ** This short-cut speeds up booting significantly.
0762     */
0763     mdelay(pci_post_reset_delay);
0764 }
0765 
0766 static int __init
0767 dino_bridge_init(struct dino_device *dino_dev, const char *name)
0768 {
0769     unsigned long io_addr;
0770     int result, i, count=0;
0771     struct resource *res, *prevres = NULL;
0772     /*
0773      * Decoding IO_ADDR_EN only works for Built-in Dino
0774      * since PDC has already initialized this.
0775      */
0776 
0777     io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
0778     if (io_addr == 0) {
0779         printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
0780         return -ENODEV;
0781     }
0782 
0783     res = &dino_dev->hba.lmmio_space;
0784     for (i = 0; i < 32; i++) {
0785         unsigned long start, end;
0786 
0787         if((io_addr & (1 << i)) == 0)
0788             continue;
0789 
0790         start = F_EXTEND(0xf0000000UL) | (i << 23);
0791         end = start + 8 * 1024 * 1024 - 1;
0792 
0793         DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
0794             start, end);
0795 
0796         if(prevres && prevres->end + 1 == start) {
0797             prevres->end = end;
0798         } else {
0799             if(count >= DINO_MAX_LMMIO_RESOURCES) {
0800                 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
0801                 break;
0802             }
0803             prevres = res;
0804             res->start = start;
0805             res->end = end;
0806             res->flags = IORESOURCE_MEM;
0807             res->name = kmalloc(64, GFP_KERNEL);
0808             if(res->name)
0809                 snprintf((char *)res->name, 64, "%s LMMIO %d",
0810                      name, count);
0811             res++;
0812             count++;
0813         }
0814     }
0815 
0816     res = &dino_dev->hba.lmmio_space;
0817 
0818     for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
0819         if(res[i].flags == 0)
0820             break;
0821 
0822         result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
0823         if (result < 0) {
0824             printk(KERN_ERR "%s: failed to claim PCI Bus address "
0825                    "space %d (%pR)!\n", name, i, &res[i]);
0826             return result;
0827         }
0828     }
0829     return 0;
0830 }
0831 
0832 static int __init dino_common_init(struct parisc_device *dev,
0833         struct dino_device *dino_dev, const char *name)
0834 {
0835     int status;
0836     u32 eim;
0837     struct resource *res;
0838 
0839     pcibios_register_hba(&dino_dev->hba);
0840 
0841     pci_bios = &dino_bios_ops;   /* used by pci_scan_bus() */
0842     pci_port = &dino_port_ops;
0843 
0844     /*
0845     ** Note: SMP systems can make use of IRR1/IAR1 registers
0846     **   But it won't buy much performance except in very
0847     **   specific applications/configurations. Note Dino
0848     **   still only has 11 IRQ input lines - just map some of them
0849     **   to a different processor.
0850     */
0851     dev->irq = gsc_alloc_irq(&dino_dev->gsc_irq);
0852     eim = ((u32) dino_dev->gsc_irq.txn_addr) | dino_dev->gsc_irq.txn_data;
0853 
0854     /* 
0855     ** Dino needs a PA "IRQ" to get a processor's attention.
0856     ** arch/parisc/kernel/irq.c returns an EIRR bit.
0857     */
0858     if (dev->irq < 0) {
0859         printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
0860         return 1;
0861     }
0862 
0863     status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
0864     if (status) {
0865         printk(KERN_WARNING "%s: request_irq() failed with %d\n", 
0866             name, status);
0867         return 1;
0868     }
0869 
0870     /* Support the serial port which is sometimes attached on built-in
0871      * Dino / Cujo chips.
0872      */
0873 
0874     gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
0875 
0876     /*
0877     ** This enables DINO to generate interrupts when it sees
0878     ** any of its inputs *change*. Just asserting an IRQ
0879     ** before it's enabled (ie unmasked) isn't good enough.
0880     */
0881     __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
0882 
0883     /*
0884     ** Some platforms don't clear Dino's IRR0 register at boot time.
0885     ** Reading will clear it now.
0886     */
0887     __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
0888 
0889     /* allocate I/O Port resource region */
0890     res = &dino_dev->hba.io_space;
0891     if (!is_cujo(&dev->id)) {
0892         res->name = "Dino I/O Port";
0893     } else {
0894         res->name = "Cujo I/O Port";
0895     }
0896     res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
0897     res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
0898     res->flags = IORESOURCE_IO; /* do not mark it busy ! */
0899     if (request_resource(&ioport_resource, res) < 0) {
0900         printk(KERN_ERR "%s: request I/O Port region failed "
0901                "0x%lx/%lx (hpa 0x%px)\n",
0902                name, (unsigned long)res->start, (unsigned long)res->end,
0903                dino_dev->hba.base_addr);
0904         return 1;
0905     }
0906 
0907     return 0;
0908 }
0909 
0910 #define CUJO_RAVEN_ADDR     F_EXTEND(0xf1000000UL)
0911 #define CUJO_FIREHAWK_ADDR  F_EXTEND(0xf1604000UL)
0912 #define CUJO_RAVEN_BADPAGE  0x01003000UL
0913 #define CUJO_FIREHAWK_BADPAGE   0x01607000UL
0914 
0915 static const char dino_vers[][4] = {
0916     "2.0",
0917     "2.1",
0918     "3.0",
0919     "3.1"
0920 };
0921 
0922 static const char cujo_vers[][4] = {
0923     "1.0",
0924     "2.0"
0925 };
0926 
0927 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
0928 
0929 /*
0930 ** Determine if dino should claim this chip (return 0) or not (return 1).
0931 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
0932 ** Much of the initialization is common though.
0933 */
0934 static int __init dino_probe(struct parisc_device *dev)
0935 {
0936     struct dino_device *dino_dev;   // Dino specific control struct
0937     const char *version = "unknown";
0938     char *name;
0939     int is_cujo = 0;
0940     LIST_HEAD(resources);
0941     struct pci_bus *bus;
0942     unsigned long hpa = dev->hpa.start;
0943     int max;
0944 
0945     name = "Dino";
0946     if (is_card_dino(&dev->id)) {
0947         version = "3.x (card mode)";
0948     } else {
0949         if (!is_cujo(&dev->id)) {
0950             if (dev->id.hversion_rev < 4) {
0951                 version = dino_vers[dev->id.hversion_rev];
0952             }
0953         } else {
0954             name = "Cujo";
0955             is_cujo = 1;
0956             if (dev->id.hversion_rev < 2) {
0957                 version = cujo_vers[dev->id.hversion_rev];
0958             }
0959         }
0960     }
0961 
0962     printk("%s version %s found at 0x%lx\n", name, version, hpa);
0963 
0964     if (!request_mem_region(hpa, PAGE_SIZE, name)) {
0965         printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
0966             hpa);
0967         return 1;
0968     }
0969 
0970     /* Check for bugs */
0971     if (is_cujo && dev->id.hversion_rev == 1) {
0972 #ifdef CONFIG_IOMMU_CCIO
0973         printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
0974         if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
0975             ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
0976         } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
0977             ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
0978         } else {
0979             printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
0980         }
0981 #endif
0982     } else if (!is_cujo && !is_card_dino(&dev->id) &&
0983             dev->id.hversion_rev < 3) {
0984         printk(KERN_WARNING
0985 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
0986 "data corruption.  See Service Note Numbers: A4190A-01, A4191A-01.\n"
0987 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
0988 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
0989             dev->id.hversion_rev);
0990 /* REVISIT: why are C200/C240 listed in the README table but not
0991 **   "Models affected"? Could be an omission in the original literature.
0992 */
0993     }
0994 
0995     dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
0996     if (!dino_dev) {
0997         printk("dino_init_chip - couldn't alloc dino_device\n");
0998         return 1;
0999     }
1000 
1001     dino_dev->hba.dev = dev;
1002     dino_dev->hba.base_addr = ioremap(hpa, 4096);
1003     dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1004     spin_lock_init(&dino_dev->dinosaur_pen);
1005     dino_dev->hba.iommu = ccio_get_iommu(dev);
1006 
1007     if (is_card_dino(&dev->id)) {
1008         dino_card_init(dino_dev);
1009     } else {
1010         dino_bridge_init(dino_dev, name);
1011     }
1012 
1013     if (dino_common_init(dev, dino_dev, name))
1014         return 1;
1015 
1016     dev->dev.platform_data = dino_dev;
1017 
1018     pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
1019                 HBA_PORT_BASE(dino_dev->hba.hba_num));
1020     if (dino_dev->hba.lmmio_space.flags)
1021         pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
1022                     dino_dev->hba.lmmio_space_offset);
1023     if (dino_dev->hba.elmmio_space.flags)
1024         pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
1025                     dino_dev->hba.lmmio_space_offset);
1026     if (dino_dev->hba.gmmio_space.flags)
1027         pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
1028 
1029     dino_dev->hba.bus_num.start = dino_current_bus;
1030     dino_dev->hba.bus_num.end = 255;
1031     dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
1032     pci_add_resource(&resources, &dino_dev->hba.bus_num);
1033     /*
1034     ** It's not used to avoid chicken/egg problems
1035     ** with configuration accessor functions.
1036     */
1037     dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
1038              dino_current_bus, &dino_cfg_ops, NULL, &resources);
1039     if (!bus) {
1040         printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
1041                dev_name(&dev->dev), dino_current_bus);
1042         pci_free_resource_list(&resources);
1043         /* increment the bus number in case of duplicates */
1044         dino_current_bus++;
1045         return 0;
1046     }
1047 
1048     max = pci_scan_child_bus(bus);
1049     pci_bus_update_busn_res_end(bus, max);
1050 
1051     /* This code *depends* on scanning being single threaded
1052      * if it isn't, this global bus number count will fail
1053      */
1054     dino_current_bus = max + 1;
1055     pci_bus_assign_resources(bus);
1056     pci_bus_add_devices(bus);
1057     return 0;
1058 }
1059 
1060 /*
1061  * Normally, we would just test sversion.  But the Elroy PCI adapter has
1062  * the same sversion as Dino, so we have to check hversion as well.
1063  * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1064  * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1065  * For card-mode Dino, most machines report an sversion of 9D.  But 715
1066  * and 725 firmware misreport it as 0x08080 for no adequately explained
1067  * reason.
1068  */
1069 static const struct parisc_device_id dino_tbl[] __initconst = {
1070     { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1071     { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1072     { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1073     { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1074     { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1075     { 0, }
1076 };
1077 
1078 static struct parisc_driver dino_driver __refdata = {
1079     .name =     "dino",
1080     .id_table = dino_tbl,
1081     .probe =    dino_probe,
1082 };
1083 
1084 /*
1085  * One time initialization to let the world know Dino is here.
1086  * This is the only routine which is NOT static.
1087  * Must be called exactly once before pci_init().
1088  */
1089 int __init dino_init(void)
1090 {
1091     register_parisc_driver(&dino_driver);
1092     return 0;
1093 }
1094
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