drivers/nvmem/sunplus-ocotp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /*
0004  * The OCOTP driver for Sunplus SP7021
0005  *
0006  * Copyright (C) 2019 Sunplus Technology Inc., All rights reserved.
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/module.h>
0016 #include <linux/nvmem-provider.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019
0020 /*
0021  * OTP memory
0022  * Each bank contains 4 words (32 bits).
0023  * Bank 0 starts at offset 0 from the base.
0024  */
0025
0026 #define OTP_WORDS_PER_BANK      4
0027 #define OTP_WORD_SIZE           sizeof(u32)
0028 #define OTP_BIT_ADDR_OF_BANK        (8 * OTP_WORD_SIZE * OTP_WORDS_PER_BANK)
0029 #define QAC628_OTP_NUM_BANKS        8
0030 #define QAC628_OTP_SIZE         (QAC628_OTP_NUM_BANKS * OTP_WORDS_PER_BANK * OTP_WORD_SIZE)
0031 #define OTP_READ_TIMEOUT_US     200000
0032
0033 /* HB_GPIO */
0034 #define ADDRESS_8_DATA          0x20
0035
0036 /* OTP_RX */
0037 #define OTP_CONTROL_2           0x48
0038 #define OTP_RD_PERIOD           GENMASK(15, 8)
0039 #define OTP_RD_PERIOD_MASK      ~GENMASK(15, 8)
0040 #define CPU_CLOCK           FIELD_PREP(OTP_RD_PERIOD, 30)
0041 #define SEL_BAK_KEY2            BIT(5)
0042 #define SEL_BAK_KEY2_MASK       ~BIT(5)
0043 #define SW_TRIM_EN          BIT(4)
0044 #define SW_TRIM_EN_MASK         ~BIT(4)
0045 #define SEL_BAK_KEY         BIT(3)
0046 #define SEL_BAK_KEY_MASK        ~BIT(3)
0047 #define OTP_READ            BIT(2)
0048 #define OTP_LOAD_SECURE_DATA        BIT(1)
0049 #define OTP_LOAD_SECURE_DATA_MASK   ~BIT(1)
0050 #define OTP_DO_CRC          BIT(0)
0051 #define OTP_DO_CRC_MASK         ~BIT(0)
0052 #define OTP_STATUS          0x4c
0053 #define OTP_READ_DONE           BIT(4)
0054 #define OTP_READ_DONE_MASK      ~BIT(4)
0055 #define OTP_LOAD_SECURE_DONE_MASK   ~BIT(2)
0056 #define OTP_READ_ADDRESS        0x50
0057
0058 enum base_type {
0059     HB_GPIO,
0060     OTPRX,
0061     BASEMAX,
0062 };
0063
0064 struct sp_ocotp_priv {
0065     struct device *dev;
0066     void __iomem *base[BASEMAX];
0067     struct clk *clk;
0068 };
0069
0070 struct sp_ocotp_data {
0071     int size;
0072 };
0073
0074 static const struct sp_ocotp_data sp_otp_v0 = {
0075     .size = QAC628_OTP_SIZE,
0076 };
0077
0078 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value)
0079 {
0080     unsigned int addr_data;
0081     unsigned int byte_shift;
0082     unsigned int status;
0083     int ret;
0084
0085     addr_data = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
0086     addr_data = addr_data / OTP_WORD_SIZE;
0087
0088     byte_shift = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
0089     byte_shift = byte_shift % OTP_WORD_SIZE;
0090
0091     addr = addr / (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
0092     addr = addr * OTP_BIT_ADDR_OF_BANK;
0093
0094     writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK &
0095            OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS);
0096     writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS);
0097     writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ,
0098            otp->base[OTPRX] + OTP_CONTROL_2);
0099     writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK
0100            & SEL_BAK_KEY_MASK & OTP_LOAD_SECURE_DATA_MASK & OTP_DO_CRC_MASK,
0101            otp->base[OTPRX] + OTP_CONTROL_2);
0102     writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK,
0103            otp->base[OTPRX] + OTP_CONTROL_2);
0104
0105     ret = readl_poll_timeout(otp->base[OTPRX] + OTP_STATUS, status,
0106                  status & OTP_READ_DONE, 10, OTP_READ_TIMEOUT_US);
0107
0108     if (ret < 0)
0109         return ret;
0110
0111     *value = (readl(otp->base[HB_GPIO] + ADDRESS_8_DATA + addr_data * OTP_WORD_SIZE)
0112           >> (8 * byte_shift)) & 0xff;
0113
0114     return ret;
0115 }
0116
0117 static int sp_ocotp_read(void *priv, unsigned int offset, void *value, size_t bytes)
0118 {
0119     struct sp_ocotp_priv *otp = priv;
0120     unsigned int addr;
0121     char *buf = value;
0122     char val[4];
0123     int ret;
0124
0125     ret = clk_enable(otp->clk);
0126     if (ret)
0127         return ret;
0128
0129     *buf = 0;
0130     for (addr = offset; addr < (offset + bytes); addr++) {
0131         ret = sp_otp_read_real(otp, addr, val);
0132         if (ret < 0) {
0133             dev_err(otp->dev, "OTP read fail:%d at %d", ret, addr);
0134             goto disable_clk;
0135         }
0136
0137         *buf++ = *val;
0138     }
0139
0140 disable_clk:
0141     clk_disable(otp->clk);
0142
0143     return ret;
0144 }
0145
0146 static struct nvmem_config sp_ocotp_nvmem_config = {
0147     .name = "sp-ocotp",
0148     .read_only = true,
0149     .word_size = 1,
0150     .size = QAC628_OTP_SIZE,
0151     .stride = 1,
0152     .reg_read = sp_ocotp_read,
0153     .owner = THIS_MODULE,
0154 };
0155
0156 static int sp_ocotp_probe(struct platform_device *pdev)
0157 {
0158     struct device *dev = &pdev->dev;
0159     struct nvmem_device *nvmem;
0160     struct sp_ocotp_priv *otp;
0161     struct resource *res;
0162     int ret;
0163
0164     otp = devm_kzalloc(dev, sizeof(*otp), GFP_KERNEL);
0165     if (!otp)
0166         return -ENOMEM;
0167
0168     otp->dev = dev;
0169
0170     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hb_gpio");
0171     otp->base[HB_GPIO] = devm_ioremap_resource(dev, res);
0172     if (IS_ERR(otp->base[HB_GPIO]))
0173         return PTR_ERR(otp->base[HB_GPIO]);
0174
0175     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otprx");
0176     otp->base[OTPRX] = devm_ioremap_resource(dev, res);
0177     if (IS_ERR(otp->base[OTPRX]))
0178         return PTR_ERR(otp->base[OTPRX]);
0179
0180     otp->clk = devm_clk_get(&pdev->dev, NULL);
0181     if (IS_ERR(otp->clk))
0182         return dev_err_probe(&pdev->dev, PTR_ERR(otp->clk),
0183                         "devm_clk_get fail\n");
0184
0185     ret = clk_prepare(otp->clk);
0186     if (ret < 0) {
0187         dev_err(dev, "failed to prepare clk: %d\n", ret);
0188         return ret;
0189     }
0190
0191     sp_ocotp_nvmem_config.priv = otp;
0192     sp_ocotp_nvmem_config.dev = dev;
0193
0194     nvmem = devm_nvmem_register(dev, &sp_ocotp_nvmem_config);
0195     if (IS_ERR(nvmem))
0196         return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
0197                         "register nvmem device fail\n");
0198
0199     platform_set_drvdata(pdev, nvmem);
0200
0201     dev_dbg(dev, "banks:%d x wpb:%d x wsize:%d = %d",
0202         (int)QAC628_OTP_NUM_BANKS, (int)OTP_WORDS_PER_BANK,
0203         (int)OTP_WORD_SIZE, (int)QAC628_OTP_SIZE);
0204
0205     return 0;
0206 }
0207
0208 static const struct of_device_id sp_ocotp_dt_ids[] = {
0209     { .compatible = "sunplus,sp7021-ocotp", .data = &sp_otp_v0 },
0210     { }
0211 };
0212 MODULE_DEVICE_TABLE(of, sp_ocotp_dt_ids);
0213
0214 static struct platform_driver sp_otp_driver = {
0215     .probe     = sp_ocotp_probe,
0216     .driver    = {
0217         .name           = "sunplus,sp7021-ocotp",
0218         .of_match_table = sp_ocotp_dt_ids,
0219     }
0220 };
0221 module_platform_driver(sp_otp_driver);
0222
0223 MODULE_AUTHOR("Vincent Shih <vincent.sunplus@gmail.com>");
0224 MODULE_DESCRIPTION("Sunplus On-Chip OTP driver");
0225 MODULE_LICENSE("GPL");
0226