drivers/nvmem/stm32-romem.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * STM32 Factory-programmed memory read access driver
0004  *
0005  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0006  * Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics.
0007  */
0008
0009 #include <linux/arm-smccc.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/nvmem-provider.h>
0013 #include <linux/of_device.h>
0014
0015 /* BSEC secure service access from non-secure */
0016 #define STM32_SMC_BSEC          0x82001003
0017 #define STM32_SMC_READ_SHADOW       0x01
0018 #define STM32_SMC_PROG_OTP      0x02
0019 #define STM32_SMC_WRITE_SHADOW      0x03
0020 #define STM32_SMC_READ_OTP      0x04
0021
0022 /* shadow registers offest */
0023 #define STM32MP15_BSEC_DATA0        0x200
0024
0025 /* 32 (x 32-bits) lower shadow registers */
0026 #define STM32MP15_BSEC_NUM_LOWER    32
0027
0028 struct stm32_romem_cfg {
0029     int size;
0030 };
0031
0032 struct stm32_romem_priv {
0033     void __iomem *base;
0034     struct nvmem_config cfg;
0035 };
0036
0037 static int stm32_romem_read(void *context, unsigned int offset, void *buf,
0038                 size_t bytes)
0039 {
0040     struct stm32_romem_priv *priv = context;
0041     u8 *buf8 = buf;
0042     int i;
0043
0044     for (i = offset; i < offset + bytes; i++)
0045         *buf8++ = readb_relaxed(priv->base + i);
0046
0047     return 0;
0048 }
0049
0050 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
0051 {
0052 #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
0053     struct arm_smccc_res res;
0054
0055     arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
0056     if (res.a0)
0057         return -EIO;
0058
0059     if (result)
0060         *result = (u32)res.a1;
0061
0062     return 0;
0063 #else
0064     return -ENXIO;
0065 #endif
0066 }
0067
0068 static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
0069                size_t bytes)
0070 {
0071     struct stm32_romem_priv *priv = context;
0072     struct device *dev = priv->cfg.dev;
0073     u32 roffset, rbytes, val;
0074     u8 *buf8 = buf, *val8 = (u8 *)&val;
0075     int i, j = 0, ret, skip_bytes, size;
0076
0077     /* Round unaligned access to 32-bits */
0078     roffset = rounddown(offset, 4);
0079     skip_bytes = offset & 0x3;
0080     rbytes = roundup(bytes + skip_bytes, 4);
0081
0082     if (roffset + rbytes > priv->cfg.size)
0083         return -EINVAL;
0084
0085     for (i = roffset; (i < roffset + rbytes); i += 4) {
0086         u32 otp = i >> 2;
0087
0088         if (otp < STM32MP15_BSEC_NUM_LOWER) {
0089             /* read lower data from shadow registers */
0090             val = readl_relaxed(
0091                 priv->base + STM32MP15_BSEC_DATA0 + i);
0092         } else {
0093             ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
0094                          &val);
0095             if (ret) {
0096                 dev_err(dev, "Can't read data%d (%d)\n", otp,
0097                     ret);
0098                 return ret;
0099             }
0100         }
0101         /* skip first bytes in case of unaligned read */
0102         if (skip_bytes)
0103             size = min(bytes, (size_t)(4 - skip_bytes));
0104         else
0105             size = min(bytes, (size_t)4);
0106         memcpy(&buf8[j], &val8[skip_bytes], size);
0107         bytes -= size;
0108         j += size;
0109         skip_bytes = 0;
0110     }
0111
0112     return 0;
0113 }
0114
0115 static int stm32_bsec_write(void *context, unsigned int offset, void *buf,
0116                 size_t bytes)
0117 {
0118     struct stm32_romem_priv *priv = context;
0119     struct device *dev = priv->cfg.dev;
0120     u32 *buf32 = buf;
0121     int ret, i;
0122
0123     /* Allow only writing complete 32-bits aligned words */
0124     if ((bytes % 4) || (offset % 4))
0125         return -EINVAL;
0126
0127     for (i = offset; i < offset + bytes; i += 4) {
0128         ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
0129                      NULL);
0130         if (ret) {
0131             dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
0132             return ret;
0133         }
0134     }
0135
0136     return 0;
0137 }
0138
0139 static int stm32_romem_probe(struct platform_device *pdev)
0140 {
0141     const struct stm32_romem_cfg *cfg;
0142     struct device *dev = &pdev->dev;
0143     struct stm32_romem_priv *priv;
0144     struct resource *res;
0145
0146     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0147     if (!priv)
0148         return -ENOMEM;
0149
0150     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0151     priv->base = devm_ioremap_resource(dev, res);
0152     if (IS_ERR(priv->base))
0153         return PTR_ERR(priv->base);
0154
0155     priv->cfg.name = "stm32-romem";
0156     priv->cfg.word_size = 1;
0157     priv->cfg.stride = 1;
0158     priv->cfg.dev = dev;
0159     priv->cfg.priv = priv;
0160     priv->cfg.owner = THIS_MODULE;
0161
0162     cfg = (const struct stm32_romem_cfg *)
0163         of_match_device(dev->driver->of_match_table, dev)->data;
0164     if (!cfg) {
0165         priv->cfg.read_only = true;
0166         priv->cfg.size = resource_size(res);
0167         priv->cfg.reg_read = stm32_romem_read;
0168     } else {
0169         priv->cfg.size = cfg->size;
0170         priv->cfg.reg_read = stm32_bsec_read;
0171         priv->cfg.reg_write = stm32_bsec_write;
0172     }
0173
0174     return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
0175 }
0176
0177 static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
0178     .size = 384, /* 96 x 32-bits data words */
0179 };
0180
0181 static const struct of_device_id stm32_romem_of_match[] = {
0182     { .compatible = "st,stm32f4-otp", }, {
0183         .compatible = "st,stm32mp15-bsec",
0184         .data = (void *)&stm32mp15_bsec_cfg,
0185     }, {
0186     },
0187 };
0188 MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
0189
0190 static struct platform_driver stm32_romem_driver = {
0191     .probe = stm32_romem_probe,
0192     .driver = {
0193         .name = "stm32-romem",
0194         .of_match_table = of_match_ptr(stm32_romem_of_match),
0195     },
0196 };
0197 module_platform_driver(stm32_romem_driver);
0198
0199 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
0200 MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
0201 MODULE_ALIAS("platform:nvmem-stm32-romem");
0202 MODULE_LICENSE("GPL v2");