drivers/nvmem/sprd-efuse.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2019 Spreadtrum Communications Inc.
0003
0004 #include <linux/clk.h>
0005 #include <linux/delay.h>
0006 #include <linux/hwspinlock.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/nvmem-provider.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012
0013 #define SPRD_EFUSE_ENABLE       0x20
0014 #define SPRD_EFUSE_ERR_FLAG     0x24
0015 #define SPRD_EFUSE_ERR_CLR      0x28
0016 #define SPRD_EFUSE_MAGIC_NUM        0x2c
0017 #define SPRD_EFUSE_FW_CFG       0x50
0018 #define SPRD_EFUSE_PW_SWT       0x54
0019 #define SPRD_EFUSE_MEM(val)     (0x1000 + ((val) << 2))
0020
0021 #define SPRD_EFUSE_VDD_EN       BIT(0)
0022 #define SPRD_EFUSE_AUTO_CHECK_EN    BIT(1)
0023 #define SPRD_EFUSE_DOUBLE_EN        BIT(2)
0024 #define SPRD_EFUSE_MARGIN_RD_EN     BIT(3)
0025 #define SPRD_EFUSE_LOCK_WR_EN       BIT(4)
0026
0027 #define SPRD_EFUSE_ERR_CLR_MASK     GENMASK(13, 0)
0028
0029 #define SPRD_EFUSE_ENK1_ON      BIT(0)
0030 #define SPRD_EFUSE_ENK2_ON      BIT(1)
0031 #define SPRD_EFUSE_PROG_EN      BIT(2)
0032
0033 #define SPRD_EFUSE_MAGIC_NUMBER     0x8810
0034
0035 /* Block width (bytes) definitions */
0036 #define SPRD_EFUSE_BLOCK_WIDTH      4
0037
0038 /*
0039  * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
0040  * and we can only access the normal efuse in kernel. So define the normal
0041  * block offset index and normal block numbers.
0042  */
0043 #define SPRD_EFUSE_NORMAL_BLOCK_NUMS    24
0044 #define SPRD_EFUSE_NORMAL_BLOCK_OFFSET  72
0045
0046 /* Timeout (ms) for the trylock of hardware spinlocks */
0047 #define SPRD_EFUSE_HWLOCK_TIMEOUT   5000
0048
0049 /*
0050  * Since different Spreadtrum SoC chip can have different normal block numbers
0051  * and offset. And some SoC can support block double feature, which means
0052  * when reading or writing data to efuse memory, the controller can save double
0053  * data in case one data become incorrect after a long period.
0054  *
0055  * Thus we should save them in the device data structure.
0056  */
0057 struct sprd_efuse_variant_data {
0058     u32 blk_nums;
0059     u32 blk_offset;
0060     bool blk_double;
0061 };
0062
0063 struct sprd_efuse {
0064     struct device *dev;
0065     struct clk *clk;
0066     struct hwspinlock *hwlock;
0067     struct mutex mutex;
0068     void __iomem *base;
0069     const struct sprd_efuse_variant_data *data;
0070 };
0071
0072 static const struct sprd_efuse_variant_data ums312_data = {
0073     .blk_nums = SPRD_EFUSE_NORMAL_BLOCK_NUMS,
0074     .blk_offset = SPRD_EFUSE_NORMAL_BLOCK_OFFSET,
0075     .blk_double = false,
0076 };
0077
0078 /*
0079  * On Spreadtrum platform, we have multi-subsystems will access the unique
0080  * efuse controller, so we need one hardware spinlock to synchronize between
0081  * the multiple subsystems.
0082  */
0083 static int sprd_efuse_lock(struct sprd_efuse *efuse)
0084 {
0085     int ret;
0086
0087     mutex_lock(&efuse->mutex);
0088
0089     ret = hwspin_lock_timeout_raw(efuse->hwlock,
0090                       SPRD_EFUSE_HWLOCK_TIMEOUT);
0091     if (ret) {
0092         dev_err(efuse->dev, "timeout get the hwspinlock\n");
0093         mutex_unlock(&efuse->mutex);
0094         return ret;
0095     }
0096
0097     return 0;
0098 }
0099
0100 static void sprd_efuse_unlock(struct sprd_efuse *efuse)
0101 {
0102     hwspin_unlock_raw(efuse->hwlock);
0103     mutex_unlock(&efuse->mutex);
0104 }
0105
0106 static void sprd_efuse_set_prog_power(struct sprd_efuse *efuse, bool en)
0107 {
0108     u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
0109
0110     if (en)
0111         val &= ~SPRD_EFUSE_ENK2_ON;
0112     else
0113         val &= ~SPRD_EFUSE_ENK1_ON;
0114
0115     writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
0116
0117     /* Open or close efuse power need wait 1000us to make power stable. */
0118     usleep_range(1000, 1200);
0119
0120     if (en)
0121         val |= SPRD_EFUSE_ENK1_ON;
0122     else
0123         val |= SPRD_EFUSE_ENK2_ON;
0124
0125     writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
0126
0127     /* Open or close efuse power need wait 1000us to make power stable. */
0128     usleep_range(1000, 1200);
0129 }
0130
0131 static void sprd_efuse_set_read_power(struct sprd_efuse *efuse, bool en)
0132 {
0133     u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
0134
0135     if (en)
0136         val |= SPRD_EFUSE_VDD_EN;
0137     else
0138         val &= ~SPRD_EFUSE_VDD_EN;
0139
0140     writel(val, efuse->base + SPRD_EFUSE_ENABLE);
0141
0142     /* Open or close efuse power need wait 1000us to make power stable. */
0143     usleep_range(1000, 1200);
0144 }
0145
0146 static void sprd_efuse_set_prog_lock(struct sprd_efuse *efuse, bool en)
0147 {
0148     u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
0149
0150     if (en)
0151         val |= SPRD_EFUSE_LOCK_WR_EN;
0152     else
0153         val &= ~SPRD_EFUSE_LOCK_WR_EN;
0154
0155     writel(val, efuse->base + SPRD_EFUSE_ENABLE);
0156 }
0157
0158 static void sprd_efuse_set_auto_check(struct sprd_efuse *efuse, bool en)
0159 {
0160     u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
0161
0162     if (en)
0163         val |= SPRD_EFUSE_AUTO_CHECK_EN;
0164     else
0165         val &= ~SPRD_EFUSE_AUTO_CHECK_EN;
0166
0167     writel(val, efuse->base + SPRD_EFUSE_ENABLE);
0168 }
0169
0170 static void sprd_efuse_set_data_double(struct sprd_efuse *efuse, bool en)
0171 {
0172     u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
0173
0174     if (en)
0175         val |= SPRD_EFUSE_DOUBLE_EN;
0176     else
0177         val &= ~SPRD_EFUSE_DOUBLE_EN;
0178
0179     writel(val, efuse->base + SPRD_EFUSE_ENABLE);
0180 }
0181
0182 static void sprd_efuse_set_prog_en(struct sprd_efuse *efuse, bool en)
0183 {
0184     u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
0185
0186     if (en)
0187         val |= SPRD_EFUSE_PROG_EN;
0188     else
0189         val &= ~SPRD_EFUSE_PROG_EN;
0190
0191     writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
0192 }
0193
0194 static int sprd_efuse_raw_prog(struct sprd_efuse *efuse, u32 blk, bool doub,
0195                    bool lock, u32 *data)
0196 {
0197     u32 status;
0198     int ret = 0;
0199
0200     /*
0201      * We need set the correct magic number before writing the efuse to
0202      * allow programming, and block other programming until we clear the
0203      * magic number.
0204      */
0205     writel(SPRD_EFUSE_MAGIC_NUMBER,
0206            efuse->base + SPRD_EFUSE_MAGIC_NUM);
0207
0208     /*
0209      * Power on the efuse, enable programme and enable double data
0210      * if asked.
0211      */
0212     sprd_efuse_set_prog_power(efuse, true);
0213     sprd_efuse_set_prog_en(efuse, true);
0214     sprd_efuse_set_data_double(efuse, doub);
0215
0216     /*
0217      * Enable the auto-check function to validate if the programming is
0218      * successful.
0219      */
0220     if (lock)
0221         sprd_efuse_set_auto_check(efuse, true);
0222
0223     writel(*data, efuse->base + SPRD_EFUSE_MEM(blk));
0224
0225     /* Disable auto-check and data double after programming */
0226     if (lock)
0227         sprd_efuse_set_auto_check(efuse, false);
0228     sprd_efuse_set_data_double(efuse, false);
0229
0230     /*
0231      * Check the efuse error status, if the programming is successful,
0232      * we should lock this efuse block to avoid programming again.
0233      */
0234     status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
0235     if (status) {
0236         dev_err(efuse->dev,
0237             "write error status %u of block %d\n", status, blk);
0238
0239         writel(SPRD_EFUSE_ERR_CLR_MASK,
0240                efuse->base + SPRD_EFUSE_ERR_CLR);
0241         ret = -EBUSY;
0242     } else if (lock) {
0243         sprd_efuse_set_prog_lock(efuse, lock);
0244         writel(0, efuse->base + SPRD_EFUSE_MEM(blk));
0245         sprd_efuse_set_prog_lock(efuse, false);
0246     }
0247
0248     sprd_efuse_set_prog_power(efuse, false);
0249     writel(0, efuse->base + SPRD_EFUSE_MAGIC_NUM);
0250
0251     return ret;
0252 }
0253
0254 static int sprd_efuse_raw_read(struct sprd_efuse *efuse, int blk, u32 *val,
0255                    bool doub)
0256 {
0257     u32 status;
0258
0259     /*
0260      * Need power on the efuse before reading data from efuse, and will
0261      * power off the efuse after reading process.
0262      */
0263     sprd_efuse_set_read_power(efuse, true);
0264
0265     /* Enable double data if asked */
0266     sprd_efuse_set_data_double(efuse, doub);
0267
0268     /* Start to read data from efuse block */
0269     *val = readl(efuse->base + SPRD_EFUSE_MEM(blk));
0270
0271     /* Disable double data */
0272     sprd_efuse_set_data_double(efuse, false);
0273
0274     /* Power off the efuse */
0275     sprd_efuse_set_read_power(efuse, false);
0276
0277     /*
0278      * Check the efuse error status and clear them if there are some
0279      * errors occurred.
0280      */
0281     status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
0282     if (status) {
0283         dev_err(efuse->dev,
0284             "read error status %d of block %d\n", status, blk);
0285
0286         writel(SPRD_EFUSE_ERR_CLR_MASK,
0287                efuse->base + SPRD_EFUSE_ERR_CLR);
0288         return -EBUSY;
0289     }
0290
0291     return 0;
0292 }
0293
0294 static int sprd_efuse_read(void *context, u32 offset, void *val, size_t bytes)
0295 {
0296     struct sprd_efuse *efuse = context;
0297     bool blk_double = efuse->data->blk_double;
0298     u32 index = offset / SPRD_EFUSE_BLOCK_WIDTH + efuse->data->blk_offset;
0299     u32 blk_offset = (offset % SPRD_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
0300     u32 data;
0301     int ret;
0302
0303     ret = sprd_efuse_lock(efuse);
0304     if (ret)
0305         return ret;
0306
0307     ret = clk_prepare_enable(efuse->clk);
0308     if (ret)
0309         goto unlock;
0310
0311     ret = sprd_efuse_raw_read(efuse, index, &data, blk_double);
0312     if (!ret) {
0313         data >>= blk_offset;
0314         memcpy(val, &data, bytes);
0315     }
0316
0317     clk_disable_unprepare(efuse->clk);
0318
0319 unlock:
0320     sprd_efuse_unlock(efuse);
0321     return ret;
0322 }
0323
0324 static int sprd_efuse_write(void *context, u32 offset, void *val, size_t bytes)
0325 {
0326     struct sprd_efuse *efuse = context;
0327     bool blk_double = efuse->data->blk_double;
0328     bool lock;
0329     int ret;
0330
0331     ret = sprd_efuse_lock(efuse);
0332     if (ret)
0333         return ret;
0334
0335     ret = clk_prepare_enable(efuse->clk);
0336     if (ret)
0337         goto unlock;
0338
0339     /*
0340      * If the writing bytes are equal with the block width, which means the
0341      * whole block will be programmed. For this case, we should not allow
0342      * this block to be programmed again by locking this block.
0343      *
0344      * If the block was programmed partially, we should allow this block to
0345      * be programmed again.
0346      */
0347     if (bytes < SPRD_EFUSE_BLOCK_WIDTH)
0348         lock = false;
0349     else
0350         lock = true;
0351
0352     ret = sprd_efuse_raw_prog(efuse, offset, blk_double, lock, val);
0353
0354     clk_disable_unprepare(efuse->clk);
0355
0356 unlock:
0357     sprd_efuse_unlock(efuse);
0358     return ret;
0359 }
0360
0361 static int sprd_efuse_probe(struct platform_device *pdev)
0362 {
0363     struct device_node *np = pdev->dev.of_node;
0364     struct nvmem_device *nvmem;
0365     struct nvmem_config econfig = { };
0366     struct sprd_efuse *efuse;
0367     const struct sprd_efuse_variant_data *pdata;
0368     int ret;
0369
0370     pdata = of_device_get_match_data(&pdev->dev);
0371     if (!pdata) {
0372         dev_err(&pdev->dev, "No matching driver data found\n");
0373         return -EINVAL;
0374     }
0375
0376     efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
0377     if (!efuse)
0378         return -ENOMEM;
0379
0380     efuse->base = devm_platform_ioremap_resource(pdev, 0);
0381     if (IS_ERR(efuse->base))
0382         return PTR_ERR(efuse->base);
0383
0384     ret = of_hwspin_lock_get_id(np, 0);
0385     if (ret < 0) {
0386         dev_err(&pdev->dev, "failed to get hwlock id\n");
0387         return ret;
0388     }
0389
0390     efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
0391     if (!efuse->hwlock) {
0392         dev_err(&pdev->dev, "failed to request hwlock\n");
0393         return -ENXIO;
0394     }
0395
0396     efuse->clk = devm_clk_get(&pdev->dev, "enable");
0397     if (IS_ERR(efuse->clk)) {
0398         dev_err(&pdev->dev, "failed to get enable clock\n");
0399         return PTR_ERR(efuse->clk);
0400     }
0401
0402     mutex_init(&efuse->mutex);
0403     efuse->dev = &pdev->dev;
0404     efuse->data = pdata;
0405
0406     econfig.stride = 1;
0407     econfig.word_size = 1;
0408     econfig.read_only = false;
0409     econfig.name = "sprd-efuse";
0410     econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH;
0411     econfig.reg_read = sprd_efuse_read;
0412     econfig.reg_write = sprd_efuse_write;
0413     econfig.priv = efuse;
0414     econfig.dev = &pdev->dev;
0415     nvmem = devm_nvmem_register(&pdev->dev, &econfig);
0416     if (IS_ERR(nvmem)) {
0417         dev_err(&pdev->dev, "failed to register nvmem\n");
0418         return PTR_ERR(nvmem);
0419     }
0420
0421     return 0;
0422 }
0423
0424 static const struct of_device_id sprd_efuse_of_match[] = {
0425     { .compatible = "sprd,ums312-efuse", .data = &ums312_data },
0426     { }
0427 };
0428
0429 static struct platform_driver sprd_efuse_driver = {
0430     .probe = sprd_efuse_probe,
0431     .driver = {
0432         .name = "sprd-efuse",
0433         .of_match_table = sprd_efuse_of_match,
0434     },
0435 };
0436
0437 module_platform_driver(sprd_efuse_driver);
0438
0439 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
0440 MODULE_DESCRIPTION("Spreadtrum AP efuse driver");
0441 MODULE_LICENSE("GPL v2");