drivers/nvmem/bcm-ocotp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2016 Broadcom
0003
0004 #include <linux/acpi.h>
0005 #include <linux/delay.h>
0006 #include <linux/device.h>
0007 #include <linux/io.h>
0008 #include <linux/module.h>
0009 #include <linux/nvmem-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 /*
0015  * # of tries for OTP Status. The time to execute a command varies. The slowest
0016  * commands are writes which also vary based on the # of bits turned on. Writing
0017  * 0xffffffff takes ~3800 us.
0018  */
0019 #define OTPC_RETRIES                 5000
0020
0021 /* Sequence to enable OTP program */
0022 #define OTPC_PROG_EN_SEQ             { 0xf, 0x4, 0x8, 0xd }
0023
0024 /* OTPC Commands */
0025 #define OTPC_CMD_READ                0x0
0026 #define OTPC_CMD_OTP_PROG_ENABLE     0x2
0027 #define OTPC_CMD_OTP_PROG_DISABLE    0x3
0028 #define OTPC_CMD_PROGRAM             0x8
0029
0030 /* OTPC Status Bits */
0031 #define OTPC_STAT_CMD_DONE           BIT(1)
0032 #define OTPC_STAT_PROG_OK            BIT(2)
0033
0034 /* OTPC register definition */
0035 #define OTPC_MODE_REG_OFFSET         0x0
0036 #define OTPC_MODE_REG_OTPC_MODE      0
0037 #define OTPC_COMMAND_OFFSET          0x4
0038 #define OTPC_COMMAND_COMMAND_WIDTH   6
0039 #define OTPC_CMD_START_OFFSET        0x8
0040 #define OTPC_CMD_START_START         0
0041 #define OTPC_CPU_STATUS_OFFSET       0xc
0042 #define OTPC_CPUADDR_REG_OFFSET      0x28
0043 #define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
0044 #define OTPC_CPU_WRITE_REG_OFFSET    0x2c
0045
0046 #define OTPC_CMD_MASK  (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
0047 #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
0048
0049
0050 struct otpc_map {
0051     /* in words. */
0052     u32 otpc_row_size;
0053     /* 128 bit row / 4 words support. */
0054     u16 data_r_offset[4];
0055     /* 128 bit row / 4 words support. */
0056     u16 data_w_offset[4];
0057 };
0058
0059 static struct otpc_map otp_map = {
0060     .otpc_row_size = 1,
0061     .data_r_offset = {0x10},
0062     .data_w_offset = {0x2c},
0063 };
0064
0065 static struct otpc_map otp_map_v2 = {
0066     .otpc_row_size = 2,
0067     .data_r_offset = {0x10, 0x5c},
0068     .data_w_offset = {0x2c, 0x64},
0069 };
0070
0071 struct otpc_priv {
0072     struct device *dev;
0073     void __iomem *base;
0074     const struct otpc_map *map;
0075     struct nvmem_config *config;
0076 };
0077
0078 static inline void set_command(void __iomem *base, u32 command)
0079 {
0080     writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
0081 }
0082
0083 static inline void set_cpu_address(void __iomem *base, u32 addr)
0084 {
0085     writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
0086 }
0087
0088 static inline void set_start_bit(void __iomem *base)
0089 {
0090     writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
0091 }
0092
0093 static inline void reset_start_bit(void __iomem *base)
0094 {
0095     writel(0, base + OTPC_CMD_START_OFFSET);
0096 }
0097
0098 static inline void write_cpu_data(void __iomem *base, u32 value)
0099 {
0100     writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
0101 }
0102
0103 static int poll_cpu_status(void __iomem *base, u32 value)
0104 {
0105     u32 status;
0106     u32 retries;
0107
0108     for (retries = 0; retries < OTPC_RETRIES; retries++) {
0109         status = readl(base + OTPC_CPU_STATUS_OFFSET);
0110         if (status & value)
0111             break;
0112         udelay(1);
0113     }
0114     if (retries == OTPC_RETRIES)
0115         return -EAGAIN;
0116
0117     return 0;
0118 }
0119
0120 static int enable_ocotp_program(void __iomem *base)
0121 {
0122     static const u32 vals[] = OTPC_PROG_EN_SEQ;
0123     int i;
0124     int ret;
0125
0126     /* Write the magic sequence to enable programming */
0127     set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
0128     for (i = 0; i < ARRAY_SIZE(vals); i++) {
0129         write_cpu_data(base, vals[i]);
0130         set_start_bit(base);
0131         ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
0132         reset_start_bit(base);
0133         if (ret)
0134             return ret;
0135     }
0136
0137     return poll_cpu_status(base, OTPC_STAT_PROG_OK);
0138 }
0139
0140 static int disable_ocotp_program(void __iomem *base)
0141 {
0142     int ret;
0143
0144     set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
0145     set_start_bit(base);
0146     ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
0147     reset_start_bit(base);
0148
0149     return ret;
0150 }
0151
0152 static int bcm_otpc_read(void *context, unsigned int offset, void *val,
0153     size_t bytes)
0154 {
0155     struct otpc_priv *priv = context;
0156     u32 *buf = val;
0157     u32 bytes_read;
0158     u32 address = offset / priv->config->word_size;
0159     int i, ret;
0160
0161     for (bytes_read = 0; bytes_read < bytes;) {
0162         set_command(priv->base, OTPC_CMD_READ);
0163         set_cpu_address(priv->base, address++);
0164         set_start_bit(priv->base);
0165         ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
0166         if (ret) {
0167             dev_err(priv->dev, "otp read error: 0x%x", ret);
0168             return -EIO;
0169         }
0170
0171         for (i = 0; i < priv->map->otpc_row_size; i++) {
0172             *buf++ = readl(priv->base +
0173                     priv->map->data_r_offset[i]);
0174             bytes_read += sizeof(*buf);
0175         }
0176
0177         reset_start_bit(priv->base);
0178     }
0179
0180     return 0;
0181 }
0182
0183 static int bcm_otpc_write(void *context, unsigned int offset, void *val,
0184     size_t bytes)
0185 {
0186     struct otpc_priv *priv = context;
0187     u32 *buf = val;
0188     u32 bytes_written;
0189     u32 address = offset / priv->config->word_size;
0190     int i, ret;
0191
0192     if (offset % priv->config->word_size)
0193         return -EINVAL;
0194
0195     ret = enable_ocotp_program(priv->base);
0196     if (ret)
0197         return -EIO;
0198
0199     for (bytes_written = 0; bytes_written < bytes;) {
0200         set_command(priv->base, OTPC_CMD_PROGRAM);
0201         set_cpu_address(priv->base, address++);
0202         for (i = 0; i < priv->map->otpc_row_size; i++) {
0203             writel(*buf, priv->base + priv->map->data_w_offset[i]);
0204             buf++;
0205             bytes_written += sizeof(*buf);
0206         }
0207         set_start_bit(priv->base);
0208         ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
0209         reset_start_bit(priv->base);
0210         if (ret) {
0211             dev_err(priv->dev, "otp write error: 0x%x", ret);
0212             return -EIO;
0213         }
0214     }
0215
0216     disable_ocotp_program(priv->base);
0217
0218     return 0;
0219 }
0220
0221 static struct nvmem_config bcm_otpc_nvmem_config = {
0222     .name = "bcm-ocotp",
0223     .read_only = false,
0224     .word_size = 4,
0225     .stride = 4,
0226     .reg_read = bcm_otpc_read,
0227     .reg_write = bcm_otpc_write,
0228 };
0229
0230 static const struct of_device_id bcm_otpc_dt_ids[] = {
0231     { .compatible = "brcm,ocotp", .data = &otp_map },
0232     { .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
0233     { },
0234 };
0235 MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
0236
0237 static const struct acpi_device_id bcm_otpc_acpi_ids[] __maybe_unused = {
0238     { .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
0239     { .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
0240     { /* sentinel */ }
0241 };
0242 MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
0243
0244 static int bcm_otpc_probe(struct platform_device *pdev)
0245 {
0246     struct device *dev = &pdev->dev;
0247     struct resource *res;
0248     struct otpc_priv *priv;
0249     struct nvmem_device *nvmem;
0250     int err;
0251     u32 num_words;
0252
0253     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0254     if (!priv)
0255         return -ENOMEM;
0256
0257     priv->map = device_get_match_data(dev);
0258     if (!priv->map)
0259         return -ENODEV;
0260
0261     /* Get OTP base address register. */
0262     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0263     priv->base = devm_ioremap_resource(dev, res);
0264     if (IS_ERR(priv->base)) {
0265         dev_err(dev, "unable to map I/O memory\n");
0266         return PTR_ERR(priv->base);
0267     }
0268
0269     /* Enable CPU access to OTPC. */
0270     writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
0271         BIT(OTPC_MODE_REG_OTPC_MODE),
0272         priv->base + OTPC_MODE_REG_OFFSET);
0273     reset_start_bit(priv->base);
0274
0275     /* Read size of memory in words. */
0276     err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
0277     if (err) {
0278         dev_err(dev, "size parameter not specified\n");
0279         return -EINVAL;
0280     } else if (num_words == 0) {
0281         dev_err(dev, "size must be > 0\n");
0282         return -EINVAL;
0283     }
0284
0285     bcm_otpc_nvmem_config.size = 4 * num_words;
0286     bcm_otpc_nvmem_config.dev = dev;
0287     bcm_otpc_nvmem_config.priv = priv;
0288
0289     if (priv->map == &otp_map_v2) {
0290         bcm_otpc_nvmem_config.word_size = 8;
0291         bcm_otpc_nvmem_config.stride = 8;
0292     }
0293
0294     priv->config = &bcm_otpc_nvmem_config;
0295
0296     nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
0297     if (IS_ERR(nvmem)) {
0298         dev_err(dev, "error registering nvmem config\n");
0299         return PTR_ERR(nvmem);
0300     }
0301
0302     return 0;
0303 }
0304
0305 static struct platform_driver bcm_otpc_driver = {
0306     .probe  = bcm_otpc_probe,
0307     .driver = {
0308         .name   = "brcm-otpc",
0309         .of_match_table = bcm_otpc_dt_ids,
0310         .acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
0311     },
0312 };
0313 module_platform_driver(bcm_otpc_driver);
0314
0315 MODULE_DESCRIPTION("Broadcom OTPC driver");
0316 MODULE_LICENSE("GPL v2");