hw/intel/ntb_hw_intel.h

0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  *   redistributing this file, you may do so under either license.
0004  *
0005  *   GPL LICENSE SUMMARY
0006  *
0007  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
0008  *   Copyright (C) 2015 EMC Corporation. All Rights Reserved.
0009  *
0010  *   This program is free software; you can redistribute it and/or modify
0011  *   it under the terms of version 2 of the GNU General Public License as
0012  *   published by the Free Software Foundation.
0013  *
0014  *   BSD LICENSE
0015  *
0016  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
0017  *   Copyright (C) 2015 EMC Corporation. All Rights Reserved.
0018  *
0019  *   Redistribution and use in source and binary forms, with or without
0020  *   modification, are permitted provided that the following conditions
0021  *   are met:
0022  *
0023  *     * Redistributions of source code must retain the above copyright
0024  *       notice, this list of conditions and the following disclaimer.
0025  *     * Redistributions in binary form must reproduce the above copy
0026  *       notice, this list of conditions and the following disclaimer in
0027  *       the documentation and/or other materials provided with the
0028  *       distribution.
0029  *     * Neither the name of Intel Corporation nor the names of its
0030  *       contributors may be used to endorse or promote products derived
0031  *       from this software without specific prior written permission.
0032  *
0033  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0034  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0035  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0036  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0037  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0038  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0039  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0040  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0041  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0043  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * Intel PCIe NTB Linux driver
0046  */
0047
0048 #ifndef NTB_HW_INTEL_H
0049 #define NTB_HW_INTEL_H
0050
0051 #include <linux/ntb.h>
0052 #include <linux/pci.h>
0053 #include <linux/io-64-nonatomic-lo-hi.h>
0054
0055 /* PCI device IDs */
0056 #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
0057 #define PCI_DEVICE_ID_INTEL_NTB_PS_JSF  0x3726
0058 #define PCI_DEVICE_ID_INTEL_NTB_SS_JSF  0x3727
0059 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
0060 #define PCI_DEVICE_ID_INTEL_NTB_PS_SNB  0x3C0E
0061 #define PCI_DEVICE_ID_INTEL_NTB_SS_SNB  0x3C0F
0062 #define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
0063 #define PCI_DEVICE_ID_INTEL_NTB_PS_IVT  0x0E0E
0064 #define PCI_DEVICE_ID_INTEL_NTB_SS_IVT  0x0E0F
0065 #define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
0066 #define PCI_DEVICE_ID_INTEL_NTB_PS_HSX  0x2F0E
0067 #define PCI_DEVICE_ID_INTEL_NTB_SS_HSX  0x2F0F
0068 #define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
0069 #define PCI_DEVICE_ID_INTEL_NTB_PS_BDX  0x6F0E
0070 #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX  0x6F0F
0071 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
0072 #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
0073 #define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
0074
0075 /* Ntb control and link status */
0076 #define NTB_CTL_CFG_LOCK        BIT(0)
0077 #define NTB_CTL_DISABLE         BIT(1)
0078 #define NTB_CTL_S2P_BAR2_SNOOP      BIT(2)
0079 #define NTB_CTL_P2S_BAR2_SNOOP      BIT(4)
0080 #define NTB_CTL_S2P_BAR4_SNOOP      BIT(6)
0081 #define NTB_CTL_P2S_BAR4_SNOOP      BIT(8)
0082 #define NTB_CTL_S2P_BAR5_SNOOP      BIT(12)
0083 #define NTB_CTL_P2S_BAR5_SNOOP      BIT(14)
0084
0085 #define NTB_LNK_STA_ACTIVE_BIT      0x2000
0086 #define NTB_LNK_STA_SPEED_MASK      0x000f
0087 #define NTB_LNK_STA_WIDTH_MASK      0x03f0
0088 #define NTB_LNK_STA_ACTIVE(x)       (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
0089 #define NTB_LNK_STA_SPEED(x)        ((x) & NTB_LNK_STA_SPEED_MASK)
0090 #define NTB_LNK_STA_WIDTH(x)        (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
0091
0092 /* flags to indicate unsafe api */
0093 #define NTB_UNSAFE_DB           BIT_ULL(0)
0094 #define NTB_UNSAFE_SPAD         BIT_ULL(1)
0095
0096 #define NTB_BAR_MASK_64         ~(0xfull)
0097 #define NTB_BAR_MASK_32         ~(0xfu)
0098
0099 struct intel_ntb_dev;
0100
0101 struct intel_ntb_reg {
0102     int (*poll_link)(struct intel_ntb_dev *ndev);
0103     int (*link_is_up)(struct intel_ntb_dev *ndev);
0104     u64 (*db_ioread)(const void __iomem *mmio);
0105     void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
0106     unsigned long           ntb_ctl;
0107     resource_size_t         db_size;
0108     int             mw_bar[];
0109 };
0110
0111 struct intel_ntb_alt_reg {
0112     unsigned long           db_bell;
0113     unsigned long           db_mask;
0114     unsigned long           db_clear;
0115     unsigned long           spad;
0116 };
0117
0118 struct intel_ntb_xlat_reg {
0119     unsigned long           bar0_base;
0120     unsigned long           bar2_xlat;
0121     unsigned long           bar2_limit;
0122     unsigned short          bar2_idx;
0123 };
0124
0125 struct intel_b2b_addr {
0126     phys_addr_t         bar0_addr;
0127     phys_addr_t         bar2_addr64;
0128     phys_addr_t         bar4_addr64;
0129     phys_addr_t         bar4_addr32;
0130     phys_addr_t         bar5_addr32;
0131 };
0132
0133 struct intel_ntb_vec {
0134     struct intel_ntb_dev        *ndev;
0135     int             num;
0136 };
0137
0138 struct intel_ntb_dev {
0139     struct ntb_dev          ntb;
0140
0141     /* offset of peer bar0 in b2b bar */
0142     unsigned long           b2b_off;
0143     /* mw idx used to access peer bar0 */
0144     unsigned int            b2b_idx;
0145
0146     /* BAR45 is split into BAR4 and BAR5 */
0147     bool                bar4_split;
0148
0149     u32             ntb_ctl;
0150     u32             lnk_sta;
0151
0152     unsigned char           mw_count;
0153     unsigned char           spad_count;
0154     unsigned char           db_count;
0155     unsigned char           db_vec_count;
0156     unsigned char           db_vec_shift;
0157
0158     u64             db_valid_mask;
0159     u64             db_link_mask;
0160     u64             db_mask;
0161
0162     /* synchronize rmw access of db_mask and hw reg */
0163     spinlock_t          db_mask_lock;
0164
0165     struct msix_entry       *msix;
0166     struct intel_ntb_vec        *vec;
0167
0168     const struct intel_ntb_reg  *reg;
0169     const struct intel_ntb_alt_reg  *self_reg;
0170     const struct intel_ntb_alt_reg  *peer_reg;
0171     const struct intel_ntb_xlat_reg *xlat_reg;
0172     void                __iomem *self_mmio;
0173     void                __iomem *peer_mmio;
0174     phys_addr_t         peer_addr;
0175
0176     unsigned long           last_ts;
0177     struct delayed_work     hb_timer;
0178
0179     unsigned long           hwerr_flags;
0180     unsigned long           unsafe_flags;
0181     unsigned long           unsafe_flags_ignore;
0182
0183     struct dentry           *debugfs_dir;
0184     struct dentry           *debugfs_info;
0185
0186     /* gen4 entries */
0187     int             dev_up;
0188 };
0189
0190 #define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
0191 #define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
0192                      hb_timer.work)
0193
0194 static inline int pdev_is_gen1(struct pci_dev *pdev)
0195 {
0196     switch (pdev->device) {
0197     case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
0198     case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
0199     case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
0200     case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
0201     case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
0202     case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
0203     case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
0204     case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
0205     case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
0206     case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
0207     case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
0208     case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
0209     case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
0210     case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
0211     case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
0212         return 1;
0213     }
0214     return 0;
0215 }
0216
0217 static inline int pdev_is_gen3(struct pci_dev *pdev)
0218 {
0219     if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
0220         return 1;
0221
0222     return 0;
0223 }
0224
0225 static inline int pdev_is_gen4(struct pci_dev *pdev)
0226 {
0227     if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
0228         return 1;
0229
0230     return 0;
0231 }
0232
0233 static inline int pdev_is_gen5(struct pci_dev *pdev)
0234 {
0235     return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
0236 }
0237
0238 #endif