hw/intel/ntb_hw_gen4.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)          */
0002 /* Copyright(c) 2020 Intel Corporation. All rights reserved.   */
0003 #ifndef _NTB_INTEL_GEN4_H_
0004 #define _NTB_INTEL_GEN4_H_
0005
0006 #include "ntb_hw_intel.h"
0007
0008 /* Supported PCI device revision range for ICX */
0009 #define PCI_DEVICE_REVISION_ICX_MIN 0x2
0010 #define PCI_DEVICE_REVISION_ICX_MAX 0xF
0011
0012 /* Intel Gen4 NTB hardware */
0013 /* PCIe config space */
0014 #define GEN4_IMBAR23SZ_OFFSET       0x00c4
0015 #define GEN4_IMBAR45SZ_OFFSET       0x00c5
0016 #define GEN4_EMBAR23SZ_OFFSET       0x00c6
0017 #define GEN4_EMBAR45SZ_OFFSET       0x00c7
0018 #define GEN4_DEVCTRL_OFFSET     0x0048
0019 #define GEN4_DEVSTS_OFFSET      0x004a
0020 #define GEN4_UNCERRSTS_OFFSET       0x0104
0021 #define GEN4_CORERRSTS_OFFSET       0x0110
0022
0023 /* BAR0 MMIO */
0024 #define GEN4_NTBCNTL_OFFSET     0x0000
0025 #define GEN4_IM23XBASE_OFFSET       0x0010  /* IMBAR1XBASE */
0026 #define GEN4_IM23XLMT_OFFSET        0x0018  /* IMBAR1XLMT */
0027 #define GEN4_IM45XBASE_OFFSET       0x0020  /* IMBAR2XBASE */
0028 #define GEN4_IM45XLMT_OFFSET        0x0028  /* IMBAR2XLMT */
0029 #define GEN4_IM_INT_STATUS_OFFSET   0x0040
0030 #define GEN4_IM_INT_DISABLE_OFFSET  0x0048
0031 #define GEN4_INTVEC_OFFSET      0x0050  /* 0-32 vecs */
0032 #define GEN4_IM23XBASEIDX_OFFSET    0x0074
0033 #define GEN4_IM45XBASEIDX_OFFSET    0x0076
0034 #define GEN4_IM_SPAD_OFFSET     0x0080  /* 0-15 SPADs */
0035 #define GEN4_IM_SPAD_SEM_OFFSET     0x00c0  /* SPAD hw semaphore */
0036 #define GEN4_IM_SPAD_STICKY_OFFSET  0x00c4  /* sticky SPAD */
0037 #define GEN4_IM_DOORBELL_OFFSET     0x0100  /* 0-31 doorbells */
0038 #define GEN4_LTR_SWSEL_OFFSET       0x30ec
0039 #define GEN4_LTR_ACTIVE_OFFSET      0x30f0
0040 #define GEN4_LTR_IDLE_OFFSET        0x30f4
0041 #define GEN4_EM_SPAD_OFFSET     0x8080
0042 /* note, link status is now in MMIO and not config space for NTB */
0043 #define GEN4_LINK_CTRL_OFFSET       0xb050
0044 #define GEN4_LINK_STATUS_OFFSET     0xb052
0045 #define GEN4_PPD0_OFFSET        0xb0d4
0046 #define GEN4_PPD1_OFFSET        0xb4c0
0047 #define GEN4_LTSSMSTATEJMP      0xf040
0048
0049 #define GEN4_PPD_CLEAR_TRN      0x0001
0050 #define GEN4_PPD_LINKTRN        0x0008
0051 #define GEN4_PPD_CONN_MASK      0x0300
0052 #define SPR_PPD_CONN_MASK       0x0700
0053 #define GEN4_PPD_CONN_B2B       0x0200
0054 #define GEN4_PPD_DEV_MASK       0x1000
0055 #define GEN4_PPD_DEV_DSD        0x1000
0056 #define GEN4_PPD_DEV_USD        0x0000
0057 #define SPR_PPD_DEV_MASK        0x4000
0058 #define SPR_PPD_DEV_DSD         0x4000
0059 #define SPR_PPD_DEV_USD         0x0000
0060 #define GEN4_LINK_CTRL_LINK_DISABLE 0x0010
0061
0062 #define GEN4_SLOTSTS            0xb05a
0063 #define GEN4_SLOTSTS_DLLSCS     0x100
0064
0065 #define GEN4_PPD_TOPO_MASK  (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK)
0066 #define GEN4_PPD_TOPO_B2B_USD   (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD)
0067 #define GEN4_PPD_TOPO_B2B_DSD   (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD)
0068
0069 #define SPR_PPD_TOPO_MASK   (SPR_PPD_CONN_MASK | SPR_PPD_DEV_MASK)
0070 #define SPR_PPD_TOPO_B2B_USD    (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_USD)
0071 #define SPR_PPD_TOPO_B2B_DSD    (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_DSD)
0072
0073 #define GEN4_DB_COUNT           32
0074 #define GEN4_DB_LINK            32
0075 #define GEN4_DB_LINK_BIT        BIT_ULL(GEN4_DB_LINK)
0076 #define GEN4_DB_MSIX_VECTOR_COUNT   33
0077 #define GEN4_DB_MSIX_VECTOR_SHIFT   1
0078 #define GEN4_DB_TOTAL_SHIFT     33
0079 #define GEN4_SPAD_COUNT         16
0080
0081 #define NTB_CTL_E2I_BAR23_SNOOP     0x000004
0082 #define NTB_CTL_E2I_BAR23_NOSNOOP   0x000008
0083 #define NTB_CTL_I2E_BAR23_SNOOP     0x000010
0084 #define NTB_CTL_I2E_BAR23_NOSNOOP   0x000020
0085 #define NTB_CTL_E2I_BAR45_SNOOP     0x000040
0086 #define NTB_CTL_E2I_BAR45_NOSNOO    0x000080
0087 #define NTB_CTL_I2E_BAR45_SNOOP     0x000100
0088 #define NTB_CTL_I2E_BAR45_NOSNOOP   0x000200
0089 #define NTB_CTL_BUSNO_DIS_INC       0x000400
0090 #define NTB_CTL_LINK_DOWN       0x010000
0091
0092 #define NTB_SJC_FORCEDETECT     0x000004
0093
0094 #define NTB_LTR_SWSEL_ACTIVE        0x0
0095 #define NTB_LTR_SWSEL_IDLE      0x1
0096
0097 #define NTB_LTR_NS_SHIFT        16
0098 #define NTB_LTR_ACTIVE_VAL      0x0000  /* 0 us */
0099 #define NTB_LTR_ACTIVE_LATSCALE     0x0800  /* 1us scale */
0100 #define NTB_LTR_ACTIVE_REQMNT       0x8000  /* snoop req enable */
0101
0102 #define NTB_LTR_IDLE_VAL        0x0258  /* 600 us */
0103 #define NTB_LTR_IDLE_LATSCALE       0x0800  /* 1us scale */
0104 #define NTB_LTR_IDLE_REQMNT     0x8000  /* snoop req enable */
0105
0106 ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
0107                       size_t count, loff_t *offp);
0108 int gen4_init_dev(struct intel_ntb_dev *ndev);
0109 ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
0110                       size_t count, loff_t *offp);
0111
0112 extern const struct ntb_dev_ops intel_ntb4_ops;
0113
0114 static inline int pdev_is_ICX(struct pci_dev *pdev)
0115 {
0116     if (pdev_is_gen4(pdev) &&
0117         pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN &&
0118         pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX)
0119         return 1;
0120     return 0;
0121 }
0122
0123 static inline int pdev_is_SPR(struct pci_dev *pdev)
0124 {
0125     if (pdev_is_gen4(pdev) &&
0126         pdev->revision > PCI_DEVICE_REVISION_ICX_MAX)
0127         return 1;
0128     return 0;
0129 }
0130
0131 #endif