hw/intel/ntb_hw_gen3.h

0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  *   redistributing this file, you may do so under either license.
0004  *
0005  *   GPL LICENSE SUMMARY
0006  *
0007  *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
0008  *
0009  *   This program is free software; you can redistribute it and/or modify
0010  *   it under the terms of version 2 of the GNU General Public License as
0011  *   published by the Free Software Foundation.
0012  *
0013  *   BSD LICENSE
0014  *
0015  *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
0016  *
0017  *   Redistribution and use in source and binary forms, with or without
0018  *   modification, are permitted provided that the following conditions
0019  *   are met:
0020  *
0021  *     * Redistributions of source code must retain the above copyright
0022  *       notice, this list of conditions and the following disclaimer.
0023  *     * Redistributions in binary form must reproduce the above copy
0024  *       notice, this list of conditions and the following disclaimer in
0025  *       the documentation and/or other materials provided with the
0026  *       distribution.
0027  *     * Neither the name of Intel Corporation nor the names of its
0028  *       contributors may be used to endorse or promote products derived
0029  *       from this software without specific prior written permission.
0030  *
0031  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0032  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0033  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0034  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0035  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0036  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0037  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0038  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0039  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0040  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0041  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0042  */
0043
0044 #ifndef _NTB_INTEL_GEN3_H_
0045 #define _NTB_INTEL_GEN3_H_
0046
0047 #include "ntb_hw_intel.h"
0048
0049 /* Intel Skylake Xeon hardware */
0050 #define GEN3_IMBAR1SZ_OFFSET        0x00d0
0051 #define GEN3_IMBAR2SZ_OFFSET        0x00d1
0052 #define GEN3_EMBAR1SZ_OFFSET        0x00d2
0053 #define GEN3_EMBAR2SZ_OFFSET        0x00d3
0054 #define GEN3_DEVCTRL_OFFSET     0x0098
0055 #define GEN3_DEVSTS_OFFSET      0x009a
0056 #define GEN3_UNCERRSTS_OFFSET       0x014c
0057 #define GEN3_CORERRSTS_OFFSET       0x0158
0058 #define GEN3_LINK_STATUS_OFFSET     0x01a2
0059
0060 #define GEN3_NTBCNTL_OFFSET     0x0000
0061 #define GEN3_IMBAR1XBASE_OFFSET     0x0010      /* SBAR2XLAT */
0062 #define GEN3_IMBAR1XLMT_OFFSET      0x0018      /* SBAR2LMT */
0063 #define GEN3_IMBAR2XBASE_OFFSET     0x0020      /* SBAR4XLAT */
0064 #define GEN3_IMBAR2XLMT_OFFSET      0x0028      /* SBAR4LMT */
0065 #define GEN3_IM_INT_STATUS_OFFSET   0x0040
0066 #define GEN3_IM_INT_DISABLE_OFFSET  0x0048
0067 #define GEN3_IM_SPAD_OFFSET     0x0080      /* SPAD */
0068 #define GEN3_USMEMMISS_OFFSET       0x0070
0069 #define GEN3_INTVEC_OFFSET      0x00d0
0070 #define GEN3_IM_DOORBELL_OFFSET     0x0100      /* SDOORBELL0 */
0071 #define GEN3_B2B_SPAD_OFFSET        0x0180      /* B2B SPAD */
0072 #define GEN3_EMBAR0XBASE_OFFSET     0x4008      /* B2B_XLAT */
0073 #define GEN3_EMBAR1XBASE_OFFSET     0x4010      /* PBAR2XLAT */
0074 #define GEN3_EMBAR1XLMT_OFFSET      0x4018      /* PBAR2LMT */
0075 #define GEN3_EMBAR2XBASE_OFFSET     0x4020      /* PBAR4XLAT */
0076 #define GEN3_EMBAR2XLMT_OFFSET      0x4028      /* PBAR4LMT */
0077 #define GEN3_EM_INT_STATUS_OFFSET   0x4040
0078 #define GEN3_EM_INT_DISABLE_OFFSET  0x4048
0079 #define GEN3_EM_SPAD_OFFSET     0x4080      /* remote SPAD */
0080 #define GEN3_EM_DOORBELL_OFFSET     0x4100      /* PDOORBELL0 */
0081 #define GEN3_SPCICMD_OFFSET     0x4504      /* SPCICMD */
0082 #define GEN3_EMBAR0_OFFSET      0x4510      /* SBAR0BASE */
0083 #define GEN3_EMBAR1_OFFSET      0x4518      /* SBAR23BASE */
0084 #define GEN3_EMBAR2_OFFSET      0x4520      /* SBAR45BASE */
0085
0086 #define GEN3_DB_COUNT           32
0087 #define GEN3_DB_LINK            32
0088 #define GEN3_DB_LINK_BIT        BIT_ULL(GEN3_DB_LINK)
0089 #define GEN3_DB_MSIX_VECTOR_COUNT   33
0090 #define GEN3_DB_MSIX_VECTOR_SHIFT   1
0091 #define GEN3_DB_TOTAL_SHIFT     33
0092 #define GEN3_SPAD_COUNT         16
0093
0094 static inline u64 gen3_db_ioread(const void __iomem *mmio)
0095 {
0096     return ioread64(mmio);
0097 }
0098
0099 static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
0100 {
0101     iowrite64(bits, mmio);
0102 }
0103
0104 ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
0105                       size_t count, loff_t *offp);
0106 int gen3_init_dev(struct intel_ntb_dev *ndev);
0107 int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
0108         enum ntb_width max_width);
0109 u64 intel_ntb3_db_read(struct ntb_dev *ntb);
0110 int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits);
0111 int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits);
0112 int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
0113                 resource_size_t *db_size,
0114                 u64 *db_data, int db_bit);
0115
0116 extern const struct ntb_dev_ops intel_ntb3_ops;
0117
0118 #endif