hw/intel/ntb_hw_gen3.c

0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  *   redistributing this file, you may do so under either license.
0004  *
0005  *   GPL LICENSE SUMMARY
0006  *
0007  *   Copyright(c) 2017 Intel Corporation. All rights reserved.
0008  *
0009  *   This program is free software; you can redistribute it and/or modify
0010  *   it under the terms of version 2 of the GNU General Public License as
0011  *   published by the Free Software Foundation.
0012  *
0013  *   BSD LICENSE
0014  *
0015  *   Copyright(c) 2017 Intel Corporation. All rights reserved.
0016  *
0017  *   Redistribution and use in source and binary forms, with or without
0018  *   modification, are permitted provided that the following conditions
0019  *   are met:
0020  *
0021  *     * Redistributions of source code must retain the above copyright
0022  *       notice, this list of conditions and the following disclaimer.
0023  *     * Redistributions in binary form must reproduce the above copy
0024  *       notice, this list of conditions and the following disclaimer in
0025  *       the documentation and/or other materials provided with the
0026  *       distribution.
0027  *     * Neither the name of Intel Corporation nor the names of its
0028  *       contributors may be used to endorse or promote products derived
0029  *       from this software without specific prior written permission.
0030  *
0031  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0032  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0033  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0034  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0035  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0036  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0037  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0038  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0039  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0040  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0041  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0042  *
0043  * Intel PCIe GEN3 NTB Linux driver
0044  *
0045  */
0046
0047 #include <linux/debugfs.h>
0048 #include <linux/delay.h>
0049 #include <linux/init.h>
0050 #include <linux/interrupt.h>
0051 #include <linux/module.h>
0052 #include <linux/pci.h>
0053 #include <linux/random.h>
0054 #include <linux/slab.h>
0055 #include <linux/ntb.h>
0056
0057 #include "ntb_hw_intel.h"
0058 #include "ntb_hw_gen1.h"
0059 #include "ntb_hw_gen3.h"
0060
0061 static int gen3_poll_link(struct intel_ntb_dev *ndev);
0062
0063 static const struct intel_ntb_reg gen3_reg = {
0064     .poll_link      = gen3_poll_link,
0065     .link_is_up     = xeon_link_is_up,
0066     .db_ioread      = gen3_db_ioread,
0067     .db_iowrite     = gen3_db_iowrite,
0068     .db_size        = sizeof(u32),
0069     .ntb_ctl        = GEN3_NTBCNTL_OFFSET,
0070     .mw_bar         = {2, 4},
0071 };
0072
0073 static const struct intel_ntb_alt_reg gen3_pri_reg = {
0074     .db_bell        = GEN3_EM_DOORBELL_OFFSET,
0075     .db_clear       = GEN3_IM_INT_STATUS_OFFSET,
0076     .db_mask        = GEN3_IM_INT_DISABLE_OFFSET,
0077     .spad           = GEN3_IM_SPAD_OFFSET,
0078 };
0079
0080 static const struct intel_ntb_alt_reg gen3_b2b_reg = {
0081     .db_bell        = GEN3_IM_DOORBELL_OFFSET,
0082     .db_clear       = GEN3_EM_INT_STATUS_OFFSET,
0083     .db_mask        = GEN3_EM_INT_DISABLE_OFFSET,
0084     .spad           = GEN3_B2B_SPAD_OFFSET,
0085 };
0086
0087 static const struct intel_ntb_xlat_reg gen3_sec_xlat = {
0088 /*  .bar0_base      = GEN3_EMBAR0_OFFSET, */
0089     .bar2_limit     = GEN3_IMBAR1XLMT_OFFSET,
0090     .bar2_xlat      = GEN3_IMBAR1XBASE_OFFSET,
0091 };
0092
0093 static int gen3_poll_link(struct intel_ntb_dev *ndev)
0094 {
0095     u16 reg_val;
0096     int rc;
0097
0098     ndev->reg->db_iowrite(ndev->db_link_mask,
0099                   ndev->self_mmio +
0100                   ndev->self_reg->db_clear);
0101
0102     rc = pci_read_config_word(ndev->ntb.pdev,
0103                   GEN3_LINK_STATUS_OFFSET, &reg_val);
0104     if (rc)
0105         return 0;
0106
0107     if (reg_val == ndev->lnk_sta)
0108         return 0;
0109
0110     ndev->lnk_sta = reg_val;
0111
0112     return 1;
0113 }
0114
0115 static int gen3_init_isr(struct intel_ntb_dev *ndev)
0116 {
0117     int i;
0118
0119     /*
0120      * The MSIX vectors and the interrupt status bits are not lined up
0121      * on Skylake. By default the link status bit is bit 32, however it
0122      * is by default MSIX vector0. We need to fixup to line them up.
0123      * The vectors at reset is 1-32,0. We need to reprogram to 0-32.
0124      */
0125
0126     for (i = 0; i < GEN3_DB_MSIX_VECTOR_COUNT; i++)
0127         iowrite8(i, ndev->self_mmio + GEN3_INTVEC_OFFSET + i);
0128
0129     /* move link status down one as workaround */
0130     if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) {
0131         iowrite8(GEN3_DB_MSIX_VECTOR_COUNT - 2,
0132              ndev->self_mmio + GEN3_INTVEC_OFFSET +
0133              (GEN3_DB_MSIX_VECTOR_COUNT - 1));
0134     }
0135
0136     return ndev_init_isr(ndev, GEN3_DB_MSIX_VECTOR_COUNT,
0137                  GEN3_DB_MSIX_VECTOR_COUNT,
0138                  GEN3_DB_MSIX_VECTOR_SHIFT,
0139                  GEN3_DB_TOTAL_SHIFT);
0140 }
0141
0142 static int gen3_setup_b2b_mw(struct intel_ntb_dev *ndev,
0143                 const struct intel_b2b_addr *addr,
0144                 const struct intel_b2b_addr *peer_addr)
0145 {
0146     struct pci_dev *pdev;
0147     void __iomem *mmio;
0148     phys_addr_t bar_addr;
0149
0150     pdev = ndev->ntb.pdev;
0151     mmio = ndev->self_mmio;
0152
0153     /* setup incoming bar limits == base addrs (zero length windows) */
0154     bar_addr = addr->bar2_addr64;
0155     iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET);
0156     bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
0157     dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
0158
0159     bar_addr = addr->bar4_addr64;
0160     iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET);
0161     bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
0162     dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
0163
0164     /* zero incoming translation addrs */
0165     iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET);
0166     iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET);
0167
0168     ndev->peer_mmio = ndev->self_mmio;
0169
0170     return 0;
0171 }
0172
0173 static int gen3_init_ntb(struct intel_ntb_dev *ndev)
0174 {
0175     int rc;
0176
0177
0178     ndev->mw_count = XEON_MW_COUNT;
0179     ndev->spad_count = GEN3_SPAD_COUNT;
0180     ndev->db_count = GEN3_DB_COUNT;
0181     ndev->db_link_mask = GEN3_DB_LINK_BIT;
0182
0183     /* DB fixup for using 31 right now */
0184     if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)
0185         ndev->db_link_mask |= BIT_ULL(31);
0186
0187     switch (ndev->ntb.topo) {
0188     case NTB_TOPO_B2B_USD:
0189     case NTB_TOPO_B2B_DSD:
0190         ndev->self_reg = &gen3_pri_reg;
0191         ndev->peer_reg = &gen3_b2b_reg;
0192         ndev->xlat_reg = &gen3_sec_xlat;
0193
0194         if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
0195             rc = gen3_setup_b2b_mw(ndev,
0196                           &xeon_b2b_dsd_addr,
0197                           &xeon_b2b_usd_addr);
0198         } else {
0199             rc = gen3_setup_b2b_mw(ndev,
0200                           &xeon_b2b_usd_addr,
0201                           &xeon_b2b_dsd_addr);
0202         }
0203
0204         if (rc)
0205             return rc;
0206
0207         /* Enable Bus Master and Memory Space on the secondary side */
0208         iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
0209               ndev->self_mmio + GEN3_SPCICMD_OFFSET);
0210
0211         break;
0212
0213     default:
0214         return -EINVAL;
0215     }
0216
0217     ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
0218
0219     ndev->reg->db_iowrite(ndev->db_valid_mask,
0220                   ndev->self_mmio +
0221                   ndev->self_reg->db_mask);
0222
0223     return 0;
0224 }
0225
0226 int gen3_init_dev(struct intel_ntb_dev *ndev)
0227 {
0228     struct pci_dev *pdev;
0229     u8 ppd;
0230     int rc;
0231
0232     pdev = ndev->ntb.pdev;
0233
0234     ndev->reg = &gen3_reg;
0235
0236     rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
0237     if (rc)
0238         return -EIO;
0239
0240     ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
0241     dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
0242         ntb_topo_string(ndev->ntb.topo));
0243     if (ndev->ntb.topo == NTB_TOPO_NONE)
0244         return -EINVAL;
0245
0246     ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;
0247
0248     rc = gen3_init_ntb(ndev);
0249     if (rc)
0250         return rc;
0251
0252     return gen3_init_isr(ndev);
0253 }
0254
0255 ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
0256                       size_t count, loff_t *offp)
0257 {
0258     struct intel_ntb_dev *ndev;
0259     void __iomem *mmio;
0260     char *buf;
0261     size_t buf_size;
0262     ssize_t ret, off;
0263     union { u64 v64; u32 v32; u16 v16; } u;
0264
0265     ndev = filp->private_data;
0266     mmio = ndev->self_mmio;
0267
0268     buf_size = min(count, 0x800ul);
0269
0270     buf = kmalloc(buf_size, GFP_KERNEL);
0271     if (!buf)
0272         return -ENOMEM;
0273
0274     off = 0;
0275
0276     off += scnprintf(buf + off, buf_size - off,
0277              "NTB Device Information:\n");
0278
0279     off += scnprintf(buf + off, buf_size - off,
0280              "Connection Topology -\t%s\n",
0281              ntb_topo_string(ndev->ntb.topo));
0282
0283     off += scnprintf(buf + off, buf_size - off,
0284              "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);
0285     off += scnprintf(buf + off, buf_size - off,
0286              "LNK STA -\t\t%#06x\n", ndev->lnk_sta);
0287
0288     if (!ndev->reg->link_is_up(ndev))
0289         off += scnprintf(buf + off, buf_size - off,
0290                  "Link Status -\t\tDown\n");
0291     else {
0292         off += scnprintf(buf + off, buf_size - off,
0293                  "Link Status -\t\tUp\n");
0294         off += scnprintf(buf + off, buf_size - off,
0295                  "Link Speed -\t\tPCI-E Gen %u\n",
0296                  NTB_LNK_STA_SPEED(ndev->lnk_sta));
0297         off += scnprintf(buf + off, buf_size - off,
0298                  "Link Width -\t\tx%u\n",
0299                  NTB_LNK_STA_WIDTH(ndev->lnk_sta));
0300     }
0301
0302     off += scnprintf(buf + off, buf_size - off,
0303              "Memory Window Count -\t%u\n", ndev->mw_count);
0304     off += scnprintf(buf + off, buf_size - off,
0305              "Scratchpad Count -\t%u\n", ndev->spad_count);
0306     off += scnprintf(buf + off, buf_size - off,
0307              "Doorbell Count -\t%u\n", ndev->db_count);
0308     off += scnprintf(buf + off, buf_size - off,
0309              "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);
0310     off += scnprintf(buf + off, buf_size - off,
0311              "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);
0312
0313     off += scnprintf(buf + off, buf_size - off,
0314              "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);
0315     off += scnprintf(buf + off, buf_size - off,
0316              "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);
0317     off += scnprintf(buf + off, buf_size - off,
0318              "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);
0319
0320     u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);
0321     off += scnprintf(buf + off, buf_size - off,
0322              "Doorbell Mask -\t\t%#llx\n", u.v64);
0323
0324     u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell);
0325     off += scnprintf(buf + off, buf_size - off,
0326              "Doorbell Bell -\t\t%#llx\n", u.v64);
0327
0328     off += scnprintf(buf + off, buf_size - off,
0329              "\nNTB Incoming XLAT:\n");
0330
0331     u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET);
0332     off += scnprintf(buf + off, buf_size - off,
0333              "IMBAR1XBASE -\t\t%#018llx\n", u.v64);
0334
0335     u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET);
0336     off += scnprintf(buf + off, buf_size - off,
0337              "IMBAR2XBASE -\t\t%#018llx\n", u.v64);
0338
0339     u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
0340     off += scnprintf(buf + off, buf_size - off,
0341              "IMBAR1XLMT -\t\t\t%#018llx\n", u.v64);
0342
0343     u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
0344     off += scnprintf(buf + off, buf_size - off,
0345              "IMBAR2XLMT -\t\t\t%#018llx\n", u.v64);
0346
0347     if (ntb_topo_is_b2b(ndev->ntb.topo)) {
0348         off += scnprintf(buf + off, buf_size - off,
0349                  "\nNTB Outgoing B2B XLAT:\n");
0350
0351         u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET);
0352         off += scnprintf(buf + off, buf_size - off,
0353                  "EMBAR1XBASE -\t\t%#018llx\n", u.v64);
0354
0355         u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET);
0356         off += scnprintf(buf + off, buf_size - off,
0357                  "EMBAR2XBASE -\t\t%#018llx\n", u.v64);
0358
0359         u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET);
0360         off += scnprintf(buf + off, buf_size - off,
0361                  "EMBAR1XLMT -\t\t%#018llx\n", u.v64);
0362
0363         u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET);
0364         off += scnprintf(buf + off, buf_size - off,
0365                  "EMBAR2XLMT -\t\t%#018llx\n", u.v64);
0366
0367         off += scnprintf(buf + off, buf_size - off,
0368                  "\nNTB Secondary BAR:\n");
0369
0370         u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET);
0371         off += scnprintf(buf + off, buf_size - off,
0372                  "EMBAR0 -\t\t%#018llx\n", u.v64);
0373
0374         u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET);
0375         off += scnprintf(buf + off, buf_size - off,
0376                  "EMBAR1 -\t\t%#018llx\n", u.v64);
0377
0378         u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET);
0379         off += scnprintf(buf + off, buf_size - off,
0380                  "EMBAR2 -\t\t%#018llx\n", u.v64);
0381     }
0382
0383     off += scnprintf(buf + off, buf_size - off,
0384              "\nNTB Statistics:\n");
0385
0386     u.v16 = ioread16(mmio + GEN3_USMEMMISS_OFFSET);
0387     off += scnprintf(buf + off, buf_size - off,
0388              "Upstream Memory Miss -\t%u\n", u.v16);
0389
0390     off += scnprintf(buf + off, buf_size - off,
0391              "\nNTB Hardware Errors:\n");
0392
0393     if (!pci_read_config_word(ndev->ntb.pdev,
0394                   GEN3_DEVSTS_OFFSET, &u.v16))
0395         off += scnprintf(buf + off, buf_size - off,
0396                  "DEVSTS -\t\t%#06x\n", u.v16);
0397
0398     if (!pci_read_config_word(ndev->ntb.pdev,
0399                   GEN3_LINK_STATUS_OFFSET, &u.v16))
0400         off += scnprintf(buf + off, buf_size - off,
0401                  "LNKSTS -\t\t%#06x\n", u.v16);
0402
0403     if (!pci_read_config_dword(ndev->ntb.pdev,
0404                    GEN3_UNCERRSTS_OFFSET, &u.v32))
0405         off += scnprintf(buf + off, buf_size - off,
0406                  "UNCERRSTS -\t\t%#06x\n", u.v32);
0407
0408     if (!pci_read_config_dword(ndev->ntb.pdev,
0409                    GEN3_CORERRSTS_OFFSET, &u.v32))
0410         off += scnprintf(buf + off, buf_size - off,
0411                  "CORERRSTS -\t\t%#06x\n", u.v32);
0412
0413     ret = simple_read_from_buffer(ubuf, count, offp, buf, off);
0414     kfree(buf);
0415     return ret;
0416 }
0417
0418 int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
0419         enum ntb_width max_width)
0420 {
0421     struct intel_ntb_dev *ndev;
0422     u32 ntb_ctl;
0423
0424     ndev = container_of(ntb, struct intel_ntb_dev, ntb);
0425
0426     dev_dbg(&ntb->pdev->dev,
0427         "Enabling link with max_speed %d max_width %d\n",
0428         max_speed, max_width);
0429
0430     if (max_speed != NTB_SPEED_AUTO)
0431         dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
0432     if (max_width != NTB_WIDTH_AUTO)
0433         dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
0434
0435     ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
0436     ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
0437     ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;
0438     ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;
0439     iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);
0440
0441     return 0;
0442 }
0443 static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
0444                    dma_addr_t addr, resource_size_t size)
0445 {
0446     struct intel_ntb_dev *ndev = ntb_ndev(ntb);
0447     unsigned long xlat_reg, limit_reg;
0448     resource_size_t bar_size, mw_size;
0449     void __iomem *mmio;
0450     u64 base, limit, reg_val;
0451     int bar;
0452
0453     if (pidx != NTB_DEF_PEER_IDX)
0454         return -EINVAL;
0455
0456     if (idx >= ndev->b2b_idx && !ndev->b2b_off)
0457         idx += 1;
0458
0459     bar = ndev_mw_to_bar(ndev, idx);
0460     if (bar < 0)
0461         return bar;
0462
0463     bar_size = pci_resource_len(ndev->ntb.pdev, bar);
0464
0465     if (idx == ndev->b2b_idx)
0466         mw_size = bar_size - ndev->b2b_off;
0467     else
0468         mw_size = bar_size;
0469
0470     /* hardware requires that addr is aligned to bar size */
0471     if (addr & (bar_size - 1))
0472         return -EINVAL;
0473
0474     /* make sure the range fits in the usable mw size */
0475     if (size > mw_size)
0476         return -EINVAL;
0477
0478     mmio = ndev->self_mmio;
0479     xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);
0480     limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);
0481     base = pci_resource_start(ndev->ntb.pdev, bar);
0482
0483     /* Set the limit if supported, if size is not mw_size */
0484     if (limit_reg && size != mw_size)
0485         limit = base + size;
0486     else
0487         limit = base + mw_size;
0488
0489     /* set and verify setting the translation address */
0490     iowrite64(addr, mmio + xlat_reg);
0491     reg_val = ioread64(mmio + xlat_reg);
0492     if (reg_val != addr) {
0493         iowrite64(0, mmio + xlat_reg);
0494         return -EIO;
0495     }
0496
0497     dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
0498
0499     /* set and verify setting the limit */
0500     iowrite64(limit, mmio + limit_reg);
0501     reg_val = ioread64(mmio + limit_reg);
0502     if (reg_val != limit) {
0503         iowrite64(base, mmio + limit_reg);
0504         iowrite64(0, mmio + xlat_reg);
0505         return -EIO;
0506     }
0507
0508     dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
0509
0510     /* setup the EP */
0511     limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
0512     base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx));
0513     base &= ~0xf;
0514
0515     if (limit_reg && size != mw_size)
0516         limit = base + size;
0517     else
0518         limit = base + mw_size;
0519
0520     /* set and verify setting the limit */
0521     iowrite64(limit, mmio + limit_reg);
0522     reg_val = ioread64(mmio + limit_reg);
0523     if (reg_val != limit) {
0524         iowrite64(base, mmio + limit_reg);
0525         iowrite64(0, mmio + xlat_reg);
0526         return -EIO;
0527     }
0528
0529     dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
0530
0531     return 0;
0532 }
0533
0534 int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
0535                    resource_size_t *db_size,
0536                    u64 *db_data, int db_bit)
0537 {
0538     phys_addr_t db_addr_base;
0539     struct intel_ntb_dev *ndev = ntb_ndev(ntb);
0540
0541     if (unlikely(db_bit >= BITS_PER_LONG_LONG))
0542         return -EINVAL;
0543
0544     if (unlikely(BIT_ULL(db_bit) & ~ntb_ndev(ntb)->db_valid_mask))
0545         return -EINVAL;
0546
0547     ndev_db_addr(ndev, &db_addr_base, db_size, ndev->peer_addr,
0548                 ndev->peer_reg->db_bell);
0549
0550     if (db_addr) {
0551         *db_addr = db_addr_base + (db_bit * 4);
0552         dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx db bit %d\n",
0553                 *db_addr, db_bit);
0554     }
0555
0556     if (db_data) {
0557         *db_data = 1;
0558         dev_dbg(&ndev->ntb.pdev->dev, "Peer db data %llx db bit %d\n",
0559                 *db_data, db_bit);
0560     }
0561
0562     return 0;
0563 }
0564
0565 int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
0566 {
0567     struct intel_ntb_dev *ndev = ntb_ndev(ntb);
0568     int bit;
0569
0570     if (db_bits & ~ndev->db_valid_mask)
0571         return -EINVAL;
0572
0573     while (db_bits) {
0574         bit = __ffs(db_bits);
0575         iowrite32(1, ndev->peer_mmio +
0576                 ndev->peer_reg->db_bell + (bit * 4));
0577         db_bits &= db_bits - 1;
0578     }
0579
0580     return 0;
0581 }
0582
0583 u64 intel_ntb3_db_read(struct ntb_dev *ntb)
0584 {
0585     struct intel_ntb_dev *ndev = ntb_ndev(ntb);
0586
0587     return ndev_db_read(ndev,
0588                 ndev->self_mmio +
0589                 ndev->self_reg->db_clear);
0590 }
0591
0592 int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits)
0593 {
0594     struct intel_ntb_dev *ndev = ntb_ndev(ntb);
0595
0596     return ndev_db_write(ndev, db_bits,
0597                  ndev->self_mmio +
0598                  ndev->self_reg->db_clear);
0599 }
0600
0601 const struct ntb_dev_ops intel_ntb3_ops = {
0602     .mw_count       = intel_ntb_mw_count,
0603     .mw_get_align       = intel_ntb_mw_get_align,
0604     .mw_set_trans       = intel_ntb3_mw_set_trans,
0605     .peer_mw_count      = intel_ntb_peer_mw_count,
0606     .peer_mw_get_addr   = intel_ntb_peer_mw_get_addr,
0607     .link_is_up     = intel_ntb_link_is_up,
0608     .link_enable        = intel_ntb3_link_enable,
0609     .link_disable       = intel_ntb_link_disable,
0610     .db_valid_mask      = intel_ntb_db_valid_mask,
0611     .db_vector_count    = intel_ntb_db_vector_count,
0612     .db_vector_mask     = intel_ntb_db_vector_mask,
0613     .db_read        = intel_ntb3_db_read,
0614     .db_clear       = intel_ntb3_db_clear,
0615     .db_set_mask        = intel_ntb_db_set_mask,
0616     .db_clear_mask      = intel_ntb_db_clear_mask,
0617     .peer_db_addr       = intel_ntb3_peer_db_addr,
0618     .peer_db_set        = intel_ntb3_peer_db_set,
0619     .spad_is_unsafe     = intel_ntb_spad_is_unsafe,
0620     .spad_count     = intel_ntb_spad_count,
0621     .spad_read      = intel_ntb_spad_read,
0622     .spad_write     = intel_ntb_spad_write,
0623     .peer_spad_addr     = intel_ntb_peer_spad_addr,
0624     .peer_spad_read     = intel_ntb_peer_spad_read,
0625     .peer_spad_write    = intel_ntb_peer_spad_write,
0626 };
0627