hw/intel/ntb_hw_gen1.h

0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  *   redistributing this file, you may do so under either license.
0004  *
0005  *   GPL LICENSE SUMMARY
0006  *
0007  *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
0008  *
0009  *   This program is free software; you can redistribute it and/or modify
0010  *   it under the terms of version 2 of the GNU General Public License as
0011  *   published by the Free Software Foundation.
0012  *
0013  *   BSD LICENSE
0014  *
0015  *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
0016  *
0017  *   Redistribution and use in source and binary forms, with or without
0018  *   modification, are permitted provided that the following conditions
0019  *   are met:
0020  *
0021  *     * Redistributions of source code must retain the above copyright
0022  *       notice, this list of conditions and the following disclaimer.
0023  *     * Redistributions in binary form must reproduce the above copy
0024  *       notice, this list of conditions and the following disclaimer in
0025  *       the documentation and/or other materials provided with the
0026  *       distribution.
0027  *     * Neither the name of Intel Corporation nor the names of its
0028  *       contributors may be used to endorse or promote products derived
0029  *       from this software without specific prior written permission.
0030  *
0031  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0032  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0033  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0034  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0035  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0036  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0037  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0038  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0039  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0040  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0041  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0042  */
0043
0044 #ifndef _NTB_INTEL_GEN1_H_
0045 #define _NTB_INTEL_GEN1_H_
0046
0047 #include "ntb_hw_intel.h"
0048
0049 /* Intel Gen1 Xeon hardware */
0050 #define XEON_PBAR23LMT_OFFSET       0x0000
0051 #define XEON_PBAR45LMT_OFFSET       0x0008
0052 #define XEON_PBAR4LMT_OFFSET        0x0008
0053 #define XEON_PBAR5LMT_OFFSET        0x000c
0054 #define XEON_PBAR23XLAT_OFFSET      0x0010
0055 #define XEON_PBAR45XLAT_OFFSET      0x0018
0056 #define XEON_PBAR4XLAT_OFFSET       0x0018
0057 #define XEON_PBAR5XLAT_OFFSET       0x001c
0058 #define XEON_SBAR23LMT_OFFSET       0x0020
0059 #define XEON_SBAR45LMT_OFFSET       0x0028
0060 #define XEON_SBAR4LMT_OFFSET        0x0028
0061 #define XEON_SBAR5LMT_OFFSET        0x002c
0062 #define XEON_SBAR23XLAT_OFFSET      0x0030
0063 #define XEON_SBAR45XLAT_OFFSET      0x0038
0064 #define XEON_SBAR4XLAT_OFFSET       0x0038
0065 #define XEON_SBAR5XLAT_OFFSET       0x003c
0066 #define XEON_SBAR0BASE_OFFSET       0x0040
0067 #define XEON_SBAR23BASE_OFFSET      0x0048
0068 #define XEON_SBAR45BASE_OFFSET      0x0050
0069 #define XEON_SBAR4BASE_OFFSET       0x0050
0070 #define XEON_SBAR5BASE_OFFSET       0x0054
0071 #define XEON_SBDF_OFFSET        0x005c
0072 #define XEON_NTBCNTL_OFFSET     0x0058
0073 #define XEON_PDOORBELL_OFFSET       0x0060
0074 #define XEON_PDBMSK_OFFSET      0x0062
0075 #define XEON_SDOORBELL_OFFSET       0x0064
0076 #define XEON_SDBMSK_OFFSET      0x0066
0077 #define XEON_USMEMMISS_OFFSET       0x0070
0078 #define XEON_SPAD_OFFSET        0x0080
0079 #define XEON_PBAR23SZ_OFFSET        0x00d0
0080 #define XEON_PBAR45SZ_OFFSET        0x00d1
0081 #define XEON_PBAR4SZ_OFFSET     0x00d1
0082 #define XEON_SBAR23SZ_OFFSET        0x00d2
0083 #define XEON_SBAR45SZ_OFFSET        0x00d3
0084 #define XEON_SBAR4SZ_OFFSET     0x00d3
0085 #define XEON_PPD_OFFSET         0x00d4
0086 #define XEON_PBAR5SZ_OFFSET     0x00d5
0087 #define XEON_SBAR5SZ_OFFSET     0x00d6
0088 #define XEON_WCCNTRL_OFFSET     0x00e0
0089 #define XEON_UNCERRSTS_OFFSET       0x014c
0090 #define XEON_CORERRSTS_OFFSET       0x0158
0091 #define XEON_LINK_STATUS_OFFSET     0x01a2
0092 #define XEON_SPCICMD_OFFSET     0x0504
0093 #define XEON_DEVCTRL_OFFSET     0x0598
0094 #define XEON_DEVSTS_OFFSET      0x059a
0095 #define XEON_SLINK_STATUS_OFFSET    0x05a2
0096 #define XEON_B2B_SPAD_OFFSET        0x0100
0097 #define XEON_B2B_DOORBELL_OFFSET    0x0140
0098 #define XEON_B2B_XLAT_OFFSETL       0x0144
0099 #define XEON_B2B_XLAT_OFFSETU       0x0148
0100 #define XEON_PPD_CONN_MASK      0x03
0101 #define XEON_PPD_CONN_TRANSPARENT   0x00
0102 #define XEON_PPD_CONN_B2B       0x01
0103 #define XEON_PPD_CONN_RP        0x02
0104 #define XEON_PPD_DEV_MASK       0x10
0105 #define XEON_PPD_DEV_USD        0x00
0106 #define XEON_PPD_DEV_DSD        0x10
0107 #define XEON_PPD_SPLIT_BAR_MASK     0x40
0108
0109 #define XEON_PPD_TOPO_MASK  (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
0110 #define XEON_PPD_TOPO_PRI_USD   (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
0111 #define XEON_PPD_TOPO_PRI_DSD   (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
0112 #define XEON_PPD_TOPO_SEC_USD   (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
0113 #define XEON_PPD_TOPO_SEC_DSD   (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
0114 #define XEON_PPD_TOPO_B2B_USD   (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
0115 #define XEON_PPD_TOPO_B2B_DSD   (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
0116
0117 #define XEON_MW_COUNT           2
0118 #define HSX_SPLIT_BAR_MW_COUNT      3
0119 #define XEON_DB_COUNT           15
0120 #define XEON_DB_LINK            15
0121 #define XEON_DB_LINK_BIT            BIT_ULL(XEON_DB_LINK)
0122 #define XEON_DB_MSIX_VECTOR_COUNT   4
0123 #define XEON_DB_MSIX_VECTOR_SHIFT   5
0124 #define XEON_DB_TOTAL_SHIFT     16
0125 #define XEON_SPAD_COUNT         16
0126
0127 /* Use the following addresses for translation between b2b ntb devices in case
0128  * the hardware default values are not reliable. */
0129 #define XEON_B2B_BAR0_ADDR  0x1000000000000000ull
0130 #define XEON_B2B_BAR2_ADDR64    0x2000000000000000ull
0131 #define XEON_B2B_BAR4_ADDR64    0x4000000000000000ull
0132 #define XEON_B2B_BAR4_ADDR32    0x20000000u
0133 #define XEON_B2B_BAR5_ADDR32    0x40000000u
0134
0135 /* The peer ntb secondary config space is 32KB fixed size */
0136 #define XEON_B2B_MIN_SIZE       0x8000
0137
0138 /* flags to indicate hardware errata */
0139 #define NTB_HWERR_SDOORBELL_LOCKUP  BIT_ULL(0)
0140 #define NTB_HWERR_SB01BASE_LOCKUP   BIT_ULL(1)
0141 #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
0142 #define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3)
0143 #define NTB_HWERR_BAR_ALIGN     BIT_ULL(4)
0144 #define NTB_HWERR_LTR_BAD       BIT_ULL(5)
0145
0146 extern struct intel_b2b_addr xeon_b2b_usd_addr;
0147 extern struct intel_b2b_addr xeon_b2b_dsd_addr;
0148
0149 int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max,
0150         int msix_shift, int total_shift);
0151 enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);
0152 void ndev_db_addr(struct intel_ntb_dev *ndev,
0153                 phys_addr_t *db_addr, resource_size_t *db_size,
0154                 phys_addr_t reg_addr, unsigned long reg);
0155 u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio);
0156 int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,
0157                 void __iomem *mmio);
0158 int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx);
0159 int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx);
0160 int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
0161         resource_size_t *addr_align, resource_size_t *size_align,
0162         resource_size_t *size_max);
0163 int intel_ntb_peer_mw_count(struct ntb_dev *ntb);
0164 int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx,
0165         phys_addr_t *base, resource_size_t *size);
0166 u64 intel_ntb_link_is_up(struct ntb_dev *ntb, enum ntb_speed *speed,
0167         enum ntb_width *width);
0168 int intel_ntb_link_disable(struct ntb_dev *ntb);
0169 u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb);
0170 int intel_ntb_db_vector_count(struct ntb_dev *ntb);
0171 u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector);
0172 int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits);
0173 int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits);
0174 int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb);
0175 int intel_ntb_spad_count(struct ntb_dev *ntb);
0176 u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx);
0177 int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val);
0178 u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx);
0179 int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, int sidx,
0180         u32 val);
0181 int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx,
0182                     phys_addr_t *spad_addr);
0183 int xeon_link_is_up(struct intel_ntb_dev *ndev);
0184
0185 #endif