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0009 #include <linux/delay.h>
0010 #include <linux/module.h>
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013 #include <linux/ntb.h>
0014
0015 #define NTB_EPF_COMMAND 0x0
0016 #define CMD_CONFIGURE_DOORBELL 1
0017 #define CMD_TEARDOWN_DOORBELL 2
0018 #define CMD_CONFIGURE_MW 3
0019 #define CMD_TEARDOWN_MW 4
0020 #define CMD_LINK_UP 5
0021 #define CMD_LINK_DOWN 6
0022
0023 #define NTB_EPF_ARGUMENT 0x4
0024 #define MSIX_ENABLE BIT(16)
0025
0026 #define NTB_EPF_CMD_STATUS 0x8
0027 #define COMMAND_STATUS_OK 1
0028 #define COMMAND_STATUS_ERROR 2
0029
0030 #define NTB_EPF_LINK_STATUS 0x0A
0031 #define LINK_STATUS_UP BIT(0)
0032
0033 #define NTB_EPF_TOPOLOGY 0x0C
0034 #define NTB_EPF_LOWER_ADDR 0x10
0035 #define NTB_EPF_UPPER_ADDR 0x14
0036 #define NTB_EPF_LOWER_SIZE 0x18
0037 #define NTB_EPF_UPPER_SIZE 0x1C
0038 #define NTB_EPF_MW_COUNT 0x20
0039 #define NTB_EPF_MW1_OFFSET 0x24
0040 #define NTB_EPF_SPAD_OFFSET 0x28
0041 #define NTB_EPF_SPAD_COUNT 0x2C
0042 #define NTB_EPF_DB_ENTRY_SIZE 0x30
0043 #define NTB_EPF_DB_DATA(n) (0x34 + (n) * 4)
0044 #define NTB_EPF_DB_OFFSET(n) (0xB4 + (n) * 4)
0045
0046 #define NTB_EPF_MIN_DB_COUNT 3
0047 #define NTB_EPF_MAX_DB_COUNT 31
0048
0049 #define NTB_EPF_COMMAND_TIMEOUT 1000
0050
0051 enum pci_barno {
0052 BAR_0,
0053 BAR_1,
0054 BAR_2,
0055 BAR_3,
0056 BAR_4,
0057 BAR_5,
0058 };
0059
0060 struct ntb_epf_dev {
0061 struct ntb_dev ntb;
0062 struct device *dev;
0063
0064 struct mutex cmd_lock;
0065
0066 enum pci_barno ctrl_reg_bar;
0067 enum pci_barno peer_spad_reg_bar;
0068 enum pci_barno db_reg_bar;
0069 enum pci_barno mw_bar;
0070
0071 unsigned int mw_count;
0072 unsigned int spad_count;
0073 unsigned int db_count;
0074
0075 void __iomem *ctrl_reg;
0076 void __iomem *db_reg;
0077 void __iomem *peer_spad_reg;
0078
0079 unsigned int self_spad;
0080 unsigned int peer_spad;
0081
0082 int db_val;
0083 u64 db_valid_mask;
0084 };
0085
0086 #define ntb_ndev(__ntb) container_of(__ntb, struct ntb_epf_dev, ntb)
0087
0088 struct ntb_epf_data {
0089
0090 enum pci_barno ctrl_reg_bar;
0091
0092 enum pci_barno peer_spad_reg_bar;
0093
0094 enum pci_barno db_reg_bar;
0095
0096 enum pci_barno mw_bar;
0097 };
0098
0099 static int ntb_epf_send_command(struct ntb_epf_dev *ndev, u32 command,
0100 u32 argument)
0101 {
0102 ktime_t timeout;
0103 bool timedout;
0104 int ret = 0;
0105 u32 status;
0106
0107 mutex_lock(&ndev->cmd_lock);
0108 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT);
0109 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND);
0110
0111 timeout = ktime_add_ms(ktime_get(), NTB_EPF_COMMAND_TIMEOUT);
0112 while (1) {
0113 timedout = ktime_after(ktime_get(), timeout);
0114 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS);
0115
0116 if (status == COMMAND_STATUS_ERROR) {
0117 ret = -EINVAL;
0118 break;
0119 }
0120
0121 if (status == COMMAND_STATUS_OK)
0122 break;
0123
0124 if (WARN_ON(timedout)) {
0125 ret = -ETIMEDOUT;
0126 break;
0127 }
0128
0129 usleep_range(5, 10);
0130 }
0131
0132 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS);
0133 mutex_unlock(&ndev->cmd_lock);
0134
0135 return ret;
0136 }
0137
0138 static int ntb_epf_mw_to_bar(struct ntb_epf_dev *ndev, int idx)
0139 {
0140 struct device *dev = ndev->dev;
0141
0142 if (idx < 0 || idx > ndev->mw_count) {
0143 dev_err(dev, "Unsupported Memory Window index %d\n", idx);
0144 return -EINVAL;
0145 }
0146
0147 return idx + 2;
0148 }
0149
0150 static int ntb_epf_mw_count(struct ntb_dev *ntb, int pidx)
0151 {
0152 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0153 struct device *dev = ndev->dev;
0154
0155 if (pidx != NTB_DEF_PEER_IDX) {
0156 dev_err(dev, "Unsupported Peer ID %d\n", pidx);
0157 return -EINVAL;
0158 }
0159
0160 return ndev->mw_count;
0161 }
0162
0163 static int ntb_epf_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
0164 resource_size_t *addr_align,
0165 resource_size_t *size_align,
0166 resource_size_t *size_max)
0167 {
0168 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0169 struct device *dev = ndev->dev;
0170 int bar;
0171
0172 if (pidx != NTB_DEF_PEER_IDX) {
0173 dev_err(dev, "Unsupported Peer ID %d\n", pidx);
0174 return -EINVAL;
0175 }
0176
0177 bar = ntb_epf_mw_to_bar(ndev, idx);
0178 if (bar < 0)
0179 return bar;
0180
0181 if (addr_align)
0182 *addr_align = SZ_4K;
0183
0184 if (size_align)
0185 *size_align = 1;
0186
0187 if (size_max)
0188 *size_max = pci_resource_len(ndev->ntb.pdev, bar);
0189
0190 return 0;
0191 }
0192
0193 static u64 ntb_epf_link_is_up(struct ntb_dev *ntb,
0194 enum ntb_speed *speed,
0195 enum ntb_width *width)
0196 {
0197 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0198 u32 status;
0199
0200 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS);
0201
0202 return status & LINK_STATUS_UP;
0203 }
0204
0205 static u32 ntb_epf_spad_read(struct ntb_dev *ntb, int idx)
0206 {
0207 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0208 struct device *dev = ndev->dev;
0209 u32 offset;
0210
0211 if (idx < 0 || idx >= ndev->spad_count) {
0212 dev_err(dev, "READ: Invalid ScratchPad Index %d\n", idx);
0213 return 0;
0214 }
0215
0216 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);
0217 offset += (idx << 2);
0218
0219 return readl(ndev->ctrl_reg + offset);
0220 }
0221
0222 static int ntb_epf_spad_write(struct ntb_dev *ntb,
0223 int idx, u32 val)
0224 {
0225 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0226 struct device *dev = ndev->dev;
0227 u32 offset;
0228
0229 if (idx < 0 || idx >= ndev->spad_count) {
0230 dev_err(dev, "WRITE: Invalid ScratchPad Index %d\n", idx);
0231 return -EINVAL;
0232 }
0233
0234 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);
0235 offset += (idx << 2);
0236 writel(val, ndev->ctrl_reg + offset);
0237
0238 return 0;
0239 }
0240
0241 static u32 ntb_epf_peer_spad_read(struct ntb_dev *ntb, int pidx, int idx)
0242 {
0243 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0244 struct device *dev = ndev->dev;
0245 u32 offset;
0246
0247 if (pidx != NTB_DEF_PEER_IDX) {
0248 dev_err(dev, "Unsupported Peer ID %d\n", pidx);
0249 return -EINVAL;
0250 }
0251
0252 if (idx < 0 || idx >= ndev->spad_count) {
0253 dev_err(dev, "WRITE: Invalid Peer ScratchPad Index %d\n", idx);
0254 return -EINVAL;
0255 }
0256
0257 offset = (idx << 2);
0258 return readl(ndev->peer_spad_reg + offset);
0259 }
0260
0261 static int ntb_epf_peer_spad_write(struct ntb_dev *ntb, int pidx,
0262 int idx, u32 val)
0263 {
0264 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0265 struct device *dev = ndev->dev;
0266 u32 offset;
0267
0268 if (pidx != NTB_DEF_PEER_IDX) {
0269 dev_err(dev, "Unsupported Peer ID %d\n", pidx);
0270 return -EINVAL;
0271 }
0272
0273 if (idx < 0 || idx >= ndev->spad_count) {
0274 dev_err(dev, "WRITE: Invalid Peer ScratchPad Index %d\n", idx);
0275 return -EINVAL;
0276 }
0277
0278 offset = (idx << 2);
0279 writel(val, ndev->peer_spad_reg + offset);
0280
0281 return 0;
0282 }
0283
0284 static int ntb_epf_link_enable(struct ntb_dev *ntb,
0285 enum ntb_speed max_speed,
0286 enum ntb_width max_width)
0287 {
0288 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0289 struct device *dev = ndev->dev;
0290 int ret;
0291
0292 ret = ntb_epf_send_command(ndev, CMD_LINK_UP, 0);
0293 if (ret) {
0294 dev_err(dev, "Fail to enable link\n");
0295 return ret;
0296 }
0297
0298 return 0;
0299 }
0300
0301 static int ntb_epf_link_disable(struct ntb_dev *ntb)
0302 {
0303 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0304 struct device *dev = ndev->dev;
0305 int ret;
0306
0307 ret = ntb_epf_send_command(ndev, CMD_LINK_DOWN, 0);
0308 if (ret) {
0309 dev_err(dev, "Fail to disable link\n");
0310 return ret;
0311 }
0312
0313 return 0;
0314 }
0315
0316 static irqreturn_t ntb_epf_vec_isr(int irq, void *dev)
0317 {
0318 struct ntb_epf_dev *ndev = dev;
0319 int irq_no;
0320
0321 irq_no = irq - pci_irq_vector(ndev->ntb.pdev, 0);
0322 ndev->db_val = irq_no + 1;
0323
0324 if (irq_no == 0)
0325 ntb_link_event(&ndev->ntb);
0326 else
0327 ntb_db_event(&ndev->ntb, irq_no);
0328
0329 return IRQ_HANDLED;
0330 }
0331
0332 static int ntb_epf_init_isr(struct ntb_epf_dev *ndev, int msi_min, int msi_max)
0333 {
0334 struct pci_dev *pdev = ndev->ntb.pdev;
0335 struct device *dev = ndev->dev;
0336 u32 argument = MSIX_ENABLE;
0337 int irq;
0338 int ret;
0339 int i;
0340
0341 irq = pci_alloc_irq_vectors(pdev, msi_min, msi_max, PCI_IRQ_MSIX);
0342 if (irq < 0) {
0343 dev_dbg(dev, "Failed to get MSIX interrupts\n");
0344 irq = pci_alloc_irq_vectors(pdev, msi_min, msi_max,
0345 PCI_IRQ_MSI);
0346 if (irq < 0) {
0347 dev_err(dev, "Failed to get MSI interrupts\n");
0348 return irq;
0349 }
0350 argument &= ~MSIX_ENABLE;
0351 }
0352
0353 for (i = 0; i < irq; i++) {
0354 ret = request_irq(pci_irq_vector(pdev, i), ntb_epf_vec_isr,
0355 0, "ntb_epf", ndev);
0356 if (ret) {
0357 dev_err(dev, "Failed to request irq\n");
0358 goto err_request_irq;
0359 }
0360 }
0361
0362 ndev->db_count = irq - 1;
0363
0364 ret = ntb_epf_send_command(ndev, CMD_CONFIGURE_DOORBELL,
0365 argument | irq);
0366 if (ret) {
0367 dev_err(dev, "Failed to configure doorbell\n");
0368 goto err_configure_db;
0369 }
0370
0371 return 0;
0372
0373 err_configure_db:
0374 for (i = 0; i < ndev->db_count + 1; i++)
0375 free_irq(pci_irq_vector(pdev, i), ndev);
0376
0377 err_request_irq:
0378 pci_free_irq_vectors(pdev);
0379
0380 return ret;
0381 }
0382
0383 static int ntb_epf_peer_mw_count(struct ntb_dev *ntb)
0384 {
0385 return ntb_ndev(ntb)->mw_count;
0386 }
0387
0388 static int ntb_epf_spad_count(struct ntb_dev *ntb)
0389 {
0390 return ntb_ndev(ntb)->spad_count;
0391 }
0392
0393 static u64 ntb_epf_db_valid_mask(struct ntb_dev *ntb)
0394 {
0395 return ntb_ndev(ntb)->db_valid_mask;
0396 }
0397
0398 static int ntb_epf_db_set_mask(struct ntb_dev *ntb, u64 db_bits)
0399 {
0400 return 0;
0401 }
0402
0403 static int ntb_epf_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
0404 dma_addr_t addr, resource_size_t size)
0405 {
0406 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0407 struct device *dev = ndev->dev;
0408 resource_size_t mw_size;
0409 int bar;
0410
0411 if (pidx != NTB_DEF_PEER_IDX) {
0412 dev_err(dev, "Unsupported Peer ID %d\n", pidx);
0413 return -EINVAL;
0414 }
0415
0416 bar = idx + ndev->mw_bar;
0417
0418 mw_size = pci_resource_len(ntb->pdev, bar);
0419
0420 if (size > mw_size) {
0421 dev_err(dev, "Size:%pa is greater than the MW size %pa\n",
0422 &size, &mw_size);
0423 return -EINVAL;
0424 }
0425
0426 writel(lower_32_bits(addr), ndev->ctrl_reg + NTB_EPF_LOWER_ADDR);
0427 writel(upper_32_bits(addr), ndev->ctrl_reg + NTB_EPF_UPPER_ADDR);
0428 writel(lower_32_bits(size), ndev->ctrl_reg + NTB_EPF_LOWER_SIZE);
0429 writel(upper_32_bits(size), ndev->ctrl_reg + NTB_EPF_UPPER_SIZE);
0430 ntb_epf_send_command(ndev, CMD_CONFIGURE_MW, idx);
0431
0432 return 0;
0433 }
0434
0435 static int ntb_epf_mw_clear_trans(struct ntb_dev *ntb, int pidx, int idx)
0436 {
0437 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0438 struct device *dev = ndev->dev;
0439 int ret = 0;
0440
0441 ntb_epf_send_command(ndev, CMD_TEARDOWN_MW, idx);
0442 if (ret)
0443 dev_err(dev, "Failed to teardown memory window\n");
0444
0445 return ret;
0446 }
0447
0448 static int ntb_epf_peer_mw_get_addr(struct ntb_dev *ntb, int idx,
0449 phys_addr_t *base, resource_size_t *size)
0450 {
0451 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0452 u32 offset = 0;
0453 int bar;
0454
0455 if (idx == 0)
0456 offset = readl(ndev->ctrl_reg + NTB_EPF_MW1_OFFSET);
0457
0458 bar = idx + ndev->mw_bar;
0459
0460 if (base)
0461 *base = pci_resource_start(ndev->ntb.pdev, bar) + offset;
0462
0463 if (size)
0464 *size = pci_resource_len(ndev->ntb.pdev, bar) - offset;
0465
0466 return 0;
0467 }
0468
0469 static int ntb_epf_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
0470 {
0471 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0472 u32 interrupt_num = ffs(db_bits) + 1;
0473 struct device *dev = ndev->dev;
0474 u32 db_entry_size;
0475 u32 db_offset;
0476 u32 db_data;
0477
0478 if (interrupt_num > ndev->db_count) {
0479 dev_err(dev, "DB interrupt %d greater than Max Supported %d\n",
0480 interrupt_num, ndev->db_count);
0481 return -EINVAL;
0482 }
0483
0484 db_entry_size = readl(ndev->ctrl_reg + NTB_EPF_DB_ENTRY_SIZE);
0485
0486 db_data = readl(ndev->ctrl_reg + NTB_EPF_DB_DATA(interrupt_num));
0487 db_offset = readl(ndev->ctrl_reg + NTB_EPF_DB_OFFSET(interrupt_num));
0488 writel(db_data, ndev->db_reg + (db_entry_size * interrupt_num) +
0489 db_offset);
0490
0491 return 0;
0492 }
0493
0494 static u64 ntb_epf_db_read(struct ntb_dev *ntb)
0495 {
0496 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0497
0498 return ndev->db_val;
0499 }
0500
0501 static int ntb_epf_db_clear_mask(struct ntb_dev *ntb, u64 db_bits)
0502 {
0503 return 0;
0504 }
0505
0506 static int ntb_epf_db_clear(struct ntb_dev *ntb, u64 db_bits)
0507 {
0508 struct ntb_epf_dev *ndev = ntb_ndev(ntb);
0509
0510 ndev->db_val = 0;
0511
0512 return 0;
0513 }
0514
0515 static const struct ntb_dev_ops ntb_epf_ops = {
0516 .mw_count = ntb_epf_mw_count,
0517 .spad_count = ntb_epf_spad_count,
0518 .peer_mw_count = ntb_epf_peer_mw_count,
0519 .db_valid_mask = ntb_epf_db_valid_mask,
0520 .db_set_mask = ntb_epf_db_set_mask,
0521 .mw_set_trans = ntb_epf_mw_set_trans,
0522 .mw_clear_trans = ntb_epf_mw_clear_trans,
0523 .peer_mw_get_addr = ntb_epf_peer_mw_get_addr,
0524 .link_enable = ntb_epf_link_enable,
0525 .spad_read = ntb_epf_spad_read,
0526 .spad_write = ntb_epf_spad_write,
0527 .peer_spad_read = ntb_epf_peer_spad_read,
0528 .peer_spad_write = ntb_epf_peer_spad_write,
0529 .peer_db_set = ntb_epf_peer_db_set,
0530 .db_read = ntb_epf_db_read,
0531 .mw_get_align = ntb_epf_mw_get_align,
0532 .link_is_up = ntb_epf_link_is_up,
0533 .db_clear_mask = ntb_epf_db_clear_mask,
0534 .db_clear = ntb_epf_db_clear,
0535 .link_disable = ntb_epf_link_disable,
0536 };
0537
0538 static inline void ntb_epf_init_struct(struct ntb_epf_dev *ndev,
0539 struct pci_dev *pdev)
0540 {
0541 ndev->ntb.pdev = pdev;
0542 ndev->ntb.topo = NTB_TOPO_NONE;
0543 ndev->ntb.ops = &ntb_epf_ops;
0544 }
0545
0546 static int ntb_epf_init_dev(struct ntb_epf_dev *ndev)
0547 {
0548 struct device *dev = ndev->dev;
0549 int ret;
0550
0551
0552 ret = ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + 1,
0553 NTB_EPF_MAX_DB_COUNT + 1);
0554 if (ret) {
0555 dev_err(dev, "Failed to init ISR\n");
0556 return ret;
0557 }
0558
0559 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
0560 ndev->mw_count = readl(ndev->ctrl_reg + NTB_EPF_MW_COUNT);
0561 ndev->spad_count = readl(ndev->ctrl_reg + NTB_EPF_SPAD_COUNT);
0562
0563 return 0;
0564 }
0565
0566 static int ntb_epf_init_pci(struct ntb_epf_dev *ndev,
0567 struct pci_dev *pdev)
0568 {
0569 struct device *dev = ndev->dev;
0570 size_t spad_sz, spad_off;
0571 int ret;
0572
0573 pci_set_drvdata(pdev, ndev);
0574
0575 ret = pci_enable_device(pdev);
0576 if (ret) {
0577 dev_err(dev, "Cannot enable PCI device\n");
0578 goto err_pci_enable;
0579 }
0580
0581 ret = pci_request_regions(pdev, "ntb");
0582 if (ret) {
0583 dev_err(dev, "Cannot obtain PCI resources\n");
0584 goto err_pci_regions;
0585 }
0586
0587 pci_set_master(pdev);
0588
0589 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
0590 if (ret) {
0591 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0592 if (ret) {
0593 dev_err(dev, "Cannot set DMA mask\n");
0594 goto err_dma_mask;
0595 }
0596 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
0597 }
0598
0599 ndev->ctrl_reg = pci_iomap(pdev, ndev->ctrl_reg_bar, 0);
0600 if (!ndev->ctrl_reg) {
0601 ret = -EIO;
0602 goto err_dma_mask;
0603 }
0604
0605 if (ndev->peer_spad_reg_bar) {
0606 ndev->peer_spad_reg = pci_iomap(pdev, ndev->peer_spad_reg_bar, 0);
0607 if (!ndev->peer_spad_reg) {
0608 ret = -EIO;
0609 goto err_dma_mask;
0610 }
0611 } else {
0612 spad_sz = 4 * readl(ndev->ctrl_reg + NTB_EPF_SPAD_COUNT);
0613 spad_off = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET);
0614 ndev->peer_spad_reg = ndev->ctrl_reg + spad_off + spad_sz;
0615 }
0616
0617 ndev->db_reg = pci_iomap(pdev, ndev->db_reg_bar, 0);
0618 if (!ndev->db_reg) {
0619 ret = -EIO;
0620 goto err_dma_mask;
0621 }
0622
0623 return 0;
0624
0625 err_dma_mask:
0626 pci_clear_master(pdev);
0627
0628 err_pci_regions:
0629 pci_disable_device(pdev);
0630
0631 err_pci_enable:
0632 pci_set_drvdata(pdev, NULL);
0633
0634 return ret;
0635 }
0636
0637 static void ntb_epf_deinit_pci(struct ntb_epf_dev *ndev)
0638 {
0639 struct pci_dev *pdev = ndev->ntb.pdev;
0640
0641 pci_iounmap(pdev, ndev->ctrl_reg);
0642 pci_iounmap(pdev, ndev->peer_spad_reg);
0643 pci_iounmap(pdev, ndev->db_reg);
0644
0645 pci_clear_master(pdev);
0646 pci_release_regions(pdev);
0647 pci_disable_device(pdev);
0648 pci_set_drvdata(pdev, NULL);
0649 }
0650
0651 static void ntb_epf_cleanup_isr(struct ntb_epf_dev *ndev)
0652 {
0653 struct pci_dev *pdev = ndev->ntb.pdev;
0654 int i;
0655
0656 ntb_epf_send_command(ndev, CMD_TEARDOWN_DOORBELL, ndev->db_count + 1);
0657
0658 for (i = 0; i < ndev->db_count + 1; i++)
0659 free_irq(pci_irq_vector(pdev, i), ndev);
0660 pci_free_irq_vectors(pdev);
0661 }
0662
0663 static int ntb_epf_pci_probe(struct pci_dev *pdev,
0664 const struct pci_device_id *id)
0665 {
0666 enum pci_barno peer_spad_reg_bar = BAR_1;
0667 enum pci_barno ctrl_reg_bar = BAR_0;
0668 enum pci_barno db_reg_bar = BAR_2;
0669 enum pci_barno mw_bar = BAR_2;
0670 struct device *dev = &pdev->dev;
0671 struct ntb_epf_data *data;
0672 struct ntb_epf_dev *ndev;
0673 int ret;
0674
0675 if (pci_is_bridge(pdev))
0676 return -ENODEV;
0677
0678 ndev = devm_kzalloc(dev, sizeof(*ndev), GFP_KERNEL);
0679 if (!ndev)
0680 return -ENOMEM;
0681
0682 data = (struct ntb_epf_data *)id->driver_data;
0683 if (data) {
0684 peer_spad_reg_bar = data->peer_spad_reg_bar;
0685 ctrl_reg_bar = data->ctrl_reg_bar;
0686 db_reg_bar = data->db_reg_bar;
0687 mw_bar = data->mw_bar;
0688 }
0689
0690 ndev->peer_spad_reg_bar = peer_spad_reg_bar;
0691 ndev->ctrl_reg_bar = ctrl_reg_bar;
0692 ndev->db_reg_bar = db_reg_bar;
0693 ndev->mw_bar = mw_bar;
0694 ndev->dev = dev;
0695
0696 ntb_epf_init_struct(ndev, pdev);
0697 mutex_init(&ndev->cmd_lock);
0698
0699 ret = ntb_epf_init_pci(ndev, pdev);
0700 if (ret) {
0701 dev_err(dev, "Failed to init PCI\n");
0702 return ret;
0703 }
0704
0705 ret = ntb_epf_init_dev(ndev);
0706 if (ret) {
0707 dev_err(dev, "Failed to init device\n");
0708 goto err_init_dev;
0709 }
0710
0711 ret = ntb_register_device(&ndev->ntb);
0712 if (ret) {
0713 dev_err(dev, "Failed to register NTB device\n");
0714 goto err_register_dev;
0715 }
0716
0717 return 0;
0718
0719 err_register_dev:
0720 ntb_epf_cleanup_isr(ndev);
0721
0722 err_init_dev:
0723 ntb_epf_deinit_pci(ndev);
0724
0725 return ret;
0726 }
0727
0728 static void ntb_epf_pci_remove(struct pci_dev *pdev)
0729 {
0730 struct ntb_epf_dev *ndev = pci_get_drvdata(pdev);
0731
0732 ntb_unregister_device(&ndev->ntb);
0733 ntb_epf_cleanup_isr(ndev);
0734 ntb_epf_deinit_pci(ndev);
0735 }
0736
0737 static const struct ntb_epf_data j721e_data = {
0738 .ctrl_reg_bar = BAR_0,
0739 .peer_spad_reg_bar = BAR_1,
0740 .db_reg_bar = BAR_2,
0741 .mw_bar = BAR_2,
0742 };
0743
0744 static const struct ntb_epf_data mx8_data = {
0745 .ctrl_reg_bar = BAR_0,
0746 .peer_spad_reg_bar = BAR_0,
0747 .db_reg_bar = BAR_2,
0748 .mw_bar = BAR_4,
0749 };
0750
0751 static const struct pci_device_id ntb_epf_pci_tbl[] = {
0752 {
0753 PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
0754 .class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,
0755 .driver_data = (kernel_ulong_t)&j721e_data,
0756 },
0757 {
0758 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x0809),
0759 .class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,
0760 .driver_data = (kernel_ulong_t)&mx8_data,
0761 },
0762 { },
0763 };
0764
0765 static struct pci_driver ntb_epf_pci_driver = {
0766 .name = KBUILD_MODNAME,
0767 .id_table = ntb_epf_pci_tbl,
0768 .probe = ntb_epf_pci_probe,
0769 .remove = ntb_epf_pci_remove,
0770 };
0771 module_pci_driver(ntb_epf_pci_driver);
0772
0773 MODULE_DESCRIPTION("PCI ENDPOINT NTB HOST DRIVER");
0774 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
0775 MODULE_LICENSE("GPL v2");
