nfc/s3fwrn5/nci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * NCI based driver for Samsung S3FWRN5 NFC chip
0004  *
0005  * Copyright (C) 2015 Samsung Electrnoics
0006  * Robert Baldyga <r.baldyga@samsung.com>
0007  */
0008
0009 #include <linux/completion.h>
0010 #include <linux/firmware.h>
0011
0012 #include "s3fwrn5.h"
0013 #include "nci.h"
0014
0015 static int s3fwrn5_nci_prop_rsp(struct nci_dev *ndev, struct sk_buff *skb)
0016 {
0017     __u8 status = skb->data[0];
0018
0019     nci_req_complete(ndev, status);
0020     return 0;
0021 }
0022
0023 const struct nci_driver_ops s3fwrn5_nci_prop_ops[4] = {
0024     {
0025         .opcode = nci_opcode_pack(NCI_GID_PROPRIETARY,
0026                 NCI_PROP_SET_RFREG),
0027         .rsp = s3fwrn5_nci_prop_rsp,
0028     },
0029     {
0030         .opcode = nci_opcode_pack(NCI_GID_PROPRIETARY,
0031                 NCI_PROP_START_RFREG),
0032         .rsp = s3fwrn5_nci_prop_rsp,
0033     },
0034     {
0035         .opcode = nci_opcode_pack(NCI_GID_PROPRIETARY,
0036                 NCI_PROP_STOP_RFREG),
0037         .rsp = s3fwrn5_nci_prop_rsp,
0038     },
0039     {
0040         .opcode = nci_opcode_pack(NCI_GID_PROPRIETARY,
0041                 NCI_PROP_FW_CFG),
0042         .rsp = s3fwrn5_nci_prop_rsp,
0043     },
0044 };
0045
0046 #define S3FWRN5_RFREG_SECTION_SIZE 252
0047
0048 int s3fwrn5_nci_rf_configure(struct s3fwrn5_info *info, const char *fw_name)
0049 {
0050     struct device *dev = &info->ndev->nfc_dev->dev;
0051     const struct firmware *fw;
0052     struct nci_prop_fw_cfg_cmd fw_cfg;
0053     struct nci_prop_set_rfreg_cmd set_rfreg;
0054     struct nci_prop_stop_rfreg_cmd stop_rfreg;
0055     u32 checksum;
0056     int i, len;
0057     int ret;
0058
0059     ret = request_firmware(&fw, fw_name, dev);
0060     if (ret < 0)
0061         return ret;
0062
0063     /* Compute rfreg checksum */
0064
0065     checksum = 0;
0066     for (i = 0; i < fw->size; i += 4)
0067         checksum += *((u32 *)(fw->data+i));
0068
0069     /* Set default clock configuration for external crystal */
0070
0071     fw_cfg.clk_type = 0x01;
0072     fw_cfg.clk_speed = 0xff;
0073     fw_cfg.clk_req = 0xff;
0074     ret = nci_prop_cmd(info->ndev, NCI_PROP_FW_CFG,
0075         sizeof(fw_cfg), (__u8 *)&fw_cfg);
0076     if (ret < 0)
0077         goto out;
0078
0079     /* Start rfreg configuration */
0080
0081     dev_info(dev, "rfreg configuration update: %s\n", fw_name);
0082
0083     ret = nci_prop_cmd(info->ndev, NCI_PROP_START_RFREG, 0, NULL);
0084     if (ret < 0) {
0085         dev_err(dev, "Unable to start rfreg update\n");
0086         goto out;
0087     }
0088
0089     /* Update rfreg */
0090
0091     set_rfreg.index = 0;
0092     for (i = 0; i < fw->size; i += S3FWRN5_RFREG_SECTION_SIZE) {
0093         len = (fw->size - i < S3FWRN5_RFREG_SECTION_SIZE) ?
0094             (fw->size - i) : S3FWRN5_RFREG_SECTION_SIZE;
0095         memcpy(set_rfreg.data, fw->data+i, len);
0096         ret = nci_prop_cmd(info->ndev, NCI_PROP_SET_RFREG,
0097             len+1, (__u8 *)&set_rfreg);
0098         if (ret < 0) {
0099             dev_err(dev, "rfreg update error (code=%d)\n", ret);
0100             goto out;
0101         }
0102         set_rfreg.index++;
0103     }
0104
0105     /* Finish rfreg configuration */
0106
0107     stop_rfreg.checksum = checksum & 0xffff;
0108     ret = nci_prop_cmd(info->ndev, NCI_PROP_STOP_RFREG,
0109         sizeof(stop_rfreg), (__u8 *)&stop_rfreg);
0110     if (ret < 0) {
0111         dev_err(dev, "Unable to stop rfreg update\n");
0112         goto out;
0113     }
0114
0115     dev_info(dev, "rfreg configuration update: success\n");
0116 out:
0117     release_firmware(fw);
0118     return ret;
0119 }