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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * I2C Link Layer for PN544 HCI based Driver
0004  *
0005  * Copyright (C) 2012  Intel Corporation. All rights reserved.
0006  */
0007 
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009 
0010 #include <linux/crc-ccitt.h>
0011 #include <linux/module.h>
0012 #include <linux/i2c.h>
0013 #include <linux/acpi.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/delay.h>
0016 #include <linux/nfc.h>
0017 #include <linux/firmware.h>
0018 #include <linux/gpio/consumer.h>
0019 
0020 #include <asm/unaligned.h>
0021 
0022 #include <net/nfc/hci.h>
0023 #include <net/nfc/llc.h>
0024 #include <net/nfc/nfc.h>
0025 
0026 #include "pn544.h"
0027 
0028 #define PN544_I2C_FRAME_HEADROOM 1
0029 #define PN544_I2C_FRAME_TAILROOM 2
0030 
0031 /* GPIO names */
0032 #define PN544_GPIO_NAME_IRQ "pn544_irq"
0033 #define PN544_GPIO_NAME_FW  "pn544_fw"
0034 #define PN544_GPIO_NAME_EN  "pn544_en"
0035 
0036 /* framing in HCI mode */
0037 #define PN544_HCI_I2C_LLC_LEN       1
0038 #define PN544_HCI_I2C_LLC_CRC       2
0039 #define PN544_HCI_I2C_LLC_LEN_CRC   (PN544_HCI_I2C_LLC_LEN + \
0040                      PN544_HCI_I2C_LLC_CRC)
0041 #define PN544_HCI_I2C_LLC_MIN_SIZE  (1 + PN544_HCI_I2C_LLC_LEN_CRC)
0042 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD   29
0043 #define PN544_HCI_I2C_LLC_MAX_SIZE  (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \
0044                      PN544_HCI_I2C_LLC_MAX_PAYLOAD)
0045 
0046 static const struct i2c_device_id pn544_hci_i2c_id_table[] = {
0047     {"pn544", 0},
0048     {}
0049 };
0050 
0051 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table);
0052 
0053 static const struct acpi_device_id pn544_hci_i2c_acpi_match[] __maybe_unused = {
0054     {"NXP5440", 0},
0055     {}
0056 };
0057 
0058 MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
0059 
0060 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
0061 
0062 /*
0063  * Exposed through the 4 most significant bytes
0064  * from the HCI SW_VERSION first byte, a.k.a.
0065  * SW RomLib.
0066  */
0067 #define PN544_HW_VARIANT_C2 0xa
0068 #define PN544_HW_VARIANT_C3 0xb
0069 
0070 #define PN544_FW_CMD_RESET 0x01
0071 #define PN544_FW_CMD_WRITE 0x08
0072 #define PN544_FW_CMD_CHECK 0x06
0073 #define PN544_FW_CMD_SECURE_WRITE 0x0C
0074 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D
0075 
0076 struct pn544_i2c_fw_frame_write {
0077     u8 cmd;
0078     u16 be_length;
0079     u8 be_dest_addr[3];
0080     u16 be_datalen;
0081     u8 data[];
0082 } __packed;
0083 
0084 struct pn544_i2c_fw_frame_check {
0085     u8 cmd;
0086     u16 be_length;
0087     u8 be_start_addr[3];
0088     u16 be_datalen;
0089     u16 be_crc;
0090 } __packed;
0091 
0092 struct pn544_i2c_fw_frame_response {
0093     u8 status;
0094     u16 be_length;
0095 } __packed;
0096 
0097 struct pn544_i2c_fw_blob {
0098     u32 be_size;
0099     u32 be_destaddr;
0100     u8 data[];
0101 };
0102 
0103 struct pn544_i2c_fw_secure_frame {
0104     u8 cmd;
0105     u16 be_datalen;
0106     u8 data[];
0107 } __packed;
0108 
0109 struct pn544_i2c_fw_secure_blob {
0110     u64 header;
0111     u8 data[];
0112 };
0113 
0114 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01
0115 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02
0116 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
0117 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
0118 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
0119 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13
0120 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
0121 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19
0122 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D
0123 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20
0124 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21
0125 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
0126 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0
0127 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6
0128 
0129 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
0130 
0131 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
0132 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
0133 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
0134 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
0135                      PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
0136                      PN544_FW_WRITE_BUFFER_MAX_LEN)
0137 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3
0138 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\
0139             PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN)
0140 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3
0141 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8
0142 
0143 #define FW_WORK_STATE_IDLE 1
0144 #define FW_WORK_STATE_START 2
0145 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
0146 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
0147 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5
0148 
0149 struct pn544_i2c_phy {
0150     struct i2c_client *i2c_dev;
0151     struct nfc_hci_dev *hdev;
0152 
0153     struct gpio_desc *gpiod_en;
0154     struct gpio_desc *gpiod_fw;
0155 
0156     unsigned int en_polarity;
0157 
0158     u8 hw_variant;
0159 
0160     struct work_struct fw_work;
0161     int fw_work_state;
0162     char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1];
0163     const struct firmware *fw;
0164     u32 fw_blob_dest_addr;
0165     size_t fw_blob_size;
0166     const u8 *fw_blob_data;
0167     size_t fw_written;
0168     size_t fw_size;
0169 
0170     int fw_cmd_result;
0171 
0172     int powered;
0173     int run_mode;
0174 
0175     int hard_fault;     /*
0176                  * < 0 if hardware error occured (e.g. i2c err)
0177                  * and prevents normal operation.
0178                  */
0179 };
0180 
0181 #define I2C_DUMP_SKB(info, skb)                 \
0182 do {                                \
0183     pr_debug("%s:\n", info);                \
0184     print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \
0185                16, 1, (skb)->data, (skb)->len, 0);  \
0186 } while (0)
0187 
0188 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy)
0189 {
0190     int polarity, retry, ret;
0191     static const char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
0192     int count = sizeof(rset_cmd);
0193 
0194     nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n");
0195 
0196     /* Disable fw download */
0197     gpiod_set_value_cansleep(phy->gpiod_fw, 0);
0198 
0199     for (polarity = 0; polarity < 2; polarity++) {
0200         phy->en_polarity = polarity;
0201         retry = 3;
0202         while (retry--) {
0203             /* power off */
0204             gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
0205             usleep_range(10000, 15000);
0206 
0207             /* power on */
0208             gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
0209             usleep_range(10000, 15000);
0210 
0211             /* send reset */
0212             dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n");
0213             ret = i2c_master_send(phy->i2c_dev, rset_cmd, count);
0214             if (ret == count) {
0215                 nfc_info(&phy->i2c_dev->dev,
0216                      "nfc_en polarity : active %s\n",
0217                      (polarity == 0 ? "low" : "high"));
0218                 goto out;
0219             }
0220         }
0221     }
0222 
0223     nfc_err(&phy->i2c_dev->dev,
0224         "Could not detect nfc_en polarity, fallback to active high\n");
0225 
0226 out:
0227     gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
0228     usleep_range(10000, 15000);
0229 }
0230 
0231 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
0232 {
0233     gpiod_set_value_cansleep(phy->gpiod_fw, run_mode == PN544_FW_MODE ? 1 : 0);
0234     gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
0235     usleep_range(10000, 15000);
0236 
0237     phy->run_mode = run_mode;
0238 }
0239 
0240 static int pn544_hci_i2c_enable(void *phy_id)
0241 {
0242     struct pn544_i2c_phy *phy = phy_id;
0243 
0244     pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
0245 
0246     phy->powered = 1;
0247 
0248     return 0;
0249 }
0250 
0251 static void pn544_hci_i2c_disable(void *phy_id)
0252 {
0253     struct pn544_i2c_phy *phy = phy_id;
0254 
0255     gpiod_set_value_cansleep(phy->gpiod_fw, 0);
0256     gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
0257     usleep_range(10000, 15000);
0258 
0259     gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
0260     usleep_range(10000, 15000);
0261 
0262     gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
0263     usleep_range(10000, 15000);
0264 
0265     phy->powered = 0;
0266 }
0267 
0268 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb)
0269 {
0270     u16 crc;
0271     int len;
0272 
0273     len = skb->len + 2;
0274     *(u8 *)skb_push(skb, 1) = len;
0275 
0276     crc = crc_ccitt(0xffff, skb->data, skb->len);
0277     crc = ~crc;
0278     skb_put_u8(skb, crc & 0xff);
0279     skb_put_u8(skb, crc >> 8);
0280 }
0281 
0282 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb)
0283 {
0284     skb_pull(skb, PN544_I2C_FRAME_HEADROOM);
0285     skb_trim(skb, PN544_I2C_FRAME_TAILROOM);
0286 }
0287 
0288 /*
0289  * Writing a frame must not return the number of written bytes.
0290  * It must return either zero for success, or <0 for error.
0291  * In addition, it must not alter the skb
0292  */
0293 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb)
0294 {
0295     int r;
0296     struct pn544_i2c_phy *phy = phy_id;
0297     struct i2c_client *client = phy->i2c_dev;
0298 
0299     if (phy->hard_fault != 0)
0300         return phy->hard_fault;
0301 
0302     usleep_range(3000, 6000);
0303 
0304     pn544_hci_i2c_add_len_crc(skb);
0305 
0306     I2C_DUMP_SKB("i2c frame written", skb);
0307 
0308     r = i2c_master_send(client, skb->data, skb->len);
0309 
0310     if (r == -EREMOTEIO) {  /* Retry, chip was in standby */
0311         usleep_range(6000, 10000);
0312         r = i2c_master_send(client, skb->data, skb->len);
0313     }
0314 
0315     if (r >= 0) {
0316         if (r != skb->len)
0317             r = -EREMOTEIO;
0318         else
0319             r = 0;
0320     }
0321 
0322     pn544_hci_i2c_remove_len_crc(skb);
0323 
0324     return r;
0325 }
0326 
0327 static int check_crc(u8 *buf, int buflen)
0328 {
0329     int len;
0330     u16 crc;
0331 
0332     len = buf[0] + 1;
0333     crc = crc_ccitt(0xffff, buf, len - 2);
0334     crc = ~crc;
0335 
0336     if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
0337         pr_err("CRC error 0x%x != 0x%x 0x%x\n",
0338                crc, buf[len - 1], buf[len - 2]);
0339         pr_info("%s: BAD CRC\n", __func__);
0340         print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
0341                    16, 2, buf, buflen, false);
0342         return -EPERM;
0343     }
0344     return 0;
0345 }
0346 
0347 /*
0348  * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
0349  * that i2c bus will be flushed and that next read will start on a new frame.
0350  * returned skb contains only LLC header and payload.
0351  * returns:
0352  * -EREMOTEIO : i2c read error (fatal)
0353  * -EBADMSG : frame was incorrect and discarded
0354  * -ENOMEM : cannot allocate skb, frame dropped
0355  */
0356 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
0357 {
0358     int r;
0359     u8 len;
0360     u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1];
0361     struct i2c_client *client = phy->i2c_dev;
0362 
0363     r = i2c_master_recv(client, &len, 1);
0364     if (r != 1) {
0365         nfc_err(&client->dev, "cannot read len byte\n");
0366         return -EREMOTEIO;
0367     }
0368 
0369     if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
0370         (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
0371         nfc_err(&client->dev, "invalid len byte\n");
0372         r = -EBADMSG;
0373         goto flush;
0374     }
0375 
0376     *skb = alloc_skb(1 + len, GFP_KERNEL);
0377     if (*skb == NULL) {
0378         r = -ENOMEM;
0379         goto flush;
0380     }
0381 
0382     skb_put_u8(*skb, len);
0383 
0384     r = i2c_master_recv(client, skb_put(*skb, len), len);
0385     if (r != len) {
0386         kfree_skb(*skb);
0387         return -EREMOTEIO;
0388     }
0389 
0390     I2C_DUMP_SKB("i2c frame read", *skb);
0391 
0392     r = check_crc((*skb)->data, (*skb)->len);
0393     if (r != 0) {
0394         kfree_skb(*skb);
0395         r = -EBADMSG;
0396         goto flush;
0397     }
0398 
0399     skb_pull(*skb, 1);
0400     skb_trim(*skb, (*skb)->len - 2);
0401 
0402     usleep_range(3000, 6000);
0403 
0404     return 0;
0405 
0406 flush:
0407     if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
0408         r = -EREMOTEIO;
0409 
0410     usleep_range(3000, 6000);
0411 
0412     return r;
0413 }
0414 
0415 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy)
0416 {
0417     int r;
0418     struct pn544_i2c_fw_frame_response response;
0419     struct i2c_client *client = phy->i2c_dev;
0420 
0421     r = i2c_master_recv(client, (char *) &response, sizeof(response));
0422     if (r != sizeof(response)) {
0423         nfc_err(&client->dev, "cannot read fw status\n");
0424         return -EIO;
0425     }
0426 
0427     usleep_range(3000, 6000);
0428 
0429     switch (response.status) {
0430     case 0:
0431         return 0;
0432     case PN544_FW_CMD_RESULT_CHUNK_OK:
0433         return response.status;
0434     case PN544_FW_CMD_RESULT_TIMEOUT:
0435         return -ETIMEDOUT;
0436     case PN544_FW_CMD_RESULT_BAD_CRC:
0437         return -ENODATA;
0438     case PN544_FW_CMD_RESULT_ACCESS_DENIED:
0439         return -EACCES;
0440     case PN544_FW_CMD_RESULT_PROTOCOL_ERROR:
0441         return -EPROTO;
0442     case PN544_FW_CMD_RESULT_INVALID_PARAMETER:
0443         return -EINVAL;
0444     case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND:
0445         return -ENOTSUPP;
0446     case PN544_FW_CMD_RESULT_INVALID_LENGTH:
0447         return -EBADMSG;
0448     case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR:
0449         return -ENOKEY;
0450     case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR:
0451         return -EINVAL;
0452     case PN544_FW_CMD_RESULT_MEMORY_ERROR:
0453         return -ENOMEM;
0454     case PN544_FW_CMD_RESULT_COMMAND_REJECTED:
0455         return -EACCES;
0456     case PN544_FW_CMD_RESULT_WRITE_FAILED:
0457     case PN544_FW_CMD_RESULT_CHUNK_ERROR:
0458         return -EIO;
0459     default:
0460         return -EIO;
0461     }
0462 }
0463 
0464 /*
0465  * Reads an shdlc frame from the chip. This is not as straightforward as it
0466  * seems. There are cases where we could loose the frame start synchronization.
0467  * The frame format is len-data-crc, and corruption can occur anywhere while
0468  * transiting on i2c bus, such that we could read an invalid len.
0469  * In order to recover synchronization with the next frame, we must be sure
0470  * to read the real amount of data without using the len byte. We do this by
0471  * assuming the following:
0472  * - the chip will always present only one single complete frame on the bus
0473  *   before triggering the interrupt
0474  * - the chip will not present a new frame until we have completely read
0475  *   the previous one (or until we have handled the interrupt).
0476  * The tricky case is when we read a corrupted len that is less than the real
0477  * len. We must detect this here in order to determine that we need to flush
0478  * the bus. This is the reason why we check the crc here.
0479  */
0480 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id)
0481 {
0482     struct pn544_i2c_phy *phy = phy_id;
0483     struct i2c_client *client;
0484     struct sk_buff *skb = NULL;
0485     int r;
0486 
0487     if (!phy || irq != phy->i2c_dev->irq) {
0488         WARN_ON_ONCE(1);
0489         return IRQ_NONE;
0490     }
0491 
0492     client = phy->i2c_dev;
0493     dev_dbg(&client->dev, "IRQ\n");
0494 
0495     if (phy->hard_fault != 0)
0496         return IRQ_HANDLED;
0497 
0498     if (phy->run_mode == PN544_FW_MODE) {
0499         phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy);
0500         schedule_work(&phy->fw_work);
0501     } else {
0502         r = pn544_hci_i2c_read(phy, &skb);
0503         if (r == -EREMOTEIO) {
0504             phy->hard_fault = r;
0505 
0506             nfc_hci_recv_frame(phy->hdev, NULL);
0507 
0508             return IRQ_HANDLED;
0509         } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
0510             return IRQ_HANDLED;
0511         }
0512 
0513         nfc_hci_recv_frame(phy->hdev, skb);
0514     }
0515     return IRQ_HANDLED;
0516 }
0517 
0518 static const struct nfc_phy_ops i2c_phy_ops = {
0519     .write = pn544_hci_i2c_write,
0520     .enable = pn544_hci_i2c_enable,
0521     .disable = pn544_hci_i2c_disable,
0522 };
0523 
0524 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name,
0525                     u8 hw_variant)
0526 {
0527     struct pn544_i2c_phy *phy = phy_id;
0528 
0529     pr_info("Starting Firmware Download (%s)\n", firmware_name);
0530 
0531     strcpy(phy->firmware_name, firmware_name);
0532 
0533     phy->hw_variant = hw_variant;
0534     phy->fw_work_state = FW_WORK_STATE_START;
0535 
0536     schedule_work(&phy->fw_work);
0537 
0538     return 0;
0539 }
0540 
0541 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy,
0542                        int result)
0543 {
0544     pr_info("Firmware Download Complete, result=%d\n", result);
0545 
0546     pn544_hci_i2c_disable(phy);
0547 
0548     phy->fw_work_state = FW_WORK_STATE_IDLE;
0549 
0550     if (phy->fw) {
0551         release_firmware(phy->fw);
0552         phy->fw = NULL;
0553     }
0554 
0555     nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result);
0556 }
0557 
0558 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr,
0559                       const u8 *data, u16 datalen)
0560 {
0561     u8 frame[PN544_FW_I2C_MAX_PAYLOAD];
0562     struct pn544_i2c_fw_frame_write *framep;
0563     u16 params_len;
0564     int framelen;
0565     int r;
0566 
0567     if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN)
0568         datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN;
0569 
0570     framep = (struct pn544_i2c_fw_frame_write *) frame;
0571 
0572     params_len = sizeof(framep->be_dest_addr) +
0573              sizeof(framep->be_datalen) + datalen;
0574     framelen = params_len + sizeof(framep->cmd) +
0575                  sizeof(framep->be_length);
0576 
0577     framep->cmd = PN544_FW_CMD_WRITE;
0578 
0579     put_unaligned_be16(params_len, &framep->be_length);
0580 
0581     framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16;
0582     framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8;
0583     framep->be_dest_addr[2] = dest_addr & 0xff;
0584 
0585     put_unaligned_be16(datalen, &framep->be_datalen);
0586 
0587     memcpy(framep->data, data, datalen);
0588 
0589     r = i2c_master_send(client, frame, framelen);
0590 
0591     if (r == framelen)
0592         return datalen;
0593     else if (r < 0)
0594         return r;
0595     else
0596         return -EIO;
0597 }
0598 
0599 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr,
0600                       const u8 *data, u16 datalen)
0601 {
0602     struct pn544_i2c_fw_frame_check frame;
0603     int r;
0604     u16 crc;
0605 
0606     /* calculate local crc for the data we want to check */
0607     crc = crc_ccitt(0xffff, data, datalen);
0608 
0609     frame.cmd = PN544_FW_CMD_CHECK;
0610 
0611     put_unaligned_be16(sizeof(frame.be_start_addr) +
0612                sizeof(frame.be_datalen) + sizeof(frame.be_crc),
0613                &frame.be_length);
0614 
0615     /* tell the chip the memory region to which our crc applies */
0616     frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16;
0617     frame.be_start_addr[1] = (start_addr & 0xff00) >> 8;
0618     frame.be_start_addr[2] = start_addr & 0xff;
0619 
0620     put_unaligned_be16(datalen, &frame.be_datalen);
0621 
0622     /*
0623      * and give our local crc. Chip will calculate its own crc for the
0624      * region and compare with ours.
0625      */
0626     put_unaligned_be16(crc, &frame.be_crc);
0627 
0628     r = i2c_master_send(client, (const char *) &frame, sizeof(frame));
0629 
0630     if (r == sizeof(frame))
0631         return 0;
0632     else if (r < 0)
0633         return r;
0634     else
0635         return -EIO;
0636 }
0637 
0638 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy)
0639 {
0640     int r;
0641 
0642     r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev,
0643                        phy->fw_blob_dest_addr + phy->fw_written,
0644                        phy->fw_blob_data + phy->fw_written,
0645                        phy->fw_blob_size - phy->fw_written);
0646     if (r < 0)
0647         return r;
0648 
0649     phy->fw_written += r;
0650     phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER;
0651 
0652     return 0;
0653 }
0654 
0655 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy,
0656                     const u8 *data, u16 datalen)
0657 {
0658     u8 buf[PN544_FW_I2C_MAX_PAYLOAD];
0659     struct pn544_i2c_fw_secure_frame *chunk;
0660     int chunklen;
0661     int r;
0662 
0663     if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN)
0664         datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN;
0665 
0666     chunk = (struct pn544_i2c_fw_secure_frame *) buf;
0667 
0668     chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE;
0669 
0670     put_unaligned_be16(datalen, &chunk->be_datalen);
0671 
0672     memcpy(chunk->data, data, datalen);
0673 
0674     chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen;
0675 
0676     r = i2c_master_send(phy->i2c_dev, buf, chunklen);
0677 
0678     if (r == chunklen)
0679         return datalen;
0680     else if (r < 0)
0681         return r;
0682     else
0683         return -EIO;
0684 
0685 }
0686 
0687 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy)
0688 {
0689     struct pn544_i2c_fw_secure_frame *framep;
0690     int r;
0691 
0692     framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data;
0693     if (phy->fw_written == 0)
0694         phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen)
0695                 + PN544_FW_SECURE_FRAME_HEADER_LEN;
0696 
0697     /* Only secure write command can be chunked*/
0698     if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD &&
0699             framep->cmd != PN544_FW_CMD_SECURE_WRITE)
0700         return -EINVAL;
0701 
0702     /* The firmware also have other commands, we just send them directly */
0703     if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) {
0704         r = i2c_master_send(phy->i2c_dev,
0705             (const char *) phy->fw_blob_data, phy->fw_blob_size);
0706 
0707         if (r == phy->fw_blob_size)
0708             goto exit;
0709         else if (r < 0)
0710             return r;
0711         else
0712             return -EIO;
0713     }
0714 
0715     r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy,
0716                        phy->fw_blob_data + phy->fw_written,
0717                        phy->fw_blob_size - phy->fw_written);
0718     if (r < 0)
0719         return r;
0720 
0721 exit:
0722     phy->fw_written += r;
0723     phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER;
0724 
0725     /* SW reset command will not trig any response from PN544 */
0726     if (framep->cmd == PN544_FW_CMD_RESET) {
0727         pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
0728         phy->fw_cmd_result = 0;
0729         schedule_work(&phy->fw_work);
0730     }
0731 
0732     return 0;
0733 }
0734 
0735 static void pn544_hci_i2c_fw_work(struct work_struct *work)
0736 {
0737     struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy,
0738                         fw_work);
0739     int r;
0740     struct pn544_i2c_fw_blob *blob;
0741     struct pn544_i2c_fw_secure_blob *secure_blob;
0742 
0743     switch (phy->fw_work_state) {
0744     case FW_WORK_STATE_START:
0745         pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
0746 
0747         r = request_firmware(&phy->fw, phy->firmware_name,
0748                      &phy->i2c_dev->dev);
0749         if (r < 0)
0750             goto exit_state_start;
0751 
0752         phy->fw_written = 0;
0753 
0754         switch (phy->hw_variant) {
0755         case PN544_HW_VARIANT_C2:
0756             blob = (struct pn544_i2c_fw_blob *) phy->fw->data;
0757             phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
0758             phy->fw_blob_dest_addr = get_unaligned_be32(
0759                             &blob->be_destaddr);
0760             phy->fw_blob_data = blob->data;
0761 
0762             r = pn544_hci_i2c_fw_write_chunk(phy);
0763             break;
0764         case PN544_HW_VARIANT_C3:
0765             secure_blob = (struct pn544_i2c_fw_secure_blob *)
0766                                 phy->fw->data;
0767             phy->fw_blob_data = secure_blob->data;
0768             phy->fw_size = phy->fw->size;
0769             r = pn544_hci_i2c_fw_secure_write_frame(phy);
0770             break;
0771         default:
0772             r = -ENOTSUPP;
0773             break;
0774         }
0775 
0776 exit_state_start:
0777         if (r < 0)
0778             pn544_hci_i2c_fw_work_complete(phy, r);
0779         break;
0780 
0781     case FW_WORK_STATE_WAIT_WRITE_ANSWER:
0782         r = phy->fw_cmd_result;
0783         if (r < 0)
0784             goto exit_state_wait_write_answer;
0785 
0786         if (phy->fw_written == phy->fw_blob_size) {
0787             r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev,
0788                                phy->fw_blob_dest_addr,
0789                                phy->fw_blob_data,
0790                                phy->fw_blob_size);
0791             if (r < 0)
0792                 goto exit_state_wait_write_answer;
0793             phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER;
0794             break;
0795         }
0796 
0797         r = pn544_hci_i2c_fw_write_chunk(phy);
0798 
0799 exit_state_wait_write_answer:
0800         if (r < 0)
0801             pn544_hci_i2c_fw_work_complete(phy, r);
0802         break;
0803 
0804     case FW_WORK_STATE_WAIT_CHECK_ANSWER:
0805         r = phy->fw_cmd_result;
0806         if (r < 0)
0807             goto exit_state_wait_check_answer;
0808 
0809         blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data +
0810                phy->fw_blob_size);
0811         phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
0812         if (phy->fw_blob_size != 0) {
0813             phy->fw_blob_dest_addr =
0814                     get_unaligned_be32(&blob->be_destaddr);
0815             phy->fw_blob_data = blob->data;
0816 
0817             phy->fw_written = 0;
0818             r = pn544_hci_i2c_fw_write_chunk(phy);
0819         }
0820 
0821 exit_state_wait_check_answer:
0822         if (r < 0 || phy->fw_blob_size == 0)
0823             pn544_hci_i2c_fw_work_complete(phy, r);
0824         break;
0825 
0826     case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER:
0827         r = phy->fw_cmd_result;
0828         if (r < 0)
0829             goto exit_state_wait_secure_write_answer;
0830 
0831         if (r == PN544_FW_CMD_RESULT_CHUNK_OK) {
0832             r = pn544_hci_i2c_fw_secure_write_frame(phy);
0833             goto exit_state_wait_secure_write_answer;
0834         }
0835 
0836         if (phy->fw_written == phy->fw_blob_size) {
0837             secure_blob = (struct pn544_i2c_fw_secure_blob *)
0838                 (phy->fw_blob_data + phy->fw_blob_size);
0839             phy->fw_size -= phy->fw_blob_size +
0840                 PN544_FW_SECURE_BLOB_HEADER_LEN;
0841             if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN
0842                     + PN544_FW_SECURE_FRAME_HEADER_LEN) {
0843                 phy->fw_blob_data = secure_blob->data;
0844 
0845                 phy->fw_written = 0;
0846                 r = pn544_hci_i2c_fw_secure_write_frame(phy);
0847             }
0848         }
0849 
0850 exit_state_wait_secure_write_answer:
0851         if (r < 0 || phy->fw_size == 0)
0852             pn544_hci_i2c_fw_work_complete(phy, r);
0853         break;
0854 
0855     default:
0856         break;
0857     }
0858 }
0859 
0860 static const struct acpi_gpio_params enable_gpios = { 1, 0, false };
0861 static const struct acpi_gpio_params firmware_gpios = { 2, 0, false };
0862 
0863 static const struct acpi_gpio_mapping acpi_pn544_gpios[] = {
0864     { "enable-gpios", &enable_gpios, 1 },
0865     { "firmware-gpios", &firmware_gpios, 1 },
0866     { },
0867 };
0868 
0869 static int pn544_hci_i2c_probe(struct i2c_client *client,
0870                    const struct i2c_device_id *id)
0871 {
0872     struct device *dev = &client->dev;
0873     struct pn544_i2c_phy *phy;
0874     int r = 0;
0875 
0876     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
0877         nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
0878         return -ENODEV;
0879     }
0880 
0881     phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy),
0882                GFP_KERNEL);
0883     if (!phy)
0884         return -ENOMEM;
0885 
0886     INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work);
0887     phy->fw_work_state = FW_WORK_STATE_IDLE;
0888 
0889     phy->i2c_dev = client;
0890     i2c_set_clientdata(client, phy);
0891 
0892     r = devm_acpi_dev_add_driver_gpios(dev, acpi_pn544_gpios);
0893     if (r)
0894         dev_dbg(dev, "Unable to add GPIO mapping table\n");
0895 
0896     /* Get EN GPIO */
0897     phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
0898     if (IS_ERR(phy->gpiod_en)) {
0899         nfc_err(dev, "Unable to get EN GPIO\n");
0900         return PTR_ERR(phy->gpiod_en);
0901     }
0902 
0903     /* Get FW GPIO */
0904     phy->gpiod_fw = devm_gpiod_get(dev, "firmware", GPIOD_OUT_LOW);
0905     if (IS_ERR(phy->gpiod_fw)) {
0906         nfc_err(dev, "Unable to get FW GPIO\n");
0907         return PTR_ERR(phy->gpiod_fw);
0908     }
0909 
0910     pn544_hci_i2c_platform_init(phy);
0911 
0912     r = devm_request_threaded_irq(&client->dev, client->irq, NULL,
0913                       pn544_hci_i2c_irq_thread_fn,
0914                       IRQF_TRIGGER_RISING | IRQF_ONESHOT,
0915                       PN544_HCI_I2C_DRIVER_NAME, phy);
0916     if (r < 0) {
0917         nfc_err(&client->dev, "Unable to register IRQ handler\n");
0918         return r;
0919     }
0920 
0921     r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME,
0922                 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM,
0923                 PN544_HCI_I2C_LLC_MAX_PAYLOAD,
0924                 pn544_hci_i2c_fw_download, &phy->hdev);
0925     if (r < 0)
0926         return r;
0927 
0928     return 0;
0929 }
0930 
0931 static int pn544_hci_i2c_remove(struct i2c_client *client)
0932 {
0933     struct pn544_i2c_phy *phy = i2c_get_clientdata(client);
0934 
0935     cancel_work_sync(&phy->fw_work);
0936     if (phy->fw_work_state != FW_WORK_STATE_IDLE)
0937         pn544_hci_i2c_fw_work_complete(phy, -ENODEV);
0938 
0939     pn544_hci_remove(phy->hdev);
0940 
0941     if (phy->powered)
0942         pn544_hci_i2c_disable(phy);
0943 
0944     return 0;
0945 }
0946 
0947 static const struct of_device_id of_pn544_i2c_match[] __maybe_unused = {
0948     { .compatible = "nxp,pn544-i2c", },
0949     {},
0950 };
0951 MODULE_DEVICE_TABLE(of, of_pn544_i2c_match);
0952 
0953 static struct i2c_driver pn544_hci_i2c_driver = {
0954     .driver = {
0955            .name = PN544_HCI_I2C_DRIVER_NAME,
0956            .of_match_table = of_match_ptr(of_pn544_i2c_match),
0957            .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match),
0958           },
0959     .probe = pn544_hci_i2c_probe,
0960     .id_table = pn544_hci_i2c_id_table,
0961     .remove = pn544_hci_i2c_remove,
0962 };
0963 
0964 module_i2c_driver(pn544_hci_i2c_driver);
0965 
0966 MODULE_LICENSE("GPL");
0967 MODULE_DESCRIPTION(DRIVER_DESC);
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