nfc/nfcmrvl/nfcmrvl.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Marvell NFC driver
0004  *
0005  * Copyright (C) 2014-2015, Marvell International Ltd.
0006  */
0007
0008 #ifndef _NFCMRVL_H_
0009 #define _NFCMRVL_H_
0010
0011 #include <linux/platform_data/nfcmrvl.h>
0012
0013 #include "fw_dnld.h"
0014
0015 /* Define private flags: */
0016 #define NFCMRVL_NCI_RUNNING         1
0017 #define NFCMRVL_PHY_ERROR           2
0018
0019 #define NFCMRVL_EXT_COEX_ID         0xE0
0020 #define NFCMRVL_NOT_ALLOWED_ID          0xE1
0021 #define NFCMRVL_ACTIVE_ID           0xE2
0022 #define NFCMRVL_EXT_COEX_ENABLE         1
0023 #define NFCMRVL_GPIO_PIN_NFC_NOT_ALLOWED    0xA
0024 #define NFCMRVL_GPIO_PIN_NFC_ACTIVE     0xB
0025 #define NFCMRVL_NCI_MAX_EVENT_SIZE      260
0026
0027 /*
0028  * NCI FW Parameters
0029  */
0030
0031 #define NFCMRVL_PB_BAIL_OUT         0x11
0032 #define NFCMRVL_PROP_REF_CLOCK          0xF0
0033 #define NFCMRVL_PROP_SET_HI_CONFIG      0xF1
0034
0035 /*
0036  * HCI defines
0037  */
0038
0039 #define NFCMRVL_HCI_EVENT_HEADER_SIZE       0x04
0040 #define NFCMRVL_HCI_EVENT_CODE          0x04
0041 #define NFCMRVL_HCI_NFC_EVENT_CODE      0xFF
0042 #define NFCMRVL_HCI_COMMAND_CODE        0x01
0043 #define NFCMRVL_HCI_OGF             0x81
0044 #define NFCMRVL_HCI_OCF             0xFE
0045
0046 enum nfcmrvl_phy {
0047     NFCMRVL_PHY_USB     = 0,
0048     NFCMRVL_PHY_UART    = 1,
0049     NFCMRVL_PHY_I2C     = 2,
0050     NFCMRVL_PHY_SPI     = 3,
0051 };
0052
0053 struct nfcmrvl_private {
0054
0055     unsigned long flags;
0056
0057     /* Platform configuration */
0058     struct nfcmrvl_platform_data config;
0059
0060     /* Parent dev */
0061     struct nci_dev *ndev;
0062
0063     /* FW download context */
0064     struct nfcmrvl_fw_dnld fw_dnld;
0065
0066     /* FW download support */
0067     bool support_fw_dnld;
0068
0069     /*
0070      * PHY related information
0071      */
0072
0073     /* PHY driver context */
0074     void *drv_data;
0075     /* PHY device */
0076     struct device *dev;
0077     /* PHY type */
0078     enum nfcmrvl_phy phy;
0079     /* Low level driver ops */
0080     const struct nfcmrvl_if_ops *if_ops;
0081 };
0082
0083 struct nfcmrvl_if_ops {
0084     int (*nci_open) (struct nfcmrvl_private *priv);
0085     int (*nci_close) (struct nfcmrvl_private *priv);
0086     int (*nci_send) (struct nfcmrvl_private *priv, struct sk_buff *skb);
0087     void (*nci_update_config)(struct nfcmrvl_private *priv,
0088                   const void *param);
0089 };
0090
0091 void nfcmrvl_nci_unregister_dev(struct nfcmrvl_private *priv);
0092 int nfcmrvl_nci_recv_frame(struct nfcmrvl_private *priv, struct sk_buff *skb);
0093 struct nfcmrvl_private *nfcmrvl_nci_register_dev(enum nfcmrvl_phy phy,
0094                 void *drv_data,
0095                 const struct nfcmrvl_if_ops *ops,
0096                 struct device *dev,
0097                 const struct nfcmrvl_platform_data *pdata);
0098
0099
0100 void nfcmrvl_chip_reset(struct nfcmrvl_private *priv);
0101 void nfcmrvl_chip_halt(struct nfcmrvl_private *priv);
0102
0103 int nfcmrvl_parse_dt(struct device_node *node,
0104              struct nfcmrvl_platform_data *pdata);
0105
0106 #endif